GB1599155A

GB1599155A - Transmission and/or recording of digital signals

Info

Publication number: GB1599155A
Application number: GB5416276A
Authority: GB
Original assignee: Independent Broadcasting Authority
Current assignee: Independent Broadcasting Authority
Priority date: 1976-12-24
Filing date: 1976-12-24
Publication date: 1981-09-30
Also published as: JPS6217306B2; DE2757164A1; JPS53114412A; DE2757164C2

Description

(54) IMPROVEMENTS IN AND RELATING TO THE TRANSMISSION AND/OR RECORDING OF DIGITAL SIGNALS (71) We, INDEPENDENT BROADCASTING AUTHORITY, a British body corporate of 70 Brompton Road, London, S.W.3, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement : The present invention relates to the transmission and/or recording of digital signals.

One problem which exists with the transmission and/or recording of digital signals is that it is necessary to synchronise the playback apparatus with the recording or transmission apparatus. In some applications, this can be overcome by use of a separate clock signal which is recorded or transmitted separately from the information signal.

However, this solution is wasteful of bandwidth and is not viable in many circumstances.

The present invention provides a method of transmitting or recording digital signals comprising sampling an analogue signal to produce a plurality of digital words, converting each of said words to a coded word, combining said coded words together in groups with at least one but not all of said words of each group being ones complemented, there being a significant positive correlation (as hereinafter defined) between the coded words.

Features and advantages of the present invention will become apparent from the following description of an embodiment thereof when taken in conjunction with the accompanying drawings, in which: Figure 1 shows a block diagram of apparatus for producing digital signals; and Figure 2 shows a suitable code for use with the apparatus of Figure 1.

The preferred embodiment of the invention will be described in relation to its use for television video signals but it will be appreciated that the apparatus is of general use, for example for sound. When a video signal is converted to digital form the technique used herein is to sample the signal at equal time intervals and to convert each sample produced into a binary number, which will be assumed to have eight digits, the binary integer 'n' chosen can be considered to be that which makes a voltage nq most closely correspond to the sample; q a quantum, is the difference between one representable level and the next. For most purposes q would be a constant, but in some applications for example before gamma correction, it may be more advantageous for q to be a variable.

An eight digit binary number can represent the decimal numbers 0 to 255, 0 corresponding to 0000 0000 and 255 to 1111 1111. If a zero corresponds to zero volts and a '1' corresponds to one volt then for a Non-Return to zero: (NRZ) code the DC component of the digital signal can vary from 0 to 1 volt.

A further problem can arise if repetition of numbers such as 0000 0000 occurs. in this case there would be no transitions and circuits relying on recovered clock signals could get out of step.

The method and apparatus used in the preferred embodiment are designed on the basis that there is a significant correlation between closely spaced points of a television picture defined by samples. As will be described in more detail later, the apparatus transmits two words in series along a path, one of the words being the ones complement to that word. Preferably, at least some of the bits of one word are interleaved with some of the bits of the ones complement of the other word, the words relating to a spatially near point of the picture. It is assumed that there is a significant positive correlation between the uncomplemented data, and a suitable binary code chosen accordingly.

The principle is to transmit along a path one word representing one point but to transmit adjacent to it and preferably to intersperse between its digit the ones complement of another word relating say to a spatially near point of the picture; the essential requirement being an expected significant positive correlation between the un complemented data. This would also permit the use of a signal one field later for example.

Normally the two words would be numerically close to one another but this does not ensure a sufficient number of transitions. To illustrate this point consider the two words representing 127 and 128; in normal binary form these are represented as 0111 1111 and 1000 0000. The second word when complemented becomes 0111 1111 so the two words when complete interdigitated are: 00111111 11111111 which only contains one transition.

This problem may be decreased by converting the words to a suitable code before complementing the bits of one of them, and remaining in this code until the critical parts of the equipment have been passed. The problem could only be serious with words approximately i or 9 of the total range apart and even then it would additionally require the DC component of one of the words to be low.

Often parity is used for error detection and concealment. Preferably this should be 'odd' parity of an odd number of bits. This is performed by modulo 2 adding say 3 or 5 bits together and if the sum is 0 the parity is '1' and vice versa. When such a parity bit is inserted in each word this increases the minimum number of transitions.

Referring now to Figure 1, a video input is fed through a comb filter 9 to an analogue to digital converter 10 which converts the video signal into a plurality of digital words by sampling the signal at a frequency which is a multiple of the frequency of the video subcarrier, in this case at twice the video subcarrier frequency. Each word is then fed to a code converter 11 which converts the binary words to a suitable code, for example the code shown in Figure 2. This is preferably achieved using a read only memory. After code conversion, a parity bit is inserted in each word by modulo 2 adding the first three bits of the word using the EXCLUSIVE OR gates 12a, 12b. The words are then red in series through a start words inserter circuit 13 to four word latches 16a to 16d. The start words inserter circuit 13 is fed from a start words generator circuit 13a operating at line frequency which produces a digital word to identify the start of a new line of video signals. The start words are used to synchronise operation of the playback apparatus (not shown). The word latches are arranged in pairs, one of each pair passing the word exactly as it enters the latch, and the other producing the ones complement of the word entering the latch.

The operation of the part of the circuit including the latches 16a and 16b will now be described, it being understood that the other part of the circuit is identical but used alternatively. When the first word is fed through the start words inserter 13 it is fed on to output lines 14 which are connected to all the word latches. Therefore depending on which latch is being clocked, the word will enter one of the latches.

Assume that the first word is clocked into latch 16a and the second word is clocked into latch 16b. The output from the latch 16a is identical to the word fed into that latch while the output from the latch 16b is the ones complement of the word fed to that latch. The outputs from the latches 16a, 16b are then fed to a serialising and interleaving circuit 17a where the first word and the ones complement of the second word are interleaved. The degree of interleaving is determined before hand and in this case only the seventh and eighth bits of each word are interleaved as shown in the drawing. This has been found to give satisfactory results.

The degree of interleaving between the words can be altered, but this is determined by the code used. For example, the above code is not intended to be fully interleaved, in fact it was chosen so that only the seventh and eighth bits of the words would be interleaved.

The interleaved words are then fed to a recording head 18a via a record amplifier for recording the digital signals on a recording medium, preferably magnetic tape.

Referring now to Figure 2 in more detail, this shows two columns for each number, the first being the number written as a binary number and the second being the code assigned to that binary number including the paroty bit. From examination of the second column, it will be seen that for numbers between 21 and 234 inclusive, the maximum run length does not exceed three at the ends of the words and five within the words. This is acceptable only because it can be shown statistically that most words will fall between numbers 21 and 234.

Using the code shown in Figure 2, the d.c.

component is substantially reduced and so the clock signals can be recovered on playback.

The code can be used for colour video signals and although shown in a recording use, can also be used for the transmission of digital video signals.

Referring again to Figure 1, it will be seen that the digital signals are processed in two channels and that two recording heads are used one for each channel which forms the subject matter of our copending application No. 54163/76 (Serial No. 1599156). This arrangement could be altered by feeding the outputs from both channels sequentially to a single recording head.

WHAT WE CLAIM IS: 1. A method of transmitting or recording

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. complemented data. This would also permit the use of a signal one field later for example. Normally the two words would be numerically close to one another but this does not ensure a sufficient number of transitions. To illustrate this point consider the two words representing 127 and 128; in normal binary form these are represented as 0111 1111 and 1000 0000. The second word when complemented becomes 0111 1111 so the two words when complete interdigitated are: 00111111 11111111 which only contains one transition. This problem may be decreased by converting the words to a suitable code before complementing the bits of one of them, and remaining in this code until the critical parts of the equipment have been passed. The problem could only be serious with words approximately i or 9 of the total range apart and even then it would additionally require the DC component of one of the words to be low. Often parity is used for error detection and concealment. Preferably this should be 'odd' parity of an odd number of bits. This is performed by modulo 2 adding say 3 or 5 bits together and if the sum is 0 the parity is '1' and vice versa. When such a parity bit is inserted in each word this increases the minimum number of transitions. Referring now to Figure 1, a video input is fed through a comb filter 9 to an analogue to digital converter 10 which converts the video signal into a plurality of digital words by sampling the signal at a frequency which is a multiple of the frequency of the video subcarrier, in this case at twice the video subcarrier frequency. Each word is then fed to a code converter 11 which converts the binary words to a suitable code, for example the code shown in Figure 2. This is preferably achieved using a read only memory. After code conversion, a parity bit is inserted in each word by modulo 2 adding the first three bits of the word using the EXCLUSIVE OR gates 12a, 12b. The words are then red in series through a start words inserter circuit 13 to four word latches 16a to 16d. The start words inserter circuit 13 is fed from a start words generator circuit 13a operating at line frequency which produces a digital word to identify the start of a new line of video signals. The start words are used to synchronise operation of the playback apparatus (not shown). The word latches are arranged in pairs, one of each pair passing the word exactly as it enters the latch, and the other producing the ones complement of the word entering the latch. The operation of the part of the circuit including the latches 16a and 16b will now be described, it being understood that the other part of the circuit is identical but used alternatively. When the first word is fed through the start words inserter 13 it is fed on to output lines 14 which are connected to all the word latches. Therefore depending on which latch is being clocked, the word will enter one of the latches. Assume that the first word is clocked into latch 16a and the second word is clocked into latch 16b. The output from the latch 16a is identical to the word fed into that latch while the output from the latch 16b is the ones complement of the word fed to that latch. The outputs from the latches 16a, 16b are then fed to a serialising and interleaving circuit 17a where the first word and the ones complement of the second word are interleaved. The degree of interleaving is determined before hand and in this case only the seventh and eighth bits of each word are interleaved as shown in the drawing. This has been found to give satisfactory results. The degree of interleaving between the words can be altered, but this is determined by the code used. For example, the above code is not intended to be fully interleaved, in fact it was chosen so that only the seventh and eighth bits of the words would be interleaved. The interleaved words are then fed to a recording head 18a via a record amplifier for recording the digital signals on a recording medium, preferably magnetic tape. Referring now to Figure 2 in more detail, this shows two columns for each number, the first being the number written as a binary number and the second being the code assigned to that binary number including the paroty bit. From examination of the second column, it will be seen that for numbers between 21 and 234 inclusive, the maximum run length does not exceed three at the ends of the words and five within the words. This is acceptable only because it can be shown statistically that most words will fall between numbers 21 and 234. Using the code shown in Figure 2, the d.c. component is substantially reduced and so the clock signals can be recovered on playback. The code can be used for colour video signals and although shown in a recording use, can also be used for the transmission of digital video signals. Referring again to Figure 1, it will be seen that the digital signals are processed in two channels and that two recording heads are used one for each channel which forms the subject matter of our copending application No. 54163/76 (Serial No. 1599156). This arrangement could be altered by feeding the outputs from both channels sequentially to a single recording head. WHAT WE CLAIM IS:

1. A method of transmitting or recording

digital signals comprising sampling an analogue signal to produce a plurality of digital words, converting each of said words to a coded word, combining said coded words together in groups with at least one but not all of said words of each group being ones complemented, there being a significant positive correlation (as hereinbefore defined) between the coded words.

2. A method according to claim I, wherein combined coded words are interleaved.

3. A method according to claim 2, wherein two bits from each coded word are interleaved.

4. A method according to claim 1, 2 or 3 wherein a parity bit is inserted into each coded word.

5. A method according to any one of the preceding claims, wherein said converting step is achieved using a code according to Figure 2.

6. A method according to any one of the preceding claims, wherein the combined coded words are subjected to a parallel to series convertion.

7. A method according to claim 6, wherein alternate combined coded word groups are processed in separate channels.

8. A method according to any one of the preceding claims wherein each group comprises two words.

9. A method of transmitting or recording digital signals according to claim 1 substantially as hereinbefore described with reference to the accompanying drawings.

10. Apparatus for producing a digital representation of an analogue signal, comprising an analogue to digital converter for sampling the analogue signal and converting the samples into digital words, a code converter connected to the output of said analogue to digital converter for converting each of said words to a coded word, means for combining the coded words together in groups and for ones complementing at least but not all, of said coded words in each group, there being a significant positive correlation (as hereinafter defined) between the coded words.

11. Apparatus according to claim 10, wherein the combining means comprises means for performing a parallel to series conversion and for interleaving the words of the group.

12. Apparatus according to claim 10 or 11, and comprising means for inserting a parity bit into each coded word.

13. Apparatus for producing a digital representation of an analogue signal according to claim 10 substantially as hereinbefore described with reference to the accompanying drawings.

14. A recording when made according to any one of claims 1 to 9.