JP2879746B2 - Semiconductor panel - Google Patents

Description

The present invention relates to a semiconductor panel having a semiconductor element and a wiring layer, such as a thin film transistor panel used for an active matrix type liquid crystal display device.

[Conventional technology]

For example, an active matrix type liquid crystal display device used for a liquid crystal television or the like generally includes a thin film transistor panel as shown in FIG. In this thin film transistor panel, a transparent pixel electrode 2 made of an ITO film or the like and a thin film transistor 3 serving as a switching element connected to the pixel electrode 2 are formed in a matrix on an insulating substrate 1 made of glass or quartz. Are arranged in a plurality. Further, a film 10 made of chromium or tantalum is formed on the substrate 1 by sewing the pixel electrodes 2 and connecting the gate electrodes of the plurality of thin film transistors 3 in one direction (horizontal direction in the figure).
A gate line (scanning line) 4 of about 0 nm and a drain line (data line) made of chromium or tantalum similarly connecting drain electrodes of a plurality of thin film transistors 3 in a direction (vertical direction in the figure) intersecting the gate line (scanning line). 5 are arranged. Note that the gate electrode of the thin film transistor 3 is a part of the gate line 4, and these are simultaneously patterned on the substrate 1.

[Problems to be solved by the invention]

In the above-mentioned conventional thin film transistor panel, as a material of the gate line 4 (including the gate electrode of the thin film transistor) formed on the insulating substrate 1 such as glass or quartz, the adhesion to the substrate 1 is high and the surface is oxidized. Hard chrome (Cr) and tantalum (Ta) were used. However, such a thin film made of chromium or tantalum has a high resistivity. For example, the sheet resistance of a 100-nm-thick chromium film or a tantalum film formed by a sputtering device is as high as 7 to 10Ω. was there.

Therefore, the driving capability of the gate line 4 is low,
Many transistors could not be driven, and it was difficult to increase the number of pixel electrodes 2. Also,
In order to reduce the resistance of the gate line 4, the line width must be widened, which makes it difficult to increase the density. For these reasons, conventionally, high performance of the thin film transistor panel has been prevented.

On the other hand, aluminum (A
If l) is used, it is possible to reduce the resistance. However, aluminum generates hillocks due to heating, causing irregularities on the surface, and the surface is easily oxidized naturally, and a natural oxide film is formed on the surface. There is a problem that it is difficult to obtain an electrical connection with the wiring.

Note that the above-described problems have occurred not only in the thin film transistor panel but also in various fields having a metal wiring layer formed on an insulating substrate such as glass or quartz.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor panel having a wiring layer that can realize a significant reduction in resistance and that can suppress surface oxidation. To provide.

[Means for solving the problem]

The present invention is characterized in that a semiconductor element and a wiring layer connected to the semiconductor element are provided on a substrate, and the wiring layer is formed of a copper alloy containing 5 to 35% by weight of nickel. .

[Action]

Nickel-copper alloys (hereinafter, referred to as white copper) have a higher nickel content that is more excellent in adhesion to an insulating substrate and an oxidation resistance of a wheat surface, and a higher copper content has a smaller resistivity. . Therefore, by setting the nickel content to about 5 to 35% by weight, it is possible to realize a wiring material having good adhesion to the substrate and oxidation resistance of the surface and low resistivity.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a thin film transistor obtained by applying an embodiment of the present invention to a gate line (gate electrode) of a thin film transistor panel as shown in FIG.

In the figure, an insulating substrate 1 made of glass or quartz is shown.
A gate electrode 6 having a thickness of about 100 nm and made of white copper (NiCu) containing 15% by weight of nickel in copper is pattern-formed thereon. The gate line extending from the gate electrode 6 is also formed of the same material as the gate electrode 6 and has the same thickness.

The entire surface of the base 1 including the gate electrode 6 is covered with a gate insulating film 7 of a silicon nitride film (SiN) having a thickness of about 300 m.
A made of (amorphous silicon) with a film thickness of about 150 nm
-Si semiconductor layer 8 is provided. Further, on both sides of the a-Si semiconductor layer 8, a chrome layer is formed via a contact n ⁺ -a-Si semiconductor layer 9 having a film thickness of about 25 nm in which n-type impurities are mixed at a high concentration in a-Si. A source electrode 10 and a drain electrode 11 each having a thickness of about 100 nm made of aluminum or tantalum are formed, and one end of a pixel electrode 2 having a thickness of about 100 nm made of an lTO film is connected to the source electrode 10. The drain electrode
The drain line extending from 11 is also the drain electrode
The same material as 11 is used, and is formed with the same thickness.

Next, an example of a method for manufacturing the thin film transistor having the above configuration will be described below.

First, a white copper film is deposited on the entire surface of the substrate 1 by sputtering using a white copper containing 15% by weight of nickel so as to have a thickness of about 100 nm. Sputtering conditions at this time include, for example, substrate temperature
100 ° C, argon gas sputter gas, sputtering pressure 0.4Pa, DC power 100W, film formation speed 5
Use a target with a target diameter of 8 inches at 00 ° / min. Subsequently, annealing is performed at 250 ° C. for 30 minutes in a nitrogen atmosphere. Thereafter, by patterning the white copper film on the substrate 1 by photolithography, a gate electrode 6 and a gate line made of white copper are formed as shown in FIG.

Subsequent steps are the same as in the related art. That is, first, the plasma is applied over the entire surface of the substrate 1 including the gate electrode 6.
Silicon nitride film for gate insulating film 7 by CVD method, a
-Si semiconductor layer 8 for the a-Si semiconductor film, n ⁺ -a-Si film thickness, respectively n ⁺ -a-Si semiconductor film for the semiconductor layer 9 is 300 nm, 1
The layers are sequentially deposited to have a thickness of 50 nm and 25 nm. Subsequently, a metal film (chromium or tantalum) for the source and drain electrodes 10 and 11 and the drain line is deposited thereon to a thickness of about 100 nm by a sputtering method or the like. Thereafter, the metal film and the underlying n ⁺ -a-Si semiconductor film are collectively patterned by a photolithography method, so that the n ⁺ -a-Si semiconductor layer 9 and the source / drain electrodes 10 are formed.
11 and a drain line are formed. Further, the a-Si semiconductor layer 8 as a device area is formed by patterning the a-Si semiconductor film by a photolithography method. Finally, an ITO film is deposited on the entire surface by sputtering or the like so as to have a thickness of about 100 nm, and is patterned by photolithography to form the pixel electrode 2.

Since the gate electrode 6 and the gate line according to the present embodiment are made of white copper, which is a nickel-copper alloy containing 15% by weight of nickel, the adhesion to the substrate 1 is high, and the surface is naturally oxidized. Also, generation of hillocks due to heating can be prevented. Moreover, since the above-mentioned white copper has a very low resistivity as compared with conventionally used chromium and tantalum, it is possible to remarkably reduce the resistance. For example, when the sheet resistance of the above-mentioned white copper is measured using the four-probe method,
Very low Ω, sheet resistance of chrome and tantalum is 7 ~
Compared to 10Ω, it can be seen that the resistance can be greatly reduced.

As described above, since the resistance of the gate line can be remarkably reduced, the driving capability of the gate line in the thin film transistor panel is improved, a large number of thin film transistors can be driven, and the number of pixel electrodes can be increased. . Furthermore, even if the width of the gate line is considerably reduced, the resistance can be reduced as compared with the conventional gate line made of chromium or tantalum. It is possible to increase the aperture ratio by increasing the area. From these facts, in the thin film transistor panel to which this embodiment is applied, it is possible to further improve the performance as compared with the related art.

The case where the thin film transistor is used as a switching element in a display panel for a liquid crystal display device has been described above. Next, the case where the thin film transistor is used in an electric circuit will be described. For example, to MizoNaru inverter underlying element in an electric circuit of a thin film transistor, as shown in FIG. 2, so as to connect the gate G and the drain D of the thin film transistor T _2. In the figure, T ₁ is a thin film transistor for driving, T ₂ is a thin film transistor for load.

Figure 3 is a plan view of a thin film transistor T ₂ according to the another embodiment of the present invention constituting the inverter as described above, Fig. 4 A-A of the transistor section in Figure 3
FIG. 5 is a cross-sectional view, and FIG. 5 is a BB cross-sectional view of the gate-drain connection portion in FIG.

As shown in FIG. 3, on an insulating substrate 21 made of glass or quartz, a gate line 22 having a thickness of about 100 nm made of white copper containing 15% by weight of nickel is formed in the same manner as in the above embodiment. Have been. Further, a transistor portion 23 having a part of the gate line 22 as a gate electrode, and a gate electrode (gate line 22) and a drain electrode (drain line 24) of the transistor portion 23 connected through a contact hole 25. The gate-drain connection part 26 of FIG. Incidentally, 27 is connected to the drain of the thin film transistor T ₁ of the second view in the source line. Next, the structure of the transistor section 23 and the gate-drain connection section 26 will be specifically described.

In the transistor section 23, as shown in FIG. 4, a gate electrode 28 having the same material and the same thickness as the gate line 22 is formed on the substrate 21 as a part of the gate line 22. It is covered with a gate insulating film 29 made of a nitride film (SiN) and having a thickness of about 300 nm. An a-Si semiconductor layer 30 having a thickness of about 150 nm is provided in a region on the gate insulating film 29 facing the gate electrode 28, and n-type contact n-layers having a thickness of about 25 nm are further provided on both sides thereof. Through a ⁺ a-Si semiconductor layer 31 and a contact metal layer 32 made of chromium and having a thickness of about 25 nm,
A source electrode 33 and a drain electrode 34 of about m are formed.

On the other hand, in the gate-drain connection portion 26, as shown in FIG. 5, a gate line 22 extending from the gate electrode 27 is formed on the substrate 21, and the entire surface thereof is covered with the gate insulating film 29. ing. In the gate insulating film 29, a contact hole 25 extending from the surface to the upper surface of the gate line 22 is formed. The drain line 24 (see FIG. 3) extending from the drain electrode 34 forms the contact hole 25. It is connected to the gate line 22 via.

Next, an example of a method for manufacturing the thin film transistor having the above configuration will be described below.

First, a white copper film is deposited to a thickness of about 100 nm on the entire surface of the substrate 21 by a sputtering method using white copper containing 15% by weight of nickel as a target, similarly to the above-described embodiment. By patterning the white copper film by a photolithography method, as shown in FIG. 3, a gate line 22 and a gate electrode 28 made of white copper are formed.

Subsequently, a silicon nitride film, an a-Si semiconductor film, an n ⁺ -a-Si semiconductor film, and a chromium film are respectively formed on the entire surface of the substrate 21 including the gate line 22 and the gate electrode 28 by a plasma CVD method. Are sequentially deposited to be 300 nm, 150 nm, 25 nm, and 25 nm. Thereafter, the chromium film, the n ⁺ -a-Si semiconductor film, and the a-Si semiconductor film are collectively patterned using the mask pattern of the device area, so that the a-Si semiconductor layer 30 is formed in the device area. , N ⁺ -a-
The Si semiconductor layer 31 and the contact metal layer 32 are formed, and the gate insulating film 29 is exposed in other areas.

Next, a contact hole 25 is formed in the gate insulating film 29 from the surface to the gate line 22 by reactive ion etching (RIE) using a mixed gas of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ). To form Next, contact hole
After depositing an aluminum film to be the source and drain electrodes 33 and 34 and the drain line 24 to a thickness of about 400 nm on the entire surface including the inside 25 by a sputtering method or the like, the source film is patterned by patterning the aluminum film. , Drain electrodes 33 and 34 and a drain line 24, and further a contact metal layer 32 and
The n ⁺ -a-Si semiconductor layer 31 is removed by etching. Through the above steps, an inverter-structured thin film transistor having the transistor portion 23 and the gate-drain connection portion 26 is obtained.

In the present embodiment, as described above, white copper (NiCu) containing 15% by weight of nickel is used as a material of the gate line 22, so that not only the resistance of the gate line 22 can be reduced, but also the gate line 22 can be reduced. Has an advantage that the surface of the metal is hardly oxidized naturally. Therefore, when the drain line 24 is connected to the surface of the gate line 22 that is not easily oxidized through the contact hole 25 in this way, when the size of the contact hole 25 is, for example, 7 μm × 7 μm, the contact resistance is about 2Ω. To a small value. On the other hand, if an attempt is made to lower the resistance by using aluminum for the gate line, the surface is easily oxidized and a natural oxide film always exists, so that the contact resistance increases and the contact hole having the same size as above Even in the case of, it is a very large value of 3 kΩ. Therefore, according to the present embodiment, the contact resistance can be reduced to 1/1000 or less as compared with the case where aluminum is used.

In each of the above embodiments, the nickel content of the white copper used as the gate line material was 15% by weight.
Within the range of 5 to 35% by weight, the intended purpose can be sufficiently achieved.

In each of the above embodiments, the present invention is applied to a gate line. However, depending on the type of a thin film transistor, a drain line may be formed on a substrate. In such a case, the present invention is applied to the drain line. Can be applied. Further, the present invention can be applied not only to the above-described gate lines and drain lines, but also to various wiring layers formed on an insulating substrate such as glass or quartz.

〔The invention's effect〕

According to the semiconductor panel of the present invention, the use of a nickel-copper alloy (white copper) containing 5-35% by weight of nickel in copper as a material of the wiring layer achieves a significant reduction in resistance. In addition, it is possible to easily obtain an electrical connection with another wiring by suppressing the oxidation of the surface. Therefore, if the present invention is applied to various devices using a thin film transistor such as a thin film transistor panel,
Along with lowering the resistance of the wiring layer and improving the oxidation resistance of the surface,
High integration and high performance of the device can be achieved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a thin film transistor obtained by applying an embodiment of the present invention to a gate line (gate electrode) of a thin film transistor panel. FIG. 2 is a diagram showing a general inverter, which is a basic element of an electric circuit, composed of a thin film transistor. FIG. 3 is a plan view of a thin film transistor to which an inverter according to another embodiment of the present invention is applied, FIG. 4 is a cross-sectional view of the transistor section taken along line AA in FIG. 3, FIG. 5 is a cross-sectional view of B- of the gate-drain connection in FIG.
B is a cross-sectional view, and FIG. 6 is a plan view of a general thin film transistor panel used for an active matrix type liquid crystal display device. 1 ... insulating substrate, 6 ... gate electrode, 7 ... gate insulating film, 8 ... a-Si semiconductor layer, 9 ... n ⁺ -a-Si semiconductor layer, 10 ... source electrode, 11 ... Drain electrode, 21 ... insulating substrate, 22 ... gate line, 23 ... transistor part, 24 ... drain line, 25 ... contact hole,
26 ... gate-drain connection, 27 ... source line,
28 gate electrode, 29 gate insulating film, 30 a-Si
Semiconductor layer, 31 ... n ⁺ -a-Si semiconductor layer, 32 ... contact metal layer, 33 ... source electrode, 34 ... drain electrode.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/1343 G02F 1/1345 H01L 29/78 617

Claims (1)

(57) [Claims] 1. A semiconductor panel having a semiconductor element and a wiring layer connected to the semiconductor element on a substrate, wherein the wiring layer is formed of a copper alloy containing nickel in an amount of 5 to 35% by weight. .