JP3346217B2 - Wiring forming method and display device manufacturing method - Google Patents

Wiring forming method and display device manufacturing method

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Publication number
JP3346217B2
JP3346217B2 JP10078097A JP10078097A JP3346217B2 JP 3346217 B2 JP3346217 B2 JP 3346217B2 JP 10078097 A JP10078097 A JP 10078097A JP 10078097 A JP10078097 A JP 10078097A JP 3346217 B2 JP3346217 B2 JP 3346217B2
Authority
JP
Japan
Prior art keywords
content
thin film
alloy thin
resistivity
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10078097A
Other languages
Japanese (ja)
Other versions
JPH10284493A (en
Inventor
建史 神谷
純司 塩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP10078097A priority Critical patent/JP3346217B2/en
Priority to US09/047,693 priority patent/US6320138B1/en
Priority to EP98911030A priority patent/EP0922301B1/en
Priority to KR1019980709822A priority patent/KR100314865B1/en
Priority to CA002256378A priority patent/CA2256378A1/en
Priority to DE69831846T priority patent/DE69831846T2/en
Priority to CNB988004151A priority patent/CN1224099C/en
Priority to PCT/JP1998/001361 priority patent/WO1998045881A1/en
Priority to TW087105072A priority patent/TW388187B/en
Publication of JPH10284493A publication Critical patent/JPH10284493A/en
Priority to HK99106200A priority patent/HK1021071A1/en
Application granted granted Critical
Publication of JP3346217B2 publication Critical patent/JP3346217B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Conductive Materials (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は配線の形成方法及
び表示装置の製造方法に関する。The present invention relates to a method for forming a wiring and a method for manufacturing a display device.

【０００２】[0002]

【従来の技術】例えば、アクティブマトリックス型の液
晶表示装置には、図１０に示すように、走査ライン１及
びデータライン２等からなる配線を備えているととも
に、走査ライン１とデータライン２の各交点近傍に画素
電極３及びスイッチング素子としての薄膜トランジスタ
４を備えたものがある。この場合、薄膜トランジスタ４
のゲート電極Ｇは走査ライン１に接続され、ドレイン電
極Ｄはデータライン２に接続され、ソース電極Ｓは画素
電極３に接続されている。2. Description of the Related Art For example, as shown in FIG. 10, an active matrix type liquid crystal display device is provided with a wiring composed of a scanning line 1 and a data line 2 and the like. Some include a pixel electrode 3 and a thin film transistor 4 as a switching element near the intersection. In this case, the thin film transistor 4
The gate electrode G is connected to the scanning line 1, the drain electrode D is connected to the data line 2, and the source electrode S is connected to the pixel electrode 3.

【０００３】次に、図１１は図１０の薄膜トランジスタ
４の部分の断面図を示したものである。ガラス基板１１
の上面の所定の箇所にはゲート電極Ｇを含む走査ライン
１が形成され、その表面には陽極酸化膜１２が形成さ
れ、その上面全体にはゲート絶縁膜１３が形成されてい
る。ゲート絶縁膜１３の上面の所定の箇所でゲート電極
Ｇに対応する部分にはアモルファスシリコンからなる半
導体薄膜１４が形成されている。半導体薄膜１４の上面
の中央部にはブロッキング層１５が形成されている。半
導体薄膜１４及びブロッキング層１５の上面の両側には
ｎ+シリコンからなるオーミックコンタクト層１６、１
７が形成されている。オーミックコンタクト層１６、１
７の各上面にはドレイン電極Ｄ及びソース電極Ｓが形成
されている。また、これら電極Ｄ、Ｓの形成と同時にデ
ータライン２が形成されている。ゲート絶縁膜１３の上
面の所定の箇所には画素電極３がソース電極Ｓに接続さ
れて形成されている。画素電極１１の所定の部分を除く
上面全体にはパッシベーション膜１８が形成されてい
る。FIG. 11 is a sectional view of the thin film transistor 4 shown in FIG. Glass substrate 11
A scanning line 1 including a gate electrode G is formed at a predetermined position on the upper surface of the substrate, an anodic oxide film 12 is formed on the surface thereof, and a gate insulating film 13 is formed on the entire upper surface. A semiconductor thin film 14 made of amorphous silicon is formed in a portion corresponding to the gate electrode G at a predetermined location on the upper surface of the gate insulating film 13. A blocking layer 15 is formed at the center of the upper surface of the semiconductor thin film 14. Ohmic made of a semiconductor thin film 14 and on both sides of the upper surface of the blocking layer 15 n + silicon contact layer 16,1
7 are formed. Ohmic contact layer 16, 1
7, a drain electrode D and a source electrode S are formed. The data line 2 is formed simultaneously with the formation of the electrodes D and S. The pixel electrode 3 is formed at a predetermined position on the upper surface of the gate insulating film 13 so as to be connected to the source electrode S. A passivation film 18 is formed on the entire upper surface of the pixel electrode 11 except for a predetermined portion.

【０００４】ところで、ゲート電極Ｇを含む走査ライン
１からなる配線の材料としては、Ｔｉ等の高融点金属を
含有するＡｌ合金を用いることが知られている（例え
ば、特開平４−１３０７７６号公報参照）。この場合、
ＡｌにＴｉ等の高融点金属を含有させるのは、Ａｌ単体
の耐熱性が十分でなく、後工程の加熱工程においてヒロ
ックが発生するのを抑制するためである。このように、
耐ヒロック特性を考慮するのは、例えば、ゲート電極Ｇ
を含む走査ライン１上に形成されるゲート絶縁膜１３の
絶縁耐圧が低下しないようにするためである。It is known that an Al alloy containing a refractory metal such as Ti is used as a material of a wiring composed of the scanning lines 1 including the gate electrode G (for example, Japanese Patent Laid-Open No. 4-130776). reference). in this case,
Al is made to contain a high melting point metal such as Ti in order to prevent the heat resistance of Al alone from being sufficient and to suppress generation of hillocks in a heating step in a later step. in this way,
Considering the hillock resistance, for example, the gate electrode G
This is to prevent the withstand voltage of the gate insulating film 13 formed on the scanning line 1 including the above from decreasing.

【０００５】しかるに、本発明者がＡｌ−Ｔｉ合金薄膜
を用いて実験を行ったところ、次に述べるような結果が
得られた。まず、Ａｌ−Ｔｉ合金薄膜の抵抗率のＴｉ含
有率依存性について調べたところ、図５に示す結果が得
られた。この図において、実線はスパッタリング法や蒸
着法により、基板温度を室温として、ガラス基板上に成
膜したＡｌ−Ｔｉ合金薄膜の抵抗率を示し、点線、一点
鎖線、二点鎖線はそれぞれ上記室温成膜のＡｌ−Ｔｉ合
金薄膜に対して２５０℃、３００℃、３５０℃の各温度
で熱処理を行った後の各Ａｌ−Ｔｉ合金薄膜の抵抗率を
示す。図５から明らかなように、すべてのＡｌ−Ｔｉ合
金薄膜において、Ｔｉ含有率が増加するほど、抵抗率が
高くなる。また、熱処理温度が高いほど、抵抗率が低く
なる。この結果、Ａｌ−Ｔｉ合金薄膜の抵抗率はＴｉ含
有率が小さいほど低くなり、かつ熱処理温度が高いほど
低くなることが確認された。However, the present inventor conducted an experiment using an Al—Ti alloy thin film, and obtained the following results. First, when the dependency of the resistivity of the Al—Ti alloy thin film on the Ti content was examined, the results shown in FIG. 5 were obtained. In this figure, the solid line shows the resistivity of the Al—Ti alloy thin film formed on the glass substrate by sputtering or vapor deposition at a substrate temperature of room temperature. The resistivity of each Al-Ti alloy thin film after heat-treating the film at 250 ° C, 300 ° C, and 350 ° C is shown. As is clear from FIG. 5, in all the Al—Ti alloy thin films, the resistivity increases as the Ti content increases. Also, the higher the heat treatment temperature, the lower the resistivity. As a result, it was confirmed that the resistivity of the Al—Ti alloy thin film was lower as the Ti content was lower, and was lower as the heat treatment temperature was higher.

【０００６】次に、Ａｌ−Ｔｉ合金薄膜の耐ヒロック特
性について調べたところ、図６に示す結果が得られた。
この図において、横軸はＴｉ含有率を表し、縦軸はヒロ
ック発生温度を表している。ただし、ここでのヒロック
発生温度とは、１００倍程度の顕微鏡観察により、高さ
０．５〜１μｍ以上のヒロックが発生したときの熱処理
温度をいう（以下、同じ）。図６から明らかなように、
熱処理温度が例えば２５０℃の場合、Ｔｉ含有率が３ａ
ｔ％以上であると、ヒロックの発生は抑制される。した
がって、耐ヒロック特性を考慮すると、熱処理温度が２
５０℃の場合、Ｔｉ含有率は３ａｔ％以上とすることが
望ましい。しかしながら、図５において点線で示す熱処
理温度２５０℃の場合には、Ｔｉ含有率が３ａｔ％以上
であると、抵抗率が１８μΩｃｍ程度以上となる。換言
すれば、耐ヒロック特性を考慮した場合、Ｔｉ含有率を
３ａｔ％以下とすることは好ましくなく、ひいては配線
（ゲート電極Ｇを含む走査ライン１）の抵抗率を１８μ
Ωｃｍ程度以下とすることができない。一方、最近で
は、液晶表示装置の高精細化や高開口率化等に伴って、
配線のより一層の低抵抗化が要求されている。このた
め、最近では、耐ヒロック特性が良く、しかも抵抗率を
１０μΩｃｍ程度以下とすることができる、Ｎｄ等の希
土類元素を含有するＡｌ合金が注目されている（例え
ば、特開平７−４５５５５号公報参照）。Next, when the hillock resistance of the Al—Ti alloy thin film was examined, the results shown in FIG. 6 were obtained.
In this figure, the horizontal axis represents the Ti content, and the vertical axis represents the hillock generation temperature. However, the hillock generation temperature here refers to a heat treatment temperature when a hillock having a height of 0.5 to 1 μm or more is generated by microscopic observation of about 100 times (hereinafter the same). As is clear from FIG.
When the heat treatment temperature is, for example, 250 ° C., the Ti content is 3a.
When it is at least t%, generation of hillocks is suppressed. Therefore, considering the hillock resistance, the heat treatment temperature is 2
In the case of 50 ° C., the Ti content is desirably 3 at% or more. However, at a heat treatment temperature of 250 ° C. indicated by a dotted line in FIG. 5, if the Ti content is 3 at% or more, the resistivity becomes about 18 μΩcm or more. In other words, in consideration of the hillock resistance, it is not preferable to set the Ti content to 3 at% or less, and thus, the resistivity of the wiring (the scanning line 1 including the gate electrode G) to 18 μm.
It cannot be less than about Ωcm. On the other hand, recently, with the increase in the definition and the aperture ratio of the liquid crystal display device,
There is a demand for further lowering the resistance of the wiring. For this reason, recently, an Al alloy containing a rare earth element such as Nd, which has good hillock resistance and a resistivity of about 10 μΩcm or less, has attracted attention (for example, Japanese Patent Application Laid-Open No. H7-45555). reference).

【０００７】しかるに、本発明者がＡｌ−Ｎｄ合金薄膜
を用いて実験を行ったところ、次に述べるような結果が
得られた。まず、Ａｌ−Ｎｄ合金薄膜の抵抗率のＮｄ含
有率依存性について調べたところ、図７に示す結果が得
られた。この図において、実線はスパッタリング法や蒸
着法により、基板温度を室温として、ガラス基板上に成
膜したＡｌ−Ｎｄ合金薄膜の抵抗率を示し、点線、一点
鎖線、二点鎖線はそれぞれ上記室温成膜のＡｌ−Ｎｄ合
金薄膜に対して２５０℃、３００℃、３５０℃の各温度
で熱処理を行った後の各Ａｌ−Ｎｄ合金薄膜の抵抗率を
示す。図７から明らかなように、すべてのＡｌ−Ｎｄ合
金薄膜において、Ｎｄ含有率が増加するほど、抵抗率が
高くなる。また、熱処理温度が高いほど、抵抗率が低く
なる。そして、Ｎｄ含有率が例えば２〜４ａｔ％の場合
には、熱処理を行ったすべてのＡｌ−Ｎｄ合金薄膜の抵
抗率が１０μΩｃｍ程度以下となる。この結果、Ａｌ−
Ｎｄ合金薄膜の抵抗率を１０μΩｃｍ程度以下とするこ
とができることが確認された。However, the present inventor conducted an experiment using an Al—Nd alloy thin film, and obtained the following results. First, the dependence of the resistivity of the Al—Nd alloy thin film on the Nd content was examined, and the results shown in FIG. 7 were obtained. In this figure, the solid line shows the resistivity of the Al-Nd alloy thin film formed on a glass substrate by sputtering or vapor deposition at a substrate temperature of room temperature. The resistivity of each Al-Nd alloy thin film after heat treatment at 250 ° C, 300 ° C, and 350 ° C for the Al-Nd alloy thin film of the film is shown. As is clear from FIG. 7, in all the Al—Nd alloy thin films, the resistivity increases as the Nd content increases. Also, the higher the heat treatment temperature, the lower the resistivity. When the Nd content is, for example, 2 to 4 at%, the resistivity of all the heat-treated Al—Nd alloy thin films becomes about 10 μΩcm or less. As a result, Al-
It has been confirmed that the resistivity of the Nd alloy thin film can be reduced to about 10 μΩcm or less.

【０００８】次に、Ａｌ−Ｎｄ合金薄膜の耐ヒロック特
性について調べたところ、図８に示す結果が得られた。
この図において、横軸はＮｄ含有率を表し、縦軸はヒロ
ック発生温度を表している。図８から明らかなように、
熱処理温度が例えば２５０℃の場合、Ｎｄ含有率が少量
でも、ヒロックの発生は抑制される。この結果、Ｎｄ含
有率が例えば２〜４ａｔ％の場合には、ヒロックの発生
は抑制される上、図７の点線（熱処理温度２５０℃）で
示すように、抵抗率が１０μΩｃｍ程度以下となること
が確認された。Next, when the hillock resistance of the Al—Nd alloy thin film was examined, the result shown in FIG. 8 was obtained.
In this figure, the horizontal axis represents the Nd content, and the vertical axis represents the hillock occurrence temperature. As is clear from FIG.
When the heat treatment temperature is, for example, 250 ° C., the generation of hillocks is suppressed even if the Nd content is small. As a result, when the Nd content is, for example, 2 to 4 at%, the generation of hillocks is suppressed, and the resistivity becomes about 10 μΩcm or less as shown by a dotted line (heat treatment temperature 250 ° C.) in FIG. Was confirmed.

【０００９】ところで、Ａｌ−Ｎｄ合金薄膜の耐ピンホ
ール特性について調べたところ、図９に示す結果が得ら
れた。この図において、横軸はＮｄ含有率を表し、縦軸
はピンホール発生温度を表している。ただし、ここでの
ピンホール発生温度とは、１００倍程度の顕微鏡観察に
より、１ｃｍ2当たり１０個以上のピンホールが発生し
たときの熱処理温度をいう（以下、同じ）。図９から明
らかなように、ピンホール発生温度は、Ｎｄ含有率４ａ
ｔ％程度以下において２５０℃よりも低く、Ｎｄ含有率
４ａｔ％程度以上において２５０℃程度でほぼ平行して
いる。したがって、耐ピンホール特性を考慮すると、熱
処理温度が２５０℃の場合、Ｎｄ含有率は４ａｔ％程度
以上とすることが望ましい。しかしながら、ピンホール
発生温度がＮｄ含有率４ａｔ％程度以上において２５０
℃程度でほぼ平行しているので、熱処理温度が２５０℃
以上の場合、Ｎｄ含有率をいくら増やしても、断線の原
因となる耐ピンホール特性に対する信頼性があまりない
ということが分かった。また、耐ピンホール特性を考慮
してＮｄ含有率を４ａｔ％程度以上とすると、図７にお
いて点線で示す熱処理温度２５０℃の場合には、抵抗率
が１０μΩｃｍ程度以上となってしまうということも分
かった。When the pinhole resistance of the Al—Nd alloy thin film was examined, the results shown in FIG. 9 were obtained. In this figure, the horizontal axis represents the Nd content, and the vertical axis represents the pinhole generation temperature. Here, the pinhole generation temperature refers to a heat treatment temperature when 10 or more pinholes are generated per 1 cm 2 by microscopic observation of about 100 times (hereinafter the same). As is clear from FIG. 9, the pinhole generation temperature is lower than the Nd content 4a.
The temperature is lower than 250 ° C. at about t% or less, and substantially parallel at about 250 ° C. at about 4 at% or more of Nd content. Therefore, in consideration of the pinhole resistance, when the heat treatment temperature is 250 ° C., the Nd content is desirably about 4 at% or more. However, when the pinhole generation temperature is about 4 at% or more for the Nd content, 250
Approximately parallel at about ℃, heat treatment temperature is 250 ℃
In the above case, it was found that no matter how much the Nd content was increased, there was not much reliability with respect to the anti-pinhole property which causes disconnection. Further, when the Nd content is set to about 4 at% or more in consideration of the pinhole resistance, it is also found that the resistivity becomes about 10 μΩcm or more at the heat treatment temperature of 250 ° C. indicated by the dotted line in FIG. Was.

【００１０】[0010]

【発明が解決しようとする課題】以上のように、Ａｌ−
Ｔｉ合金薄膜からなる配線の場合には、耐ヒロック特性
を考慮すると、Ｔｉ含有率を３ａｔ％以下とすることは
好ましくなく、ひいては抵抗率を１８μΩｃｍ程度以下
とすることができないという問題があった。一方、Ａｌ
−Ｎｄ合金薄膜からなる配線の場合には、Ｎｄ含有率を
４ａｔ％以上としても、断線の原因となる耐ピンホール
特性に対する信頼性があまりない上、耐ピンホール特性
を考慮してＮｄ含有率を４ａｔ％以上とすると、図７の
点線（熱処理温度２５０℃）で示すように、抵抗率が１
０μΩｃｍ程度以上となってしまうという問題があっ
た。この発明の課題は、抵抗率をＡｌ−Ｔｉ合金薄膜の
場合と同程度以下とすることができる上、ヒロック及び
ピンホールの発生を抑制することができるようにするこ
とである。As described above, Al-
In the case of a wiring made of a Ti alloy thin film, considering the hillock resistance, it is not preferable to set the Ti content to 3 at% or less, and there is a problem that the resistivity cannot be reduced to about 18 μΩcm or less. On the other hand, Al
-In the case of a wiring made of an Nd alloy thin film, even if the Nd content is set to 4 at% or more, there is not much reliability with respect to the pinhole resistance which causes disconnection, and the Nd content is considered in consideration of the pinhole resistance. Is 4 at% or more, as shown by the dotted line (heat treatment temperature 250 ° C.) in FIG.
There was a problem that it was about 0 μΩcm or more. It is an object of the present invention to reduce the resistivity to about the same as or less than that of an Al—Ti alloy thin film, and to suppress the occurrence of hillocks and pinholes.

【００１１】[0011]

【課題を解決するための手段】この発明は、Ｎｄおよび
Ｔｉの含有率が、それぞれ０．１ａｔ％以上で、合計で
は１．５ａｔ％以下であるＡｌ合金を室温で成膜し、２
４０℃〜２７０℃の温度で熱処理を行うようにしたもの
である。Means for Solving the Problems] The present invention, the content of Nd and Ti, respectively 0.1 at% or more, the Al alloy is not more than 1.5 at% in total formed at room temperature, 2
The heat treatment is performed at a temperature of 40 ° C to 270 ° C.

【００１２】この発明によれば、配線を例えばＡｌ−Ｎ
ｄ−Ｔｉ合金薄膜によって形成すると、抵抗率をＡｌ−
Ｔｉ合金薄膜の場合と同程度以下とすることができる
上、ヒロック及びピンホールの発生を抑制することがで
きる。According to the present invention, the wiring is made of, for example, Al-N
When formed by a d-Ti alloy thin film, the resistivity becomes Al-
The thickness can be reduced to about the same level as or less than that of the Ti alloy thin film, and the generation of hillocks and pinholes can be suppressed.

【００１３】[0013]

【発明の実施の形態】本発明者は、図１に示すこの発明
の一実施形態のように、スパッタリング法や蒸着法によ
り、基板温度を室温として、ガラス基板（透明絶縁基
板）２１上に成膜したＡｌ−Ｎｄ−Ｔｉ合金薄膜（配
線）２２について、いくつかの実験を行った。まず、上
記のように基板温度を室温として成膜したＡｌ−Ｎｄ−
Ｔｉ合金薄膜の抵抗率のＮｄ含有率及びＴｉ含有率依存
性について調べたところ、図２に示す結果が得られた。
ただし、Ｎｄ含有率及びＴｉ含有率の最小値は共に０．
１ａｔ％とした。この図において、抵抗率は、領域Ａ1
で１０μΩｃｍ以下であり、領域Ａ2で１０〜２０μΩ
ｃｍであり、領域Ａ3で２０〜３０μΩｃｍであり、領
域Ａ4で３０〜４０μΩｃｍであり、領域Ａ5で４０〜５
０μΩｃｍであり、領域Ａ6で５０〜６０μΩｃｍであ
り、領域Ａ7で６０〜７０μΩｃｍである。図２から明
らかなように、Ｎｄ含有率及びＴｉ含有率が増加するほ
ど、抵抗率が高くなることが分かる。また、基板温度を
室温として成膜したＡｌ−Ｎｄ−Ｔｉ合金薄膜の抵抗率
を１０μΩｃｍ程度以下とする場合には、Ｎｄ含有率及
びＴｉ含有率を領域Ａ1から適宜に選択すれば良いこと
が分かる。なお、同抵抗率を２０μΩｃｍ程度以下とす
る場合には、Ｎｄ含有率及びＴｉ含有率を領域Ａ1及び
Ａ2から適宜に選択すれば良いことも分かる。BEST MODE FOR CARRYING OUT THE INVENTION The inventor of the present invention formed a substrate on a glass substrate (transparent insulating substrate) 21 at a room temperature by sputtering or vapor deposition as in one embodiment of the present invention shown in FIG. Several experiments were performed on the formed Al—Nd—Ti alloy thin film (wiring) 22. First, as described above, the Al-Nd-
When the dependency of the resistivity of the Ti alloy thin film on the Nd content and the Ti content was examined, the results shown in FIG. 2 were obtained.
However, the minimum values of the Nd content and the Ti content are both 0.1.
It was 1 at%. In this figure, the resistivity is in the region A 1
10 μΩcm or less in the area A 2 and 10 to 20 μΩcm in the area A2.
cm, and a 20~30μΩcm in the area A 3, in the area A 4 is 30～40Myuomegacm, in the area A 5 40 to 5
A 0Myuomegacm, a 50~60μΩcm in the area A 6, a 60~70μΩcm in region A 7. As can be seen from FIG. 2, the resistivity increases as the Nd content and the Ti content increase. Also, when the resistivity of the Al-Nd-Ti alloy thin film formed as a room at a substrate temperature of more than about 10μΩcm may be a Nd content and Ti content may be selected appropriately from the area A 1 I understand. When the resistivity is set to about 20 μΩcm or less, it can be seen that the Nd content and the Ti content may be appropriately selected from the regions A 1 and A 2 .

【００１４】次に、Ａｌ−Ｎｄ−Ｔｉ合金薄膜の耐ヒロ
ック特性のＮｄ含有率及びＴｉ含有率依存性について調
べたところ、図３に示す結果が得られた。この図におい
て、ヒロック発生温度は、領域Ｂ1で２４０〜２７０℃
であり、領域Ｂ2で２７０〜３００℃であり、領域Ｂ3で
３００〜３３０℃であり、領域Ｂ4で３３０〜３６０℃
である。図３から明らかなように、熱処理温度が２４０
〜２７０℃の場合には、領域Ｂ1においてヒロックの発
生は抑制されることが分かる。Next, when the dependency of the hillock resistance of the Al—Nd—Ti alloy thin film on the Nd content and the Ti content was examined, the results shown in FIG. 3 were obtained. In this figure, hillock occurrence temperature is in the region B 1 240 to 270 ° C.
270 to 300 ° C. in the region B 2 , 300 to 330 ° C. in the region B 3 , and 330 to 360 ° C. in the region B 4.
It is. As is clear from FIG.
In the case of to 270 ° C., the generation of hillocks in the region B 1 represents understood to be inhibited.

【００１５】次に、Ａｌ−Ｎｄ−Ｔｉ合金薄膜の耐ピン
ホール特性のＮｄ含有率及びＴｉ含有率依存性について
調べたところ、図４に示す結果が得られた。この図にお
いて、ピンホール発生温度は、領域Ｃ1で２４０〜２７
０℃であり、領域Ｃ2で２７０〜３００℃であり、領域
Ｃ3で３００〜３３０℃であり、領域Ｃ4で３３０〜３６
０℃である。図４から明らかなように、熱処理温度が２
４０〜２７０℃の場合には、領域Ｃ1においてピンホー
ルの発生は抑制されることが分かる。Next, the dependence of the pinhole resistance of the Al—Nd—Ti alloy thin film on the Nd content and the Ti content was examined. The results shown in FIG. 4 were obtained. In this figure, the pinhole occurrence temperature is in the region C 1 two hundred and forty to twenty-seven
0 ° C., 270 to 300 ° C. in the region C 2 , 300 to 330 ° C. in the region C 3 , and 330 to 36 ° C. in the region C 4 .
0 ° C. As is clear from FIG.
In the case of forty to two hundred seventy ° C., the formation of pinholes in the region C 1 it is seen to be inhibited.

【００１６】ここで、一例として、Ｎｄ含有率を０．７
５ａｔ％とし、Ｔｉ含有率を０．５ａｔ％とすると、図
３では領域Ｂ1と領域Ｂ2との境界部分であり、図４では
領域Ｃ1と領域2との境界部分であり、したがって熱処理
温度を２４０〜２７０℃とすると、ヒロック及びピンホ
ールの発生は抑制されることになる。しかも、Ｎｄ含有
率を０．７５ａｔ％とし、Ｔｉ含有率を０．５ａｔ％と
すると、図２では領域Ａ1（１０μΩｃｍ以下）内であ
り、基板温度を室温として成膜したＡｌ−Ｎｄ−Ｔｉ合
金薄膜の場合における抵抗率を８μΩｃｍ程度とするこ
とができる。なお、熱処理した場合には、図５及び図７
から類推すると、抵抗率を８μΩｃｍ程度よりもさらに
低くすることができる。換言すれば、熱処理した場合に
は、図２における領域Ａ1（１０μΩｃｍ以下）が領域
Ａ2側に広がることになるので、Ｎｄ含有率とＴｉ含有
率の合計を１．５ａｔ％程度以下（ただし、Ｎｄ含有率
及びＴｉ含有率は共に０．１ａｔ％以上）とすると、熱
処理後のＡｌ−Ｎｄ−Ｔｉ合金薄膜の抵抗率を１０μΩ
ｃｍ程度以下とすることができる。また、この合計含有
率（１．５ａｔ％程度以下）の範囲では、図３及び図４
から明らかなように、熱処理温度が２４０〜２７０℃の
場合、ヒロック及びピンホールの発生はほぼ抑制される
ことになる。Here, as an example, the Nd content is set to 0.7.
Assuming that the content of Ti is 5 at% and the content of Ti is 0.5 at%, it is the boundary between the region B 1 and the region B 2 in FIG. 3 and the boundary between the region C 1 and the region 2 in FIG. When the temperature is 240 to 270 ° C., generation of hillocks and pinholes is suppressed. Moreover, assuming that the Nd content is 0.75 at% and the Ti content is 0.5 at%, the Al-Nd-Ti film formed within the region A 1 (10 μΩcm or less) in FIG. The resistivity in the case of an alloy thin film can be about 8 μΩcm. Note that, when heat treatment was performed, FIGS.
By analogy with this, the resistivity can be made even lower than about 8 μΩcm. In other words, when the heat treatment is performed, the region A 1 (10 μΩcm or less) in FIG. 2 spreads to the region A 2 side, so that the total of the Nd content and the Ti content is about 1.5 at% or less (however, , Nd content and Ti content are each 0.1 at% or more), the resistivity of the Al—Nd—Ti alloy thin film after the heat treatment is set to 10 μΩ.
cm or less. 3 and 4 in the range of the total content (about 1.5 at% or less).
As is clear from the above, when the heat treatment temperature is 240 to 270 ° C., generation of hillocks and pinholes is almost suppressed.

【００１７】次に、Ａｌ−Ｎｄ−Ｔｉ合金薄膜の抵抗率
をＡｌ−Ｔｉ合金薄膜の場合と同様に１８μΩｃｍ程度
とする場合について説明する。まず、図２に示すよう
に、Ｎｄ含有率とＴｉ含有率の合計を例えば３．５ａｔ
％程度以下（ただし、Ｎｄ含有率及びＴｉ含有率は共に
０．１ａｔ％以上）とすると、基板温度を室温として成
膜したＡｌ−Ｎｄ−Ｔｉ合金薄膜の抵抗率が２０μΩｃ
ｍ程度以下となる。一方、この合計含有率（３．５ａｔ
％程度以下）の範囲では、図３及び図４から明らかなよ
うに、熱処理温度が２４０〜２７０℃の場合には、ヒロ
ックまたはピンホールがやや発生するが、熱処理温度が
高くなるほどヒロックまたはピンホールの発生は抑制さ
れることになる。また、この場合も、熱処理すると、図
５及び図７から類推して、抵抗率を２０μΩｃｍ程度よ
りも低くすることができる。換言すれば、熱処理する
と、この場合のＡｌ−Ｎｄ−Ｔｉ合金薄膜の抵抗率を１
８μΩｃｍ程度以下とすることができる。Next, a case where the resistivity of the Al—Nd—Ti alloy thin film is set to about 18 μΩcm as in the case of the Al—Ti alloy thin film will be described. First, as shown in FIG. 2, the total of the Nd content and the Ti content is, for example, 3.5 at.
% Or less (however, both the Nd content and the Ti content are 0.1 at% or more), the resistivity of the Al—Nd—Ti alloy thin film formed at a substrate temperature of room temperature is 20 μΩc.
m or less. On the other hand, the total content (3.5 at
3 and 4, hillocks or pinholes occur slightly when the heat treatment temperature is 240 to 270 ° C., but as the heat treatment temperature increases, the hillocks or pinholes increase. Is suppressed. Also in this case, when the heat treatment is performed, the resistivity can be made lower than about 20 μΩcm by analogy with FIGS. 5 and 7. In other words, when the heat treatment is performed, the resistivity of the Al—Nd—Ti alloy thin film in this case becomes 1
It can be about 8 μΩcm or less.

【００１８】ここで、Ａｌ−Ｎｄ−Ｔｉ合金薄膜のＮｄ
含有率について考察する。例えば、図４の領域Ｃ1で
は、熱処理温度が２４０〜２７０℃の場合、Ｎｄ含有率
に関係なく、ピンホールが発生する。一方、図３の領域
Ｂ1では、熱処理温度が２４０〜２７０℃の場合、Ｎｄ
含有率１ａｔ％弱以下で、ヒロックが発生する。したが
って、Ｎｄ含有率は、ピンホールの発生をあまり考慮す
る必要はなく、ヒロックの発生を考慮すればよく、１ａ
ｔ％程度としてもよい。Ｎｄ含有率を１ａｔ％程度とし
た場合には、抵抗率を考慮すると、図２から明らかなよ
うに、Ｔｉ含有率は０．１〜２ａｔ％程度が好ましく、
さらには０．１〜０．５ａｔ％程度がより好ましい。Here, the Nd of the Al—Nd—Ti alloy thin film
Consider the content. For example, in the area C 1 of FIG. 4, the heat treatment temperature is the case of 240 to 270 ° C., regardless Nd content, pinholes. On the other hand, in the region B 1 in FIG. 3, when the heat treatment temperature is 240 to 270 ° C., Nd
When the content is less than 1 at%, hillocks are generated. Therefore, the Nd content does not need to consider much the occurrence of pinholes, but only the generation of hillocks.
It may be about t%. In the case where the Nd content is about 1 at%, considering the resistivity, as apparent from FIG. 2, the Ti content is preferably about 0.1 to 2 at%,
Furthermore, about 0.1 to 0.5 at% is more preferable.

【００１９】ところで、Ａｌ−Ｔｉ合金薄膜の場合に
は、図５及び図６に示すように、低抵抗化と耐ヒロック
特性（熱処理温度２５０℃）を考慮すると、Ｔｉ含有率
は２．９ａｔ％程度が好ましい。一方、Ａｌ−Ｎｄ合金
薄膜の場合には、図７及び図９に示すように、低抵抗化
と耐ピンホール特性（熱処理温度２５０℃）を考慮する
と、Ｎｄ含有率は４ａｔ％程度が好ましい。これに対し
て、Ａｌ−Ｎｄ−Ｔｉ合金薄膜の場合には、上述したよ
うに、ＮｄとＴｉの合計含有率を１．５ａｔ％程度以下
とすることができる。したがって、Ａｌ−Ｎｄ−Ｔｉ合
金薄膜の場合には、Ｔｉ単体またはＮｄ単体を含有する
Ａｌ合金薄膜と比較して、高価なＮｄ及びＴｉの含有率
を少なくすることができ、ひいてはコストの低減を図る
こともできる。By the way, in the case of an Al—Ti alloy thin film, as shown in FIGS. 5 and 6, considering the low resistance and the hillock resistance (heat treatment temperature of 250 ° C.), the Ti content is 2.9 at%. The degree is preferred. On the other hand, in the case of an Al—Nd alloy thin film, as shown in FIGS. 7 and 9, the Nd content is preferably about 4 at% in consideration of low resistance and pinhole resistance (heat treatment temperature of 250 ° C.). On the other hand, in the case of the Al—Nd—Ti alloy thin film, as described above, the total content of Nd and Ti can be set to about 1.5 at% or less. Therefore, in the case of the Al-Nd-Ti alloy thin film, the content of expensive Nd and Ti can be reduced as compared with the Al alloy thin film containing Ti alone or Nd alone, and the cost can be reduced. You can also plan.

【００２０】なお、上記説明では、この発明の配線を表
示装置に適用した場合について説明したが、表示装置以
外の配線にも幅広く適用することができる。また、薄膜
トランジスタのゲート電極を含む走査ラインに限らず、
ソース電極、ドレイン電極及びデータラインにも適用す
ることができる。この場合、図１１を参照して説明する
と、ゲート絶縁膜４上にＡｌ−Ｎｄ−Ｔｉ合金薄膜から
なるデータライン等をパターン形成するとき、ＩＴＯか
らなる画素電極１１がＡｌエッチング液によって侵され
るのを防止するために、ゲート絶縁膜４上にｎ+シリコ
ン層やクロム層等を形成し、その上にデータライン等を
形成するためのＡｌ−Ｎｄ−Ｔｉ合金薄膜を形成するよ
うにしてもよい。さらに、Ａｌ−Ｎｄ−Ｔｉ合金薄膜に
限らず、希土類元素のうちの１種または２種以上とＴ
ｉ、Ｔａ、Ｍｏ、Ｃｒ、Ａｕ、Ａｇ、Ｃｕのうちの１種
または２種以上とを含有するＡｌ合金薄膜によって配線
を形成するようにしてもよい。In the above description, the case where the wiring of the present invention is applied to a display device has been described. However, the present invention can be widely applied to wiring other than the display device. In addition, not limited to the scanning line including the gate electrode of the thin film transistor,
The present invention can be applied to a source electrode, a drain electrode, and a data line. In this case, referring to FIG. 11, when a data line or the like made of an Al—Nd—Ti alloy thin film is formed on the gate insulating film 4, the pixel electrode 11 made of ITO is affected by the Al etchant. In order to prevent this, an n + silicon layer, a chromium layer, or the like may be formed on the gate insulating film 4, and an Al—Nd—Ti alloy thin film for forming a data line or the like may be formed thereon. . Further, not only the Al—Nd—Ti alloy thin film but also one or more of the rare earth elements and T
The wiring may be formed by an Al alloy thin film containing one or more of i, Ta, Mo, Cr, Au, Ag, and Cu.

【００２０】[0020]

【発明の効果】以上説明したように、この発明によれ
ば、配線を例えばＡｌ−Ｎｄ−Ｔｉ合金薄膜によって形
成すると、抵抗率をＡｌ−Ｔｉ合金薄膜の場合と同程度
以下とすることができる上、ヒロック及びピンホールの
発生を抑制することができる。As described above, according to the present invention, when the wiring is formed of, for example, an Al—Nd—Ti alloy thin film, the resistivity can be made equal to or less than that of the Al—Ti alloy thin film. In addition, generation of hillocks and pinholes can be suppressed.

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明の一実施形態における配線の断面図。FIG. 1 is a sectional view of a wiring according to an embodiment of the present invention.

【図２】Ａｌ−Ｎｄ−Ｔｉ合金薄膜の抵抗率のＮｄ含有
率及びＴｉ含有率依存性を示す図。FIG. 2 is a graph showing the dependency of the resistivity of an Al—Nd—Ti alloy thin film on the Nd content and the Ti content.

【図３】Ａｌ−Ｎｄ−Ｔｉ合金薄膜の耐ヒロック特性の
Ｎｄ含有率及びＴｉ含有率依存性を示す図。FIG. 3 is a graph showing dependence of hillock resistance of an Al—Nd—Ti alloy thin film on Nd content and Ti content.

【図４】Ａｌ−Ｎｄ−Ｔｉ合金薄膜の耐ピンホール特性
のＮｄ含有率及びＴｉ含有率依存性を示す図。FIG. 4 is a graph showing the dependence of the pinhole resistance of an Al—Nd—Ti alloy thin film on the Nd content and the Ti content.

【図５】Ａｌ−Ｔｉ合金薄膜の抵抗率のＴｉ含有率依存
性を示す図。FIG. 5 is a diagram showing the Ti content dependency of the resistivity of an Al—Ti alloy thin film.

【図６】Ａｌ−Ｔｉ合金薄膜の耐ヒロック特性を示す
図。FIG. 6 is a diagram showing hillock resistance of an Al—Ti alloy thin film.

【図７】Ａｌ−Ｎｄ合金薄膜の抵抗率のＮｄ含有率依存
性を示す図。FIG. 7 is a graph showing the dependence of the resistivity of an Al—Nd alloy thin film on the Nd content.

【図８】Ａｌ−Ｎｄ合金薄膜の耐ヒロック特性を示す
図。FIG. 8 is a graph showing hillock resistance of an Al—Nd alloy thin film.

【図９】Ａｌ−Ｎｄ合金薄膜の耐ピンホール特性を示す
図。FIG. 9 is a diagram showing pinhole resistance characteristics of an Al—Nd alloy thin film.

【図１０】従来の液晶表示装置の一部の回路図。FIG. 10 is a circuit diagram of a part of a conventional liquid crystal display device.

【図１１】図１０の薄膜トランジスタの部分の断面図。11 is a cross-sectional view of a portion of the thin film transistor of FIG.

【符号の説明】[Explanation of symbols]

２１ ガラス基板 ２２ Ａｌ−Ｎｄ−Ｔｉ合金薄膜 21 glass substrate 22 Al-Nd-Ti alloy thin film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 29/786 Ｈ０１Ｌ 21/88 Ｎ Ｈ０５Ｋ 1/09 29/78 ６１２Ｃ ６１７Ｍ (56)参考文献 特開 平８−250494（ＪＰ，Ａ) 特開 平５−65631（ＪＰ，Ａ) 特開 平７−142478（ＪＰ，Ａ) 特開 平４−130776（ＪＰ，Ａ) 特開 平10−60636（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/3205 G02F 1/1343 G09F 9/30 338 H01B 1/02 H01L 21/28 301 H01L 29/786 H05K 1/09 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI H01L 29/786 H01L 21/88 N H05K 1/09 29/78 612C 617M (56) References JP-A-8-250494 (JP, A) JP-A-5-65631 (JP, A) JP-A-7-142478 (JP, A) JP-A-4-130776 (JP, A) JP-A-10-60636 (JP, A) (58) Survey Fields (Int.Cl. 7 , DB name) H01L 21/3205 G02F 1/1343 G09F 9/30 338 H01B 1/02 H01L 21/28 301 H01L 29/786 H05K 1/09

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】ＮｄとＴｉとを含有するＡｌ合金からなる
配線の形成方法であって、ＮｄおよびＴｉの含有率が、
それぞれ０．１ａｔ％以上で、合計では１．５ａｔ％以
下であるＡｌ合金を室温で成膜し、２４０℃〜２７０℃
の温度で熱処理を行うことを特徴とする配線の形成方
法。1. A method for forming a wiring made of an Al alloy containing Nd and Ti, wherein the content of Nd and Ti is
Respectively 0.1 at% or more, the Al alloy is not more than 1.5 at% in total formed at room temperature, 240 ° C. to 270 ° C.
A method of forming a wiring, wherein a heat treatment is performed at a temperature of 1 . 【請求項２】スイッチング素子に結合される配線の少な
くとも一部をＮｄとＴｉとを含有するＡｌ合金で形成し
たアクティブ型の表示装置の製造方法であって、Ｎｄお
よびＴｉの含有率が、それぞれ０．１ａｔ％以上で、合
計では１．５ａｔ％以下であるＡｌ合金を室温で成膜
し、２４０℃〜２７０℃の温度で熱処理を行うことを特
徴とする表示装置の製造方法。2. A method for manufacturing an active display device in which at least a part of a wiring coupled to a switching element is formed of an Al alloy containing Nd and Ti, wherein the contents of Nd and Ti are respectively A method for manufacturing a display device, comprising: forming an Al alloy of not less than 0.1 at% and not more than 1.5 at% in total at room temperature, and performing heat treatment at a temperature of 240 to 270 ° C.
JP10078097A 1997-04-04 1997-04-04 Wiring forming method and display device manufacturing method Expired - Fee Related JP3346217B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP10078097A JP3346217B2 (en) 1997-04-04 1997-04-04 Wiring forming method and display device manufacturing method
US09/047,693 US6320138B1 (en) 1997-04-04 1998-03-25 Substrate with conductor formed of low-resistance aluminum alloy
KR1019980709822A KR100314865B1 (en) 1997-04-04 1998-03-26 Substrates with conductors formed from low-resistance aluminum alloys
CA002256378A CA2256378A1 (en) 1997-04-04 1998-03-26 Substrate with conductor formed of low-resistance aluminum alloy
DE69831846T DE69831846T2 (en) 1997-04-04 1998-03-26 SUBSTRATE WITH LADDER OF ALUMINUM ALLOY WITH LOW RESISTANCE
CNB988004151A CN1224099C (en) 1997-04-04 1998-03-26 Substrate with conductor formed of low-resistance aluminum alloy
EP98911030A EP0922301B1 (en) 1997-04-04 1998-03-26 Substrate with conductor formed of low-resistance aluminum alloy
PCT/JP1998/001361 WO1998045881A1 (en) 1997-04-04 1998-03-26 Substrate with conductor formed of low-resistance aluminum alloy
TW087105072A TW388187B (en) 1997-04-04 1998-04-03 Substrate with conductor formed of low-resistance aluminum alloy
HK99106200A HK1021071A1 (en) 1997-04-04 1999-12-30 Substrate with conductor formed of low-resistance aluminum alloy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10078097A JP3346217B2 (en) 1997-04-04 1997-04-04 Wiring forming method and display device manufacturing method

Publications (2)

Publication Number Publication Date
JPH10284493A JPH10284493A (en) 1998-10-23
JP3346217B2 true JP3346217B2 (en) 2002-11-18

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Country Status (10)

Country Link
US (1) US6320138B1 (en)
EP (1) EP0922301B1 (en)
JP (1) JP3346217B2 (en)
KR (1) KR100314865B1 (en)
CN (1) CN1224099C (en)
CA (1) CA2256378A1 (en)
DE (1) DE69831846T2 (en)
HK (1) HK1021071A1 (en)
TW (1) TW388187B (en)
WO (1) WO1998045881A1 (en)

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Also Published As

Publication number Publication date
CN1223014A (en) 1999-07-14
EP0922301A1 (en) 1999-06-16
TW388187B (en) 2000-04-21
DE69831846T2 (en) 2006-05-18
JPH10284493A (en) 1998-10-23
KR100314865B1 (en) 2002-02-28
CA2256378A1 (en) 1998-10-15
HK1021071A1 (en) 2000-05-26
KR20000016250A (en) 2000-03-25
CN1224099C (en) 2005-10-19
WO1998045881A1 (en) 1998-10-15
EP0922301B1 (en) 2005-10-12
DE69831846D1 (en) 2005-11-17
US6320138B1 (en) 2001-11-20

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