JP2835220B2 - Personal computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer capable of saving program capacity by efficiently turning on or off a clock.

[0002]

2. Description of the Related Art Clock on / off operations in a conventional personal computer are shown in FIGS. In the normal processing routine other than the interrupt processing, as shown in FIG. 4, before the application program enters a state of waiting for input of a device such as a K / B or a mouse (step 3), the operation clock is operated at a low speed to enable the interrupt. I do. On the other hand, in the interrupt processing routine, as shown in FIG. 5, the operation clock is operated at high speed (step 4), and each device processing is performed (step 5). In the device input waiting state of the normal processing routine and the interrupt processing routine, when processing is performed on the device, the interrupt processing routine is given control over the normal processing routine, so that a routine that always operates the operation clock at a high speed is provided. Driven.

[0003]

In a conventional personal computer, the operating clock is increased in the interrupt processing routine. Therefore, as the number of interrupt processes increases, the operating clock is increased in each interrupt processing routine. Therefore, there is a problem that the program capacity is increased due to the necessity of performing.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve these problems. When a device such as an input means, a timer and an output means is driven, an interrupt is generated and the normal processing routine temporarily stops. In a personal computer controlled by the central controller so that the device processing is executed by the interrupt processing routine, and when the device processing ends, the normal processing routine is prohibited. Means, a low-speed clock means for lowering the operation clock when the interrupt prohibiting means operates, a halt instruction for temporarily stopping the central controller until a device is input, and a halt instruction when an interrupt is generated by the device input. A high-speed clock that releases instructions and increases the operating clock speed And a personal computer having interrupt permitting means for enabling the interrupt disabled state, wherein when the interrupt prohibiting is enabled by the interrupt permitting means, an interrupt processing routine executes an interrupt process that occurs after a halt instruction. .

[0005]

According to the personal computer constructed as described above, interrupts are prohibited in processing routines other than the interrupt processing, the operation clock is reduced, the halt instruction is executed while waiting for device input, and then the operation clock is increased. After that, whenever an interrupt is generated due to the configuration that enables the interrupt, the processing speed is increased and then the device processing, which is the interrupt processing routine, is performed. it can.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. FIG. 1 is a diagram corresponding to claims of a personal computer showing one embodiment of the present invention, FIG. 2 is a flowchart for controlling a normal process of the personal computer showing one embodiment of the present invention, and FIG. FIG. 4 is a flow chart for controlling a normal processing of a conventional personal computer, and FIG. 5 is a flow chart for controlling an interrupt processing of a conventional personal computer. It is a flowchart. In FIG.
The personal computer of the present invention has an input means 50 for inputting data and a RAM 4 for storing the input data.
0, the ROM 30 storing the program, and the RO
A central processing unit 60 for controlling according to the program instructions stored in M30, a clock 80 for driving the personal computer of the present invention, and a low-speed clock means 10 for lowering the clock speed;
Conversely, high-speed clock means 20 for increasing the clock speed, and output means 7 for outputting the processing result
0 and a timer 95 that counts time in real time
And transmission / reception means 110 for transmitting / receiving data to / from another computer.

The operation will be described with reference to FIGS. 1, 2 and 3. The personal computer according to the embodiment of the present invention has a timer interrupt, a K / B interrupt, a transmission interrupt, and a reception interrupt function for improving the efficiency of data processing. An interrupt is generated at regular time intervals counted by 95, and a K / B interrupt causes a K / B
An interrupt occurs, a transmission interrupt generates a transmission interrupt when data is transmitted, and a reception interrupt generates a reception interrupt when data is received. As described above, respective interrupts are generated in a state of waiting for device input. Therefore, since an interrupt processing routine is required for each device, four types of interrupt processing routines are required in this case.

The present invention utilizes a halt instruction provided in the central processing unit 60 to execute an instruction next to the halt instruction when an interrupt occurs in a state where the interrupt is disabled in a normal processing other than the interrupt processing routine. This is characterized by utilizing a unique function of the central processing unit 60.

FIGS. 2 and 3 illustrate the operation of waiting for device input. In a normal processing routine other than the interrupt processing routine, the interrupt processing is prohibited by the interrupt prohibiting means 90 shown in FIG. 1 (step 10). In the state where the interrupt is prohibited, the speed of the clock 80 is reduced by the low-speed clock means 10 shown in FIG. 1 (step 2).
0). Thereafter, the halt instruction is executed in a state of waiting for device input (step 30), and the speed of the clock 80 is increased by the high-speed clock means 20 shown in FIG. 1 (step 40). Further, the interrupt is enabled by the interrupt permitting means 100 shown in FIG. 1 (step 5).
0). In the interrupt processing routine shown in FIG. 3, the above-described timer interrupt, K / B interrupt, transmission interrupt, and reception interrupt processing are performed (step 60).

If an interrupt occurs in such a device input wait state, the interrupt processing routine is not immediately processed, and the speed of the clock 80 by the high-speed clock means 20, which is the instruction following the halt instruction, is increased (step 40). ), An interrupt processing routine is performed. Therefore, in each interrupt processing routine, the clock 80
Since it is no longer necessary to increase the speed of
The program can be simplified and the capacity can be reduced.

In a conventional personal computer, when an interrupt occurs in a state where the device is not waiting for a device input, a process for increasing the speed of the clock 80 is performed in both the normal processing routine other than the interrupt processing routine and the interrupt processing routine. I have. In the personal computer of the present invention, the processing speed is increased because the processing for increasing the speed of the clock 80 is not performed on both sides.

[0012]

As described above, the present invention utilizes the halt instruction provided in the central processing unit to execute the instruction following the halt instruction when an interrupt occurs while the interrupt is disabled. By using the specific functions of the processing device, the program can be simplified and the capacity can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram corresponding to a claim of a personal computer showing one embodiment of the present invention.

FIG. 2 is a flowchart illustrating control of normal processing of a personal computer according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating control of interrupt processing of a personal computer according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating control of normal processing of a conventional personal computer.

And FIG. 5 is a flowchart for controlling interrupt processing of a conventional personal computer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Low-speed clock means 20 High-speed clock means 30 ROM 40 RAM 50 Input means 60 Central processing unit 70 Output means 80 Clock 90 Interrupt prohibition means 95 Timer 100 Interrupt permission means 110 Transmission / reception means

Claims (1)

(57) [Claims] 1. An input means, a timer and an output means.
When the device is driven, an interrupt occurs and the normal processing routine
From an interrupt handling routine.
Device processing is executed, and when this device processing ends,
Also, the central control unit is set to return to the normal processing routine.
Smell controlled by a personal computer
In the normal processing routine, the interrupt disabling procedure
And the operation clock is activated when the interrupt inhibiting means is activated.
Slow clock means to slow down and device input
Halt command to temporarily stop the central control unit until
When an interrupt is generated by this device input, this home
High-speed clock to release the
Interrupt means for enabling the interrupt disabled state.
And interrupt prohibition by the interrupt permitting means.
Halt instruction in the interrupt handling routine when
A personal computer characterized by executing an interrupt process that has occurred after a command .