JPH0421148A - Control system for issue of input/output instruction and interruption acknowledge - Google Patents

Abstract

PURPOSE:To remove useless power failure time by providing the system with an order control means and controlling receiving/issuing order between an I/O instruction and an interruption acknowledge (ACK) corresponding to the same channel device number. CONSTITUTION:The order control means 37 controls the receiving/issuing order of an I/O instruction and an interruption ACK signal which correspond to the same channel device number outputted from a central processing unit(CPU) 1. The means 37 issues the I/O instruction and the interruption ACK signal in the channel device CH2 in accordance with the receiving order. When the I/O instruction and the ACK signal corresponding to the same channel number obtained from the CPU 1 are simultaneously included in a channel control device 3, their receiving order is stored. The stored order is serialized to guarantee the receiving order of the channel device CH2. Since the CPU 1 can execute rejecting operation, useless processing aborting time can be removed and the performance of the system can be improved.

Description

[Detailed Description of the Invention] [Summary] A mechanism for controlling input/output commands and 5 interrupt processing, etc. via a bus for a plurality of channel devices (C)l) in an information processing device, such as a channel control Interrupt control method in the unit (CHC), especially input/output commands and 5 interrupt response signals (IACK signals) for the same channel device (CH)
Regarding the issuance control method, the order of input/output commands and 5 interrupt response signals (IACK signals) to the channel device (CI) is determined by
It is managed by the channel control unit (CHC) between the central processing unit (CP[I) and the channel control unit (CHC).
This eliminates the need for interlock control between the central processing unit (CPU) and the wasted processing stop time caused by the interlock control in the central processing unit (CPU).
), the purpose of this is to improve the performance of input/output commands and one interrupt response signal (IACK) for the same channel device number from the central processing unit (CPU).
means for controlling the signals (signals) according to the reception order on the channel device (CH) side of the number, that is, means for storing the reception order and serializing the issuing order,
The reception for the channel device (CH) is configured to guarantee order.

[Industrial Application Field] The present invention provides a method for controlling a plurality of channel devices (C8
), a configuration that controls input/output commands and one interrupt processing via a bus, such as a channel control unit (CHC).
Interrupt control schemes in co-channel devices (C
I/O commands and 9 interrupt response signals (IAC
This invention relates to a method for controlling the issuance of K signals.

Due to the diversification of data processing and the increase in the amount of processing performed by recent information processing devices, there is a demand for improvements in the processing capabilities of the information processing devices, and there is a trend toward connecting various input/output devices.

Conventionally, each input/output device is connected to a channel device (C
The input/output commands for 1() and the interrupt response signal (IA (J signal) for interrupts from the channel device (CH) are interlocked between the central processing unit (CPU) and the channel device (CH). The order is guaranteed.

With this interlock control, for example, if some of the various input/output devices connected to the information processing device are low-speed, it may have a large impact on the performance of the central processing unit (CPU). Therefore, there is a need for an interrupt control method that can guarantee the order in which input/output commands and nine interrupt responses are issued without having the central processing unit (CPU) itself monitor the order.

[Prior Art and Problems to be Solved by the Invention] FIG. 2 is a diagram illustrating a conventional input/output command and 9-interrupt response signal issuance control system.

In the conventional circuit example shown in Fig. 2, 1 is a central processing unit (C
PU), 32 is the cPU interface section in the f-p channel control unit (CHC), 33 is the bus control section, and 35 is the central processing unit (CPU).
Similarly, a flip-flop circuit (hereinafter referred to as FF) 36 that holds the request for sending out the ACK signal) is connected to the central processing unit (
CPU) F that holds requests for sending input/output commands from 1.
It is F. Then, a central processing bag fi (CPIJ) 1 and a CPU interface section 32. And bus control section 33
and channel device (cH) 2 are bus 5,
Connected by 4.

The FF output signal shown in 35.36 above is transmitted to the hash control unit 33, and passes through the bus 4 between the channel control device 1f (CHC) and the channel device (CFI) to the channel device (C) 2. will be forwarded to.

The FFs 35 and 36 are set by the CPU interface section 32 in response to instructions from the central processing unit (CPU) 1, and receive and receive a transfer end signal to the channel device f (CI() 2) from the bus control section 33. will be reset.

At this time, the hash control unit 33 normally processes the requests in the order in which they are received.
H) If CPU 2 is busy due to access from another central processing unit (CPU) 1,
The request will be canceled and retried after a certain period of time, and the request will be processed in the meantime. Therefore, the order of the input/output command and one interrupt response signal (IACK signal) may be reversed.

Therefore, in the conventional system, the channel device (CH)
The input/output commands for 2 and the interrupt response signal (IACK signal) for 1 were interlocked between the central processing unit (CPU) 1 and the channel device (C8) 2 to guarantee their order.

Specifically, an interlock mechanism 10 in the central processing unit (CPU) 1 causes the central processing unit (CPU) 1 to accept and add an interrupt signal before transmitting the interrupt response signal (I).
The processing in the central processing unit (CPIt) 1 is stopped until it is confirmed by receiving the IACK confirmation signal from the bus control unit 33 that the ACK signal) has arrived at the channel device (CFRI 2). , the same channel equipment?I (CI)
The order of interrupt processing for 2 and primary input/output instructions was guaranteed. Therefore, this has been an obstacle to improving the performance of the central processing unit (CPU) 1.

In view of the above-mentioned conventional drawbacks, the present invention provides a central processing unit (CPU)
) to the channel device (CI()), the order of input/output commands and one interrupt response (IACK signal) is managed by the central processing unit (CPU) and the channel control device (CHC) located between the channel device (CH). and the central processing unit (
By eliminating the need for interlock control between the central processing unit (CPU) and the channel device (CFI), wasteful processing stop time of the central processing unit (CPU) due to the interlock control is eliminated, and the central processing unit (CPU) It is an object of the present invention to provide a control method for issuing an input/output instruction 1 interrupt response that can improve the performance of the input/output instruction.

[Means to solve the problem]

(1) A control mechanism (channel control device) that controls input/output commands and one interrupt processing from a central processing unit (CPU) via a bus to multiple channel devices (CH) within an information processing device. CHC) ), the above central processing unit! A sequence control means is provided for issuing input/output commands and one interrupt response signal (IACK signal) from the (CPU) to the same channel device number in the order in which they are received on the channel device f (CH) side of that number. and, by the order control means, the same channel device (CH)
It is configured to control the reception 9 issuance order between the input/output command and one interrupt response (IACK) for the input/output command.

(2) As the above order control means, a central processing unit (CPU)
) is provided with a flip-flop (FF) that is set or reset by an interrupt response signal (IACK signal) or an input/output command from
The interrupt response signal (IACK signal) is generated by the output of F).
and input/output instructions.

[Effect]

That is, according to the present invention, a control mechanism (channel control device) that controls input/output commands and one interrupt processing, etc., for a plurality of channel devices (CH) within an information processing device, for example, via a general-purpose bus. CHC) ), the central processing unit (
A control unit, for example, a central A flip-flop (FF) that is set or reset by an interrupt response signal (IACK signal) from the processing unit (CPII) or an input/output command is provided, and the same channel from the central processing unit (CPU) is provided. When an input/output command for a number and a 9 interrupt response signal (IACK signal) are present on the channel control device (CHC) at the same time, the reception is performed by storing the order and serializing the issuing order.
Reception at (CH) guarantees order.

Therefore, the central processing unit (CPU) and the channel unit (CH
), there is no need to perform interlock control between
The central processing unit (CPU) can perform a so-called unrestricted operation, eliminating wasteful processing stop time, and as a result, the performance of the information processing apparatus can be improved.

(Embodiment) Embodiments of the present invention will be described in detail with reference to the drawings.9 FIG. 1 is a diagram showing an embodiment of the present invention, in which input/output commands and interrupt response signals ( IA
CK) according to the reception order on the channel device (CH) side of the number. When interrupt response signals (IACK signals) are simultaneously present on the channel control device (CRC) 3, the reception order in the channel device (CH) 2 is memorized and the issuing order is serialized. Means for ensuring this is a necessary means for implementing the present invention.

Note that the same reference numerals indicate the same objects throughout the figures.

The interrupt response of the present invention will be explained below with reference to FIG.

Also, a method for controlling the issuance of input/output commands will be explained.

The embodiment shown in FIG. 1 is characterized by input/output commands and 9
An FF 37 is provided for serializing an interrupt response signal (hereinafter referred to as an IACK signal) according to the reception timing. By setting when the input/output command is received and resetting when receiving the input/output command, when the FF 37 is 1",
It is possible to operate so that the input/output command comes first, and the IACK signal comes first when it is 0.

The gates 38 and 310 are inserted with conditions for transmitting an IACK signal transfer request to the bus control unit 33, and the F of the present invention is
If F37 is 01', there is an input/output command request, and the channel device numbers (CO-NO,) match, the IACK signal transfer request is suppressed.

Similarly, the gates 39 and 311 insert conditions for transmitting requests for input/output commands, such that the FF 37 is at °0'' and the IA
If there is a CK signal transfer request and the channel device numbers (CEI-Ni1) match, the input/output command transfer request is suppressed.

In this way, FF 37. Gate 38,310.39,3
By adding 11 circuits, regardless of the status of bus 4 or channel device (C)l) 2, the first one to receive the same channel number will receive the next one until the request from the one that made the request is completely completed. requests are suppressed, so the order can be guaranteed.

Of course, for input/output commands with different channel numbers or interrupt response signals, the gates 38 and 39 always
Since it is open, it is not subject to the order control of the present invention.
The same transfer operation as before will be performed.

As described above, the present invention provides a method for controlling a plurality of channel devices (CH) in an information processing device, for example, in a channel control unit (CHC) that controls input/output commands and 5 interrupt processing via a general-purpose bus. Interrupt control method, in particular, to control the order of issuance of input/output commands and one interrupt response signal (IACK signal) to the same channel device (CH), the method for controlling the same channel device number from the central processing unit (CPtl) , a control means 37 is provided for issuing an input/output command and a 9-interrupt response signal CIACK) in the order in which the channel device (CH) side of the number receives the input/output command and a 9-interrupt response signal CIACK. When signals (IACK signals) exist simultaneously on the channel control device (CHC) 3, the reception at the channel device (C1() 2) remembers the order and serializes the issuing order. The feature is that it is guaranteed.

〔Effect of the invention〕

As described above in detail, the input/output command 1 interrupt response issuance control method of the present invention allows input/output commands to be issued to a plurality of channel devices (CH) within an information processing device, for example, via a general-purpose bus. The interrupt control method in the channel control unit (CHC) that controls 1 interrupt processing, etc., especially the same one that controls the issuance of input/output commands and 9 interrupt response signals (IACK signals) to the same channel device (CO). The input/output command and 1 interrupt response signal (■^CM signal) for the channel device number are sent to the channel device W (CH
) side, that is, a means for storing the receiving order and serializing the issuing order, so as to guarantee the receiving order for the channel device (CH). This eliminates the need for interlock control between the central processing unit (CP[I) and the channel device (CH), and the central processing unit (CPU) can perform unrestricted operations. This has the effect of eliminating wasteful processing stop time and improving the performance of the information processing device.

[Brief explanation of the drawing]

While FIG. 1 shows an embodiment of the present invention, FIG. 2 is a diagram illustrating a conventional input/output command and one interrupt response signal issuance control system. In the drawings, 1 is a central processing unit (CPU) and 10 is an interlock control mechanism. 2 is a channel device (C8). 3 is a channel control device (CFIC) or a mechanism that controls interrupt processing. The input/output command 32 is a CPU interface section 33 is a bus control section. 35 is a flip-flop (FF) that holds an IACK signal transmission request; 36 is a flip-flop (FF) that holds a request for sending an input/output instruction. 37 is a flip-flop (FF) or order control means for serializing input/output instructions and IACK signals. 38. 39, 310, 311 are gates. are shown respectively.

Claims (2)

[Claims] (1) Multiple channel devices (CH) (
2) is connected to the central processing unit (CP) via the bus (4).
U) In the control mechanism (3) that controls input/output commands from (1) and interrupt processing, input/output commands for the same channel device number from the central processing unit (CPU) (1), Interrupt response signal (
IACK signal) and the channel device (CH) with the corresponding number (
2) order control means (3) for issuing according to the order of reception on the side;
7) is provided, and the order control means (37) controls the reception and issuance order between the input/output command to the same channel device (CH) (2) and the interrupt response (IACK). Features input/output commands and interrupt response issuance control method. (2) As the sequence control means (37), a flip-flop (FF) is set or reset by an interrupt response signal (IACK signal) from the central processing unit (CPU) (1) or an input/output command. (37),
By the output of the flip-flop (FF) (37),
2. The input/output command and interrupt response issuing control method according to claim 1, wherein the issuing order of the interrupt response signal (IACK signal) and the input/output command is controlled.