JP2510031B2 - I / O instruction, interrupt response issuance control method - Google Patents

Description

DETAILED DESCRIPTION [Overview] A mechanism for controlling input / output commands and interrupt processing via a bus for a plurality of channel devices (CH) in an information processing device, such as a channel control unit (CH). CHC) interrupt control method, especially the issue control method of input / output instruction and interrupt response signal (IACK signal) to the same channel device (CH), regarding input / output instruction and interrupt response signal to channel device (CH) (IACK signal) order, central processing unit (CPU)
Is managed by the channel controller (CHC) between the channel processor (CH) and the channel processor (CH), and the interlock control between the central processor (CPU) and the channel processor (CH) is not required, and the central processor In order to improve the performance of the central processing unit (CPU) by eliminating unnecessary processing stop time in the interlock control in the (CPU), the same channel device from the central processing unit (CPU) A means for controlling an input / output command and an interrupt response signal (IACK signal) for a number in the order of reception on the channel device (CH) side of the number, that is, storing the acceptance order and setting the issue order. A means for serializing is provided to ensure the order of acceptance for the channel device (CH).

[Industrial applications]

The present invention provides a plurality of channel devices (C
H), a configuration for controlling input / output commands and interrupt processing via a bus, for example, a channel controller (CHC)
Interrupt control method in, especially co-channel devices (C
H)), I / O instruction, and interrupt response signal (IACK signal) issue control method.

Due to the recent diversification of data processing and the increase in processing amount of information processing apparatuses, it is required to improve the processing capability of the information processing apparatuses, while various input / output devices are being connected.

Conventionally, the input / output command for the channel device (CH) to which each input / output device is connected and the interrupt response signal (IACK signal) for the interrupt from the channel device (CH) are the central processing unit (CPU) and the channel device. The order is guaranteed by interlocking with (CH).

In this interlock control, for example, if various types of input / output devices connected to the information processing device have a low speed, the performance of the central processing unit (CPU) may be significantly affected. Therefore, there is a need for an interrupt control method capable of guaranteeing the issuing order without the central processing unit (CPU) itself monitoring the order of input / output instructions and interrupt responses.

[Problems to be Solved by Conventional Techniques and Inventions]

FIG. 2 is a diagram for explaining a conventional input / output instruction and an interrupt response signal issuing control system.

In the conventional circuit example shown in FIG. 2, 1 is a central processing unit (CPU), 32 is a CPU interface unit in a channel control unit (CHC), 33 is a bus control unit, and 35 is a central processing unit (CHU).
Similarly, a flip-flop circuit (hereinafter referred to as FF) 36 for holding an interrupt response signal (IACK signal) transmission request from the CPU is an FF for holding an input / output instruction transmission request from the central processing unit (CPU) 1. . And the central processing unit (CPU)
1, the CPU interface unit 32, the bus control unit 33, and the channel device (CH) 2 are connected by buses 5 and 4, respectively.

The output signals of the FFs indicated by 35 and 36 are transmitted to the bus control unit 33, and the channel control device (CHC) -channel device (C
It is transferred to the channel device (CH) 2 through the bus 4 between H).

The FFs 35 and 36 are set by the CPU interface unit 32 in response to an instruction from the central processing unit (CPU) 1, and a transfer end signal to the channel device (CH) 2 is received from the bus control unit 33 and reset.

At this time, the bus control unit 33 normally performs the processing in the order in which the requests are received.
H) 2 is busy due to access from another central processing unit (CPU) 1, etc., the bus request is temporarily withdrawn, and retry is made after a certain period of time. Process of request. Therefore, the order of the input / output instruction and the interrupt response signal (IACK signal) may be interchanged.

Therefore, in the conventional method, the channel device (CH) 2
Input / output instruction for and interrupt response signal (IACK signal)
Is a central processing unit (CPU) 1 and a channel device (CH) 2
The order was guaranteed by interlocking between.

Specifically, after the central processing unit (CPU) 1 accepts the interrupt signal by the interlock mechanism 10 in the central processing unit (CPU) 1, the above interrupt response signal (IACK signal)
Until it reaches the channel device (CH) 2 by receiving the IACK confirmation signal from the bus control unit 33 and confirming that the same process is stopped by the central processing unit (CPU) 1. The order of interrupt processing for the channel device (CH) 2 and the next input / output instruction was guaranteed. Therefore, it has been an obstacle to improving the performance of the central processing unit (CPU) 1.

In view of the above-mentioned conventional drawbacks, the present invention is directed to a central processing unit (CP
I / O command from U) to the channel device (CH),
The order of interrupt response (IACK signal) is controlled by the central processing unit (CP
U) and the channel control unit (CH) between the channel control unit (CHC), and by eliminating the interlock control between the central processing unit (CPU) and the channel unit (CH), It is possible to provide an input / output instruction and interrupt response issuance control method that can improve the performance of the central processing unit (CPU) by eliminating unnecessary processing stop time of the central processing unit (CPU) due to the interlock control. It is intended.

[Means for solving the problem]

(1) A control mechanism that controls input / output commands from a central processing unit (CPU) and interrupt processing via a bus for a plurality of channel devices (CH) in an information processing device {channel control device ( CHC)}, the input / output instruction and the interrupt response signal (IACK signal) for the same channel device number from the central processing unit (CPU) are received in the order of reception on the channel device (CH) side of the number. A sequence control means for issuing as follows is provided, and the same channel device (CH) is provided by the sequence control means.
It is configured to control the receiving and issuing order between the above-mentioned input / output instruction and the interrupt response (IACK).

(2) As the sequence control means, a central processing unit (CP
U) An interrupt response signal (IACK signal) or a flip-flop (FF) that is set or reset by an input / output instruction is provided, and an interrupt response signal (IACK) is output by the flip-flop (FF). Signal) and the input / output signal issuance sequence is controlled.

[Action]

That is, according to the present invention, a control mechanism (channel control device (channel control device (CH)) that controls input / output commands and interrupt processing for a plurality of channel devices (CH) in the information processing device, for example, via a general-purpose bus. CHC)}, an input / output instruction and an interrupt response signal (IACK signal) for the same channel device number from the central processing unit (CPU)
And a control means for issuing the numbers in the order of reception on the side of the channel device (CH), such as a central processing unit (CPU)
I / O command from the central processing unit (CPU) to the same channel number by providing a flip-flop (FF) that is set or reset by an interrupt response signal (IACK signal) from And the interrupt response signal (IACK signal) exist on the channel controller (CHC) at the same time, the acceptance order in the channel device (CH) is stored by storing the acceptance order and serializing the issue order. Is guaranteed.

Therefore, central processing unit (CPU) and channel unit (CH)
There is no need to perform interlock control between the central processing unit (CPU) and the CPU, so that the central processing unit (CPU) can perform so-called push-out operation, wasteful processing stop time is eliminated, and the performance of the information processing apparatus is improved as a result. There is an effect that can be made.

〔Example〕

 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an implementation order of the present invention, in which an input / output command and an interrupt response signal (IACK) for the same channel device number are sent by the channel device (CH) side of the number. By providing the order control means 37 for issuing according to the reception order,
When an input / output instruction for the same channel number from the central processing unit (CPU) and an interrupt response signal (IACK signal) are simultaneously present on the channel control unit (CHC) 3,
Means for guaranteeing the order of acceptance in the channel device (CH) 2 by storing the order of acceptance and serializing the order of issue is a necessary means for implementing the present invention.
Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, referring to FIG. 1, the interrupt response of the present invention, and
The issue control method of the input / output instruction will be described.

A characteristic of the embodiment of FIG. 1 is that an FF 37 is provided for serializing an input / output instruction and an interrupt response signal (hereinafter referred to as an IACK signal) according to a reception timing. , The FF37 is set when the IACK signal is received from the CPU interface unit 32, and reset when the I / O command is received, so that when the FF37 is '1', the I / O command comes first. When it is '0', the IACK signal can be operated first.

The gates 38 and 310 insert conditions for transmitting the transfer request of the IACK signal to the bus control unit 33, and the FF 37 of the present invention sets the value to "1".
When there is an input / output command request and the channel device numbers (CH-No.) Match, the IACK signal transfer request is suppressed.

Similarly, the gates 39 and 311 insert a condition for transmitting a request for an input / output command, the FF 37 is '0', there is a transfer request for the IACK signal, and the channel device number (CH-No.) Is the same. If so, the transfer request of the I / O command is suppressed.

In this way, by adding the circuit of FF37, gates 38, 310, 39, 311, regardless of the state of the bus 4 or channel device (CH) 2, the request from the side that received first for the same channel number is complete. Since the next request is suppressed until the end of, the order can be guaranteed.

Of course, for input / output commands with different channel numbers or interrupt response signals, the above-mentioned gates 38 and 39 are always open, so that the same transfer operation as in the past can be performed without receiving the sequence control of the present invention. Will be done.

As described above, the present invention relates to a channel control unit (CHC) that controls input / output commands and interrupt processing for a plurality of channel devices (CH) in an information processing device, for example, via a general-purpose bus. Interrupt control method, especially for controlling the order of issuing I / O commands and interrupt response signals (IACK signals) for the same channel device (CH), the same channel device number from the central processing unit (CPU) , An input / output instruction and an interrupt response signal (IACK) are issued in the order of reception on the channel device (CH) side of the number, and a control means 37 is provided so that the input / output instruction and the interrupt for the same channel number are provided. When the response signal (IACK signal) is present on the channel controller (CHC) 3 at the same time, the acceptance order in the channel device (CH) 2 is stored by storing the acceptance order and serializing the issue order. There is a feature in that it is guaranteed.

〔The invention's effect〕

As described above in detail, the input / output instruction of the present invention,
The interrupt response issuance control method is an interrupt in a channel control unit (CHC) that controls input / output commands and interrupt processing, for example, via a general-purpose bus to multiple channel devices (CH) in the information processing device. Control method, especially to control the issue of I / O command and interrupt response signal (IACK signal) for the same channel device (CH), input / output command and interrupt response signal (IACK signal) for the same channel device number
Signal) and a means for controlling the reception order on the side of the channel device (CH) of the number, that is, a means for storing the reception order and serializing the issuing order, for the channel device (CH). Since the order of acceptance is guaranteed, there is no need to perform interlock control between the central processing unit (CPU) and the channel device (CH), and the central processing unit (CPU) does not need to perform a release operation. There is an effect that it can be performed, wasteful processing stop time is eliminated, and the performance of the information processing apparatus can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional input / output instruction and an interrupt response signal issuing control system. In the drawing, 1 is a central processing unit (CPU), 10 is an interlock control mechanism, 2 is a channel device (CH), 3 is a channel control device (CHC), or an input / output instruction,
Mechanism for controlling interrupt processing, 32 CPU interface unit, 33 bus control unit, 35 flip-flop (FF) holding IACK signal sending request, 36 flip-flop holding I / O command sending request Flops (FF) and 37 are input / output instructions and flip-flops (FF) for serializing the IACK signal, or sequence control means, and 38, 39, 310 and 311 are gates, respectively.

Claims (2)

(57) [Claims] 1. A plurality of channel devices (C
H) (2), a control mechanism (3) for controlling input / output commands from a central processing unit (CPU) (1) and interrupt processing via a bus (4), (CPU) Input / output instruction and interrupt response signal (IA) for the same channel device number from (1)
CK signal) and a sequence control means (37) for issuing the CK signal) according to the reception order on the side of the channel device (CH) (2) of the number, and the sequence control means (37) controls the same channel device (37). CH) (2) Input / output instruction and interrupt response issuance control method characterized by controlling the receiving and issuing order between the above input / output instruction and interrupt response (IACK). 2. The sequence control means (37) is a flip-flop that is set or reset by an interrupt response signal (IACK signal) from a central processing unit (CPU) (1) or an input / output instruction. An FF) (37) is provided, and the issuing order of the interrupt response signal (IACK signal) and the input / output instruction is controlled by the output of the flip-flop (FF) (37). Input / output instruction and interrupt response issue control method described.