JPH05108192A - Personal computer - Google Patents

Abstract

PURPOSE:To reduce the capacity of a program by always executing a high speed clock means and then inhibiting an operation clock processing by means of an interrupt processing routine when an interrupt takes place. CONSTITUTION:In an ordinary processing routine other than the interrupt processing routine, the interrupt processing is inhibited with an interrupt inhibit means 90 and under a state where the interrupt is inhibited, the speed of a clock 80 is changed to low speed with a low speed clock means 10. Then under a device input waiting state, a hold command is executed and the speed of the clock 80 is changed to high speed with a high speed clock 20. The interrupt is enabled with an interrupt permission means 100. At this time under the device input waiting state, when the interrupt takes place, a processing to the interrupt processing routine is not soon executed, the speed of the clock 80 is changed to high speed with the high speed clock means 20 which is a command next specified after the hold command and then the interrupt processing routine is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer capable of reducing a program capacity by efficiently turning a clock on or off.

[0002]

2. Description of the Related Art Turning on or off a clock in a conventional personal computer is shown in FIGS. In the normal processing routine other than the interrupt processing, as shown in FIG. 4, the operation clock is operated at a low speed and the interrupt is enabled before the application program enters the device input waiting state (step 3) such as K / B or mouse. To do. On the other hand, in the interrupt processing routine, the operation clock is operated at high speed as shown in FIG. 5 (step 4) and each device processing is performed (step 5). When device processing is performed in the device input wait state of the normal processing routine and the interrupt processing routine, the interrupt processing routine is given priority over the normal processing routine, so a routine that always operates the operating clock at a high speed is provided. Driven.

[0003]

In the conventional personal computer, since the operating clock is made faster in the interrupt processing routine, as the number of interrupt processing increases, the processing for making the operating clock faster in each interrupt processing routine. However, there is a problem in that the program capacity is increased due to the need to do so.

[0004]

The present invention is to solve these problems, and in a personal computer equipped with a central processing unit having a standby mode function,
Interrupt prohibition means that prohibits interrupts in processing routines other than interrupt processing, low-speed clock means that slows down the operation clock when the interrupt prohibition means operates, and high-speed operation clock after executing a halt instruction while waiting for device input And an interrupt enable means for enabling the interrupt prohibiting means after the execution of the high speed clock means. When an interrupt occurs, the high speed clock means is always executed and then the operation clock processing is performed by the interrupt processing routine. Providing a personal computer that is prohibited.

[0005]

According to the personal computer configured as described above, the interrupt is prohibited in the processing routine other than the interrupt processing, the operation clock is slowed down, the halt instruction is executed while waiting for the device input, and then the operation clock is speeded up. After that, whenever an interrupt occurs due to the configuration in which the interrupt is enabled, the processing capacity to speed up the operation clock is performed, and then each device processing that is an interrupt processing routine is performed, so the program capacity is reduced. it can.

[0006]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a claim correspondence diagram of a personal computer showing an embodiment of the present invention, FIG. 2 is a flowchart for controlling normal processing of a personal computer showing an embodiment of the present invention, and FIG. FIG. 4 is a flowchart for controlling interrupt processing of a personal computer showing an embodiment, FIG. 4 is a flowchart for controlling normal processing of a conventional personal computer, and FIG. 5 is for controlling interrupt processing of a conventional personal computer. It is a flowchart. In FIG.
The personal computer of the present invention includes an input unit 50 for inputting data and a RAM 4 for storing the input data.
0, ROM 30 in which the program is stored, and RO
A central processing unit 60 for controlling according to program instructions stored in M30, a clock 80 for driving the personal computer of the present invention, and a low speed clock means 10 for reducing the clock speed thereof.
On the contrary, a high-speed clock means 20 for increasing the clock speed and an output means 7 for outputting the processing result.
0 and timer 95 that counts the time in real time
And a sending / receiving means 110 for sending / receiving data to / from another computer.

The operation will be described with reference to FIGS. 1, 2 and 3. The personal computer which is an embodiment of the present invention has the timer interrupt, K / B interrupt, transmission interrupt, and reception interrupt functions in order to improve the efficiency of data processing. An interrupt is generated at regular intervals counted by 95, and K / B interrupt causes K / B when key input is made.
An interrupt occurs, a transmission interrupt causes a transmission interrupt when data is transmitted, and a reception interrupt causes a reception interrupt when data is received. In this way, each interrupt is generated while waiting for device input. Therefore, since an interrupt handling routine is required for each device, four types of interrupt handling routines are required in this case.

The present invention utilizes the halt instruction provided in the central processing unit 60 having the standby mode function in the normal processing other than the interrupt processing routine. It is characterized by utilizing the unique function of the central processing unit 60 for executing the next instruction.

FIGS. 2 and 3 explain the operation of waiting for device input. In normal processing routines other than the interrupt processing routine, interrupt processing is prohibited by the interrupt prohibiting means 90 shown in FIG. 1 (step 10). While the interrupt is prohibited, the speed of the clock 80 is reduced by the low speed clock means 10 shown in FIG. 1 (step 2).
0). After this, the halt instruction is executed in the state of waiting for device input (step 30), and the speed of the clock 80 is increased by the high speed clock means 20 shown in FIG. 1 (step 40). Further, the interrupt is enabled by the interrupt permission means 100 shown in FIG. 1 (step 5
0). In the interrupt processing routine shown in FIG. 3, the above-described timer interrupt, K / B interrupt, transmission interrupt, and reception interrupt processing are performed (step 60).

When an interrupt occurs in such a device input waiting state, the interrupt processing routine is not immediately processed and the speed of the clock 80 by the high-speed clock means 20, which is the next instruction after the halt instruction, is increased (step 40). ), The interrupt processing routine is performed. Therefore, in each interrupt processing routine, the clock 80
Since there is no need for processing to speed up the
The program is simple and the capacity can be reduced.

Further, in the conventional personal computer, when an interrupt occurs in a state not waiting for device input, processing for increasing the speed of the clock 80 is performed by both the normal processing routine and the interrupt processing routine other than the interrupt processing routine. There is. In the personal computer of the present invention, the processing speed is improved because neither of them performs the processing for increasing the speed of the clock 80.

[0012]

As described above, according to the present invention, the halt instruction provided in the central processing unit having the standby mode function is used, and when an interrupt occurs while the interrupt is disabled, the instruction next to the halt instruction is generated. By utilizing the peculiar function of this central processing unit for executing, the program can be simplified and the capacity can be reduced.

[Brief description of drawings]

FIG. 1 is a claim correspondence diagram of a personal computer showing an embodiment of the present invention.

FIG. 2 is a flowchart for controlling a normal process of a personal computer showing an embodiment of the present invention.

FIG. 3 is a flow chart for controlling interrupt processing of a personal computer showing an embodiment of the present invention.

FIG. 4 is a flowchart for controlling a normal process of a conventional personal computer.

FIG. 5 is a flowchart for controlling interrupt processing of a conventional personal computer.

[Explanation of symbols]

 10 low-speed clock means 20 high-speed clock means 30 ROM 40 RAM 50 input means 60 central processing unit 70 output means 80 clock 90 interrupt prohibition means 95 timer 100 interrupt permission means 110 transmission / reception means

Claims (1)

[Claims] 1. In a personal computer having a central processing unit having a standby mode function, an interrupt prohibiting means for prohibiting an interrupt in a processing routine other than the interrupt processing, and a low speed for lowering the operation clock when the interrupt prohibiting means operates. The interrupt means comprises a clock means, a high-speed clock means for speeding up an operation clock after executing a halt instruction while waiting for device input, and an interrupt permitting means for enabling the interrupt prohibiting means after executing the high-speed clock means. The personal computer is characterized in that the operation clock processing is prohibited in the interrupt processing routine after the execution of the high-speed clock means whenever any of the above occurs.