JPH0736813A - Channel control device - Google Patents

Abstract

PURPOSE:To reduce the generation probability of data overrun by considering and determining the sort of a peripheral device in addition to a transfer system and the number of counts remaining in a data buffer at the time of determining data transfer interruption priority for data from respective channels in a channel control device. CONSTITUTION:In the case of sending instruction codes for starting I/O data transfer from respective peripheral control devices 41 to 44 to respective channel devices 71 to 74, sorted information of peripheral devices for starting transfer is included in the instruction codes and the sorted information is stored in respective device sort storing means 101 to 104. In the case of preparing interruption requests by respective interruption request preparing means 91 to 94 and sending the requests to an inter-channel priority judging means 6, the information in the means 101 to 104 is also sent to the means 6, which determines the priority order of respective data transfer interruption requests while considering transfer methods, the numbers of counts remaining in the data buffer and sorted information for respective requests.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel controller, and more particularly to a channel controller for controlling input / output with a plurality of peripheral controllers.

[0002]

2. Description of the Related Art A conventional channel control device of this type utilizes the transfer method of each channel and the remaining count of the data buffer as a determination factor when determining the priority of a data transfer interrupt request from the channel. , In the case of a transfer method with a high transfer capacity, the priority of an interrupt request is high, in the case of a transfer method with a low transfer capacity, the priority of an interrupt request is low, and when the remaining count of the data buffer is small, The priority level of the interrupt request is set high, and the priority level of the interrupt request is set low when the remaining count has a margin.

[0003]

In the above-mentioned conventional priority determination method, although the transfer method has a low priority, when the transfer capability of the peripheral device is high, the priority of the interrupt request is set low and the data is transferred. May cause overrun.

An object of the present invention is to provide a channel control device in which the probability of occurrence of data overrun is further improved by determining the priority in consideration of the type of peripheral device actually used.

[0005]

A channel control device of the present invention is connected between an input / output processing device connected to a main memory device and a plurality of peripheral control devices to connect the main memory device and each peripheral device. In the channel control device for controlling data input / output between the channel control devices, each channel device corresponding to the peripheral control device has a device type storage unit for storing the type of the peripheral device to be transferred. Between channels for determining the priority in consideration of the type of peripheral device stored in the device type storage means in addition to the transfer method and the remaining count of the data buffer in the channel device in response to the data transfer interrupt request from It is configured to include priority determination means.

[0006]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a system configuration including an embodiment of the present invention.

The channel controller 3 of this embodiment shown in FIG.
Is connected between the input / output processing device 2 that processes data input / output of the main storage device 1 and the peripheral control devices 41 to 44, and the input / output interfaces 111 to 114 are connected to the peripheral control devices 41 to 44. The channel devices 71 to 74 for executing data transfer via the channel device, the inter-channel priority determining means 6 for determining the priority of the data transfer interrupt request from the channel devices 71 to 74, and the requests of the channel devices 71 to 74 are managed. A channel request processing device 5 for controlling data exchange with the input / output processing device 2 is provided. Further, in each of the channel devices 71 to 74, the peripheral control device 4 is provided.
Data buffer 81 for storing transfer data with 1 to 44
To 84, interrupt request creation means 91 to 94 for creating an interrupt request, and device type storage means 10 for storing the types of operating peripheral devices under the control of the peripheral control devices 41 to 44.
1 to 104 are provided.

Next, the operation will be described with reference to FIG. For example, assuming that an input / output operation between the main storage device 1 and a peripheral device under the peripheral control device 41 is activated, first, the channel program waits for the peripheral control device 41 from the input / output processing device 2. Will be notified. As a response to this notification, an instruction code for instructing a channel command word transfer request from the peripheral control device 41 is sent to the channel device 71, and when the input / output processing device 2 accepts this request, a firmware interrupt for the channel command word sending process occurs. Then, the channel command word is read from the main memory 1 by the processing of the firmware. This channel command word is sent by the input / output processor 2 to the channel controller 3 and the input / output interface 11.
1 to the peripheral control device 41. When the peripheral control device 41 sends the instruction code to the channel device 71, information in which the type of the peripheral device that starts the transfer is coded in the instruction code (for example, the transfer capability depending on the type of the peripheral device is set to two levels). The information including the divided 1-bit information) is sent to the channel device 71 together with the instruction code.

When the channel device 71 receives the instruction code sent from the peripheral control device 41, the interrupt request creating means 91 creates an interrupt request. Further, the device type storage means 101 stores the type code of the peripheral device in the instruction code sent from the peripheral control device 41.
When the interrupt of the instruction code is accepted by the input / output processing device 2, the input / output processing device 2 generates a firmware interrupt, and the channel device 71 is processed by the firmware.
To enable data transfer.

When the channel command word for the data transfer to be started is input, the data from the peripheral controller 41 is stored in the data buffer 81 via the input / output interface 111, and when a certain amount of data is accumulated, an interrupt request is created. The means 91 creates an input data transfer interrupt request. The type code information in the device type storage means 101 is sent to the inter-channel priority determination means 6 together with the interrupt request created by the interrupt request creation means 91. When there are a plurality of data transfer interrupt requests at the same time, the inter-channel priority determining means 6 determines that each channel device 71
To 74, the remaining counts of the data buffers 81 to 84, the transfer capability of the input / output interfaces 111 to 114 depending on the transfer method, and the device type storage unit 101.
Judgment is made from the type of the peripheral device which stores the interrupt request currently stored in ~ 104, and one interrupt request having the highest urgency is selected. This selection is performed based on the criteria set in the inter-channel priority determining means 6 in advance. The data in the data buffer in the channel device corresponding to the selected interrupt request is sent to the input / output processing device 2 under the control of the channel request processing device 5, and the input data is written in the main storage device 1.

When the channel command word is output, the interrupt request creating means 91 creates an output data transfer interrupt request, and like the input data transfer, together with the interrupt request created by the interrupt request creating means 91,
The type code information in the device type storage means 101 is sent to the inter-channel priority determination means 6, and the inter-channel priority determination means 6 uses the remaining counts of the data buffers 81 to 84 in the respective channel devices 71 to 74, the input / output interface. 1
Data transfer capability due to the difference in the transfer method of 11 to 114,
Also, one of the interrupt requests having the highest urgency is selected by judging from the type of the peripheral device which is currently raising the interrupt request stored in the device type storage means 101 to 104.
The selected interrupt request is sent to the channel request processing device 5, and the input / output processing device 2 is sent via the channel request processing device 5.
Sent to. When an interrupt request is sent to the input / output processing device 2, the input / output processing device 2 sends the output data from the main memory 1 and stores the output data in the data buffer in the channel device that has issued the output data transfer interrupt request. . The output data stored in the data buffer is sent to the peripheral controller via the input / output interface. When the data is transferred and the data in the data buffer falls below a certain value, an input data transfer interrupt request is issued.

In the above embodiment, the device type storage means stores the type code information of the peripheral device sent from the peripheral control device, but the same information is determined by the channel control by judging from the peripheral device name. It may be determined and stored on the device side.

[0014]

As described above, the channel control device of the present invention interrupts a data transfer interrupt request from a channel in consideration of the type of peripheral device in addition to the transfer method and the remaining count of the data buffer. Since the priority of the request is determined, it is possible to interrupt a request having a higher interrupt need, which has the effect of reducing the probability of data overrun and enabling efficient interrupts.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration including an embodiment of the present invention.

[Explanation of symbols]

1 main memory 2 input / output processor 3 channel controller 41, 42, 43, 44 peripheral controller 5 channel request processor 6 inter-channel priority determination means 71, 72, 73, 74 channel device 81, 82, 83, 84 Data buffer 91, 92, 93, 94 Interrupt request creating means 101, 102, 103, 104 Device type storage means 111, 112, 113, 114 Input / output interface

Claims (1)

[Claims] 1. A channel controller which is connected between an input / output processing device connected to a main storage device and a plurality of peripheral control devices and which controls data input / output between the main storage device and each peripheral device. In each channel device corresponding to the peripheral control device, device type storage means for storing the type of peripheral device to be transferred is stored, and in the channel device in response to a data transfer interrupt request from each channel device. A channel provided with inter-channel priority determining means for determining the priority in consideration of the type of peripheral device stored in the device type storing means in addition to the transfer method and the remaining count of the data buffer. Control device.