JPH0535640A - Channel priority deciding circuit - Google Patents

Abstract

PURPOSE:To shorten the reading time of a channel command by taking priority over a small-scaled data transfer request with the small number of transfers. CONSTITUTION:A transfer number control part 14 to control the number of transfers to be transferred by each channel controller is held, it is judged whether or not the data transfer request is a small-scaled data transfer request, and at the time of the small-scaled data transfer request, the transfer request priority-decided and selected by a small-scaled data transfer priority deciding part 13 takes priority over the transfer request selected by a data transfer request priority deciding part 12 and the small-scaled data transfer of the small number of the transfers such as the channel command transfer is processed earlier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel priority judging circuit, and more particularly, it is provided with a plurality of channel control devices which operate in accordance with an instruction of a channel program existing in a main memory device, and selects a data transfer request from each channel control device. Channel priority determination circuit.

[0002]

2. Description of the Related Art A conventional channel priority determination circuit is designed to select a data transfer request generated by a plurality of channel control devices under its control according to a certain rule.

For example, if this rule gives priority to a channel control device number in ascending order, a data transfer request with the smallest channel control device number among channel control devices requesting data transfer is selected. Alternatively, when the channel control device once selected by the priority determination makes the next data transfer request, the priority of the data transfer request is set to the lowest and the priorities are equalized.

Next, the channel control device under the priority determination circuit will be described. The channel control unit is a transmission line for information that connects the peripheral control unit under its control to the higher-order I / O control unit.The operation of the channel control unit is independent of the central processing unit. It is determined by executing a series of programs at any time after an instruction called a program for executing an input / output operation (hereinafter referred to as a channel command).

Therefore, the channel controller requests the I / O controller to calculate the storage address of the corresponding channel command in the main memory in order to read the channel command to be executed next from the main memory. Then, the calculated storage address and the number of transfer data are returned, and thereafter, the channel command in the main storage device is read out via the input / output control device and the command transfer is delivered to the peripheral control device.

In data transfer, the channel command read as described above is decoded, and if the channel command is a data transfer request of an input transfer instruction or an output transfer instruction, the channel command is attached. The channel control unit reads the output transfer data from the main storage unit via the I / O control unit, or the input transfer to the main storage unit, with the flag, the data transfer start address, and the number of transfer bytes that are passed together as data. Data is written.

As described above, the command transfer is also handled as the data transfer and is not particularly distinguished and executed.

[0008]

In this conventional channel priority judgment circuit, in order to select one data transfer request from a large number of data transfer requests, the channel control device numbers are prioritized in the ascending order or once. The priority of the selected channel control device is set to the lowest priority and the equalization priority is set.

However, since no distinction is made between data transfer and command transfer, when one channel control device rapidly needs a channel command, data transfer of a plurality of other channel control devices is being executed, If the priority of its own command transfer request is low, the disk device connected to the peripheral controller under the channel controller may exceed the command processing time limit. In the case of transfer, although it is time to write or read transfer data on the disk, a command overrun occurs in which it cannot be executed because the previous command processing is not completed.

When this command overrun occurs, there is a problem that the channel program must be re-executed from the beginning.

An object of the present invention is to provide a channel priority determination circuit that solves the above problems.

[0012]

In order to achieve the above object, in a channel priority determination circuit according to the present invention, a data transfer request having a highest priority is selected from data transfer requests generated from a plurality of channel control devices. A data transfer priority determination unit, a small transfer number upper limit register that stores an upper limit value of the number of transfers for which the number of transfers of the data transfer request is small and is regarded as small-scale data transfer, and the transfer of the data transfer request A transfer number management unit that holds the transfer number for each channel control device is compared with the transfer number upper limit value of the small transfer number upper limit register and the transfer number of the transfer number management unit, and the transfer number management unit compares the transfer number lower than the upper limit value. A valid bit corresponding to a channel control device indicating small-scale data transfer and a small-scale data transfer required for prioritizing the data transfer request validated by the valid bit. A priority determination unit and a transfer request switching unit that switches the small-scale data transfer request selected by the small-scale data transfer priority determination unit with priority over the data transfer request selected by the data transfer request priority determination unit. Is to have.

[0013]

In the present invention, the priority is given to the small-scale data transfer in which the number of data transfers is smaller than the upper-limit value of the small-scale transfer, as compared with the normal data transfer.

[0014]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, a channel priority determination circuit 10
Are connected to a plurality of channel control devices 30, and are further connected to the input / output control device 50 of the host device. Further, a peripheral control device 40 is individually connected under the channel control device 30.

The channel priority determination circuit of the present invention comprises a data transfer request priority determination unit 12 for selecting data transfer requests generated from a plurality of channel control devices 30, and a small number of data transfer requests to be transferred. Data transfer upper limit register 22 for storing the upper limit value of the number of transfers, a transfer number management unit 14 for holding the transfer number of the data transfer request to be transferred for each channel control device, and the small transfer number. A valid bit 15 corresponding to the channel control device, which indicates that the transfer count upper limit value of the upper limit register 22 and the transfer count of the transfer count management unit 14 are smaller than the transfer count upper limit value and indicates small-scale data transfer, and a valid bit. Selected by the small-scale data transfer priority determining unit 13 and the data-transfer request priority determining unit 12 that prioritize a data transfer request that has been validated as a small-scale data transfer in 15. And a transfer request switching unit 11 toggle its small data transfer request selected by the small data transfer priority determining unit 13 than the data transfer request with priority.
Reference numeral 40 is a peripheral control device.

Next, the operation of this embodiment will be described.
Data transfer request 31 generated by each channel control device 30
On the other hand, the data transfer request priority determination unit 12 selects one data transfer request 31 having the highest priority and selects the highest priority data transfer request 17 and the highest priority data transfer request channel number 1.
9 is sent out.

Although this operation is the same as that of the conventional apparatus, the transfer number management unit 14 judges that each channel control device 30 executes small-scale data transfer having the number of transfer bytes to be transferred and smaller than the small-scale transfer number upper limit value 23. Then, the corresponding bit position of the valid bit 15 indicating the small-scale data transfer corresponding to the channel control device 30 is validated, and the data transfer request 31 determined to be the small-scale data transfer is given the small-scale data transfer priority. The determination unit 13 side makes priority determination.

It is assumed that the small-scale transfer number upper limit register 22 holding the small-scale transfer number upper limit value 23 can set an arbitrary number of transfers. The small-scale data transfer priority determination unit 13 is a priority determination unit dedicated to a small-scale data transfer request, and has the highest priority from the data transfer requests 31 of the channel control device 30 that have performed small-scale data transfer with the valid bit 15. The highest priority small-scale data transfer request 16 and the highest-priority small-scale data transfer request channel number 18 with high frequency are selected.

Next, the highest priority data transfer request 17, the highest priority data transfer request channel number 19 and the small data transfer priority determination unit 1 selected by the data transfer request priority determination unit 12 are selected.
The highest priority small-scale data transfer request 16 and the highest-priority small-scale data transfer request channel number 18 selected in No. 3 compete, but the transfer request switching unit 11 determines the highest-priority data transfer request 17
Then, the small-scale data transfer priority determination unit 13 sends to the input / output control device 50 that the OR gate 20 has a transfer request.

Further, the highest priority data transfer request 17 and the small-scale data transfer priority determination unit 13 to the AND gate 21.
Then, the small-scale data transfer side is given priority, and the highest-priority small-scale data transfer request channel number 18 is set to the transfer request channel number 15
To the input / output control device 50.

In the input / output control device 50, based on the transfer request 14 and the transfer request channel number 15, when input data is written in the main storage device or when a command is transferred from the main storage device, channel commands, flags, etc. are read out. At the time of data transfer, output data is read.

[0023]

As described above, according to the present invention, the priority is given to the small-scale data transfer in which the number of data transfers is smaller than the upper limit of the number of small-scale transfers, and the priority is higher than that of the normal data transfer. When transferring the channel command, flag, etc., the number of transfers is small, so that the channel command can be transferred to the peripheral control device quickly by giving priority to small-scale data transfer.

Therefore, the command transfer which is executed by other data transfer is not waited, so that the probability of exceeding the channel command processing time limit in the peripheral control device can be reduced, and as a result, the command over This has the effect of reducing the occurrence rate of orchids.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 10 Channel Priority Judgment Circuit 11 Transfer Request Switching Unit 12 Data Transfer Request Priority Judgment Unit 13 Small Data Transfer Priority Judgment Unit 14 Transfer Request 15 Effective Bit 16 Top Priority Small Data Transfer Request 17 Top Priority Data Transfer Request 18 Top Priority Small Scale Data transfer request channel number 19 Highest priority data transfer request channel number 20 OR gate 21 AND gate 22 Small scale transfer number upper limit register 23 Small scale transfer number upper limit value 30 Channel control device 31 Data transfer request 40 Peripheral control device 50 Input / output control device

Claims (1)

Claim: What is claimed is: 1. A data transfer priority determination unit for selecting a data transfer request having the highest priority among data transfer requests generated from a plurality of channel control devices, and a transfer to be transferred of the data transfer request. A small-scale transfer number upper limit register that stores a transfer number upper limit value that is regarded as a small number of small-scale data transfers, and a transfer number management unit that holds the transfer number to be transferred of the data transfer request for each channel control device. An effective bit corresponding to a channel control device indicating that the transfer count upper limit value of the small scale transfer count upper limit register is compared with the transfer count of the transfer count management unit to indicate a small scale small data transfer. A small-scale data transfer request priority determination unit that prioritizes the data transfer request that has been validated by the valid bit, and data selected by the data transfer request priority determination unit. A channel priority determination circuit comprising: a transfer request switching unit that switches the small-scale data transfer request selected by the small-scale data transfer priority determination unit with priority over the transfer request.