JPS61165163A - Channel selecting system - Google Patents

Abstract

PURPOSE:To realize an efficient channel selection corresponding to a processing request by a comparatively simple circuit, by providing two kinds of a waiting register for emergency and a usual waiting register which requires no emer gency, in accordance with a degree of emergency of the processing request, and selecting preferentially channel information of a high priority degree, to a processing register. CONSTITUTION:In a channel memory stack (CMS) 1', a processing request bit (R) and an emergency processing bit (P) are stored together with the same channel control information as a conventional system, and channel information which requires priority processing is always transferred to an emergency use waiting register (EWR) 42, or a usual waiting register (WR) 41 from a stack read register (SRR) 2, but at the time of usual channel information, it is controlled so that it is transferred to only the WR41, and also, when a processing register (PROR) 5 becomes 'idle', it is controlled so that the waiting register of the highest priority is selected from two kinds of waiting registers (WR41, EWR42).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for selecting a channel to be processed next in a channel control device having a common control circuit that commonly controls a plurality of channels.

With the recent remarkable progress in semiconductor technology, the speed of data processing devices has been increased, and a common control method has been adopted for channel control devices as well, with the aim of making them more economical.

However, when processing requests from a plurality of channels are to be processed by one common control device, the problem arises as to which channel should be selected.

In the conventional method, there are problems such as the selection circuit becoming complicated and the control for 2-selection processing becoming complicated. has become required.

[Conventional technology]

Conventional channel selection methods can be roughly divided into an emergency replacement method and a one-way method of copying processing requests for all channels. Fig. 2 shows a block diagram of the emergency replacement method, and Fig. 3 shows a block diagram of one method for copying processing requests for all channels. shall be indicated.

In Figure 2, ■ is a channel memory tank (hereinafter referred to as
CMS), lL12 is the channel M register (hereinafter referred to as CLLN0), 2 is the stack leave register (hereinafter referred to as Sfl[l), 3 is the selection control section, 4 is the wait register (WR), and 5 is the processing. register (PRO
R).

6 is an input/output processing section.

First, CllN011 is incremented by 1 every operation cycle, and CMS 1 is accessed to set its contents, such as channel activation information, channel command word (hereinafter referred to as CCW) fetch information, status analysis information, etc., to 5RR2.

In the selection control section 3, the SRI? It analyzes the contents of CllN0.2, generates a processing request (R) and a priority (P), and if the wait register (WR) is in the "empty" state, sets it in that specific field, and also sets it in the specific field. and S
l? By transferring the contents of R2, the processing of the channel enters a "waiting" state.

However, if the wait register (WR) is busy and the priority (1) of the above-mentioned 5II112 is higher than the priority (P) of the wait register (WR) 4, the wait register (WR) is busy. )4 is replaced with the contents of 5IlR2.

In addition, in the above comparison process, even if CllN0 matches, the contents of the wait register (WR) 4 are changed to 51711' in order to bring the contents of the wait register (1) 4 to the latest state.
It works as if replacing with the contents of 2.

In cases other than J-, the channel information read out to SRR2 is erased in the next cycle, and is
I'm stunned.

On the other hand, the channel information set in the processing register (PROR) 5 is read by the input/output processing unit 6 and executed.

Therefore, when the processing in the input/output processing section 6 is completed, -J
- The channel information set in the write waiting register (WR) 4 is transferred to the processing register (PROR) 5, so that channel processing is performed sequentially.

The above-mentioned emergency selection process occurs when the input/output processing unit 6 is processing a certain CllN0 channel, for example, when the write buffer becomes "empty" while executing a write process, or when a read process is being executed. , the data sofa is full (
FUI, 1. ), or when it becomes necessary to fetch CCW for chain data, it is detected that an emergency is required.
This is a case where the CMS I is accessed and the contents of the CII NO indicated by CLLN012 are updated. The above is the channel selection method using the emergency replacement method.

Next, a channel selection method using one method of copying processing requests for all channels will be explained with reference to FIG.

In this method, in the selection control section 3, the SRR2
By analyzing the information of all channels set in ', each Cl
The processing request (1?) corresponding to lN0 is stored in the processing request register (
The priority (P) is stored in the priority register (P
RR) 72, and a comparison circuit 8 compares the processing request (R) and priority (P) for all the set channels.
When the processing being executed in the input/output processing unit 6 is completed, the processing request (R
), accesses CMS1 using its CLLN0, sets it in the processing register (Pl?OR) 5, and performs the next channel processing.

The urgent selection process mentioned above is for the commercials explained in Figure 2.
This is a case where the contents of CI'lS1 are changed in the same way as the update operation of CI'lS].

[Problem that the invention seeks to solve]

Therefore, in the conventional channel selection method, (1) In the emergency replacement method, each time the contents of CMS I are updated, the contents of SRR2 are changed in order to reflect the updated status in wait register (WR) 4. and the waiting register (M
l? ) There was a problem in that it was necessary to compare the contents of 4. This made the process complicated.

■ Copying processing requests for all channels In one type, processing request register (RQR) 71 and priority register (PRR) are used to record processing requests (R) and priorities (P) for all channels in 1.1. ) 72 and selects the channel request with the highest priority, which requires a comparison circuit 8, which results in a complicated circuit.

In view of the above-mentioned conventional drawbacks, the present invention provides the following as a waiting register:
By providing two types of waiting registers (WR) for normal processing and waiting registers (EWR) for emergency processing, and by providing an emergency processing bit (P) in each waiting register (WR, EWR), it is possible to respond to processing requests. The purpose is to provide efficient channel selection using a relatively simple circuit.

[Means for Solving Problem c] This purpose is to provide a control circuit that commonly controls a plurality of channels, and while the common control circuit is being used for processing one channel, it is possible to control the next processing candidate. In a channel control device that has a plurality of wait registers for storing processing requests from channels and channel numbers, and selects the next processing channel from among the wait registers according to the degree of urgency, the type of the wait register is There are two types of processing requests, urgent and non-urgent, depending on the urgency of the processing request.In addition, an urgent processing bit is provided in the wait register to select the next processing channel depending on the urgency of the processing request. This is achieved by the channel selection method of the present invention.

[Effect]

That is, according to the present invention, the type of the waiting register is changed to the emergency waiting register ([!MR) depending on the urgency of the processing request.
In addition to providing two types of wait registers (WR) and a normal wait register (WR) that does not require an emergency, an emergency processing bit is also provided in the wait register, so that when an event that requires an emergency occurs while a certain channel process is being executed, , updates the information corresponding to the channel in the channel memory tank (CMS), and turns on the emergency processing bit, thereby reading the wait register (W) from the stack read register (SRR).
R), the emergency processing bit is referred to and if the emergency processing wait register (EWI?) or the register ([WR) is busy, the normal wait register (
WR), so the emergency wait register (EWR) and normal wait register (WR)
The one with higher priority is stored in the processing register (PROR).
This has the effect of allowing priority selection to be made, and efficient channel selection according to processing demands can be achieved with a relatively simple circuit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention in a block diagram, in which the same reference numerals as in FIGS. 2 and 3 indicate the same objects, including a channel memory stack (CMS) 1'.

Emergency Waiting Register (EWR) 42. Processing request bit 21° and emergency processing bit 223 selection control units 90 and 91 are functional blocks necessary to implement the present invention.

First, the CMS 1' stores a processing request bit (R) and an emergency processing bit (P) along with the same channel control information as in the conventional method, and the CMS
The l-lN0 register 1 is updated, and the channel information corresponding to each C) INO is read to the SRR2, and the wait register (WR) 4 and the emergency wait register (EWR) are read out.
42 or the like is "vacant", it is stored in one of the waiting registers (WR4LRWR42) according to the respective priority according to the control signal EN of the selection control unit 9o.

Here, processing register (PROI?) 5 is “empty”
When this occurs, the highest priority wait register is selected by the control signal SEL of the selection control unit 91, transferred to the processing register (PRO[l) 5, and channel processing is executed in the input/output processing unit 6. Ru.

In this state, when an event that requires the above-mentioned priority processing occurs in a certain channel, CMS L' is accessed, and the control information that requires the priority processing is stored in the area of ClN0 indicated by CtljJ, 012. and the priority processing bit is set on.

When the CllN0 register 11 is updated and the channel information of the CHNO that requires the above-mentioned priority processing is read out to the SRR2, the selection control unit 90 sets the processing request bits (R,) 2.1, (I optical processing bits ( P)22
is referenced and both bits are on, a free wait register is searched and the emergency wait register (EWR) is
42 is in the "empty" state, the corresponding wait register (EW
I? ) 42, but the wait register (EWR
) 42 is busy, wait register (WR) 4
The “empty” wait register (WR) in 5RR2 is selected, and the contents of 5RR2 are transferred to the corresponding wait register (WR).
) Transferred to 41.

In this state, the channel processing currently being executed is completed in the input/output processing unit 6, and the processing register (PROR) 5
When becomes “vacant”, the selection control unit 91 selects the emergency waiting register ([!WR) 42 and the emergency processing pin of the waiting register (WR) from the plurality of waiting registers (WR41, EWR42). Based on the information in P), the highest priority wait register is selected, the channel information is transferred to the processing register (PROR) 5, and the input/output processing section 6 executes the channel processing.

As described above, in the present invention, channel information that requires priority processing is always stored in the emergency waiting register (EWR) 42. from 5IIR2. Or the normal wait register (WR
) 41, but when it is normal channel information, it is controlled so that it is only transferred to the wait register (WR) 41, and also to the processing register (PROR) 5.
When becomes “empty”, the two types of wait registers (In
? 41. It is characterized in that it is controlled so that the highest priority wait register is selected from the EWR 42).

〔Effect of the invention〕

As described above in detail, the channel selection method of the present invention determines the type of waiting register depending on the urgency of the processing request.
Emergency waiting register (E) 11? ) and a normal waiting register (-R) that does not require an emergency, and an emergency processing hint is provided in the waiting register.1. If the above-mentioned urgent event occurs while a certain channel process is being executed, the channel memory stack (CMS)
When fetching from the stack read register (S1?Il) to the wait register (WR) by updating the information corresponding to the relevant channel and turning on the emergency processing bit, refer to the emergency processing bit, The above emergency processing wait register (EWR), or the register (EWR)
) is busy, the transfer is made to the normal wait register (WR), so the emergency wait register (P.

Mll), or transfers high priority channel information from the normal wait register (WR) to the processing register (PROI?).
) can be selected preferentially, and efficient channel selection according to processing demands can be achieved with a relatively simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing an example of a conventional channel selection circuit. FIG. 3 is a block diagram showing another example of a conventional channel selection circuit. It is. In the drawing, 1 is a channel memory stack (CMS). 11.12 is Channel South Register (CIINO). 2.2" is the stack read register (SRR). 21 is the processing request bit (R'), 22 is the emergency processing bit (P). 3.90.91 is the selection control section. 4.41 is the wait register (WR) . 42 is an emergency processing wait register (EWR). 5 is a processing register (PROI?). 6 is an input/output processing unit. 71 is a processing request register (12Ql?). 72 is a priority register (PRR). 8 is a Comparison circuit.

Claims (1)

[Claims] A control circuit for controlling a plurality of channels in common, and a control circuit for storing a processing request from a next processing candidate channel and a channel number while the common control circuit is used for processing one channel. In a channel control device that has a plurality of waiting registers and selects the next processing channel from among the waiting registers according to the degree of urgency, the type of the waiting register is determined as urgent according to the degree of urgency of the processing request;
A channel selection method characterized by providing two types of non-urgent processing channels, and providing an urgent processing bit in the waiting register, so that the next processing channel is selected depending on the urgency of the processing request.