JPH07210490A - Input/output control system - Google Patents

Abstract

PURPOSE:To reduce time for executing an output instruction by interrupting and restarting the interruption processing of a microprocessor concerning an input/output control system controlling plural channels by the single microprocessor. CONSTITUTION:The input/output control system can interrupt and restart the interruption processing of the microprocessor by providing with an interruption generating means 6 capable of optionally setting from the microprocessor 3 to a channel 4 connected to the microprocessor 3 and a means 7 for interruption from the channel 4 or interruption generation. Thereby, the system can complete the input/output instruction by the absolute minimum processing without affecting time for interruption processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control system, and more particularly to an input / output control system for controlling a plurality of channels by a single microprocessor.

[0002]

2. Description of the Related Art A general configuration of an input / output system is shown in FIG.

CHC (channel controller) 2 is a C
Communication control between the PU (central processing unit) 1 and the CH (channel) 4 is performed. Since the CPU1 communicates in units of CHC2, the CHC2 supervises the report requests from the plurality of CH4 under the CHC2 to the CPU1 and prevents the competition of the communication control of each CH4. CH4 is a CH based on data transfer control with I / O (input / output device) 5 and report request from I / O5
The status is reported to the CPU 1 via C2.

CHC2 and CH4 are controlled by a program on the same microprocessor 3, and CHC2 is assigned to a non-interrupt level and CH4 is assigned to a specific interrupt level. A time chart of a series of input / output command operations in this input / output system is shown in FIG.

When the CHC 2 receives an input / output activation instruction from the CPU 1, the I / O instructed by the activation acceptance processing 9
Then, the monitoring loop 10 waits for an I / O 5 activation response report.

Next, an interrupt is generated by the activation response report from the I / O 5, and the activation response code creation process 12 is performed following the interrupt acceptance process 11 to create the activation response code according to the contents of the activation response report from the I / O 5. To do. After that, if data transfer is possible, the data transfer start processing 15 is performed, and then the activation response report request to the CHC 2 is made and the CH is re-started.
Return to the monitoring loop 10 of C2. The CHC 2 detects the activation response report request of the CH 4 in the monitoring loop 10 and reports the activation response code created by the CH 4 to the CPU 1 by the activation response process 13.

With the above, one input / output instruction of the CPU 1 is completed.

[0008] Examples of related devices of this type include, for example, JP-A-58-86645.

[0009]

In the above conventional technique, C
The start response cannot be made to the CPU 1 until the processing of H4 is completed.

In recent years, the processing speed of the CPU 1 has been improved, and C
The difference in processing performance from H4 tends to increase. In addition, as CH4 data transfer methods become more sophisticated and complex, CH4
Because the percentage of I / O command time occupied by
However, there is a problem that the input / output instruction performance of No. 1 is deteriorated.

The present invention is intended to solve the above problems, and an object of the present invention is to provide an input / output control system capable of giving priority to a response to a host.

[0012]

In order to achieve the above object, an interrupt generating means that can be arbitrarily set in CH4 from the microprocessor 3 side, and an interrupt whether it is an interrupt from CH4 or an interrupt by the interrupt generating means An identification means is provided.

[0013]

Therefore, the microprocessor 3 interrupts the interrupt processing of CH4 at the time when the activation response becomes possible, and the CHC
The control shifts to the control 2 to end the activation response operation to the CPU 1.

After the completion of the start-up response operation, the interrupt means again generates an interrupt from CH4, and the microprocessor 3 which has received the interrupt restarts the interrupt processing which has been temporarily interrupted by the interrupt identification means.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, in which F is provided as an interrupt generating means capable of arbitrarily generating an interrupt from CH3 to the microprocessor 3.
An F (flip-flop) 6 and a scan bus 7 as a setting or interrupt identification means of the FF 6 are provided. FF
The output of 6 is ORed with the interrupt signal 8 generated by CH4, and an interrupt equivalent to the interrupt from CH4 to the microprocessor 3 can be generated.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention. 2, those parts which are the same as those corresponding parts in FIG. 3 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 2, after a series of start-up processing is completed, CH4 starts the start-up response code 12
CHC2 monitoring loop 1 by creating a start response code by issuing a start response report request to CHC2 and returning
Return to 0. The CHC 2 detects the activation response report request from the CH 4 in the monitoring loop 10 and reports the activation response code to the CPU 1. Thus, the input / output command of the CPU 1 is completed first.

Next, the CHC 2 sets the FF 6 which is the interrupt generation means of the present invention in the re-interruption request processing 14, and again C
Generate an interrupt from H4. Microprocessor 3
Starts the process for CH4 by accepting the interrupt from CH4, and the value of FF6 is read out by the interrupt accepting process 11 at the head thereof via the scan bus 7 which is the interrupt identifying means of the present invention. As a result, it is recognized that the interrupt process currently being performed is generated by the FF 6 which is the interrupt generation means, and the microprocessor 3 restarts the interrupt process that was interrupted before and performs the data transfer start process 15. The process ends.

[0019]

As is clear from the above description, CHC
2. In CH4, the process from the activation to I / O5 to the response to the activation to CPU1 can be completed with the minimum necessary processing without affecting the entire processing time of CH4.

Therefore, the input / output command time of the CPU 1 is shortened and the deterioration of the command performance of the CPU 1 is prevented.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a time chart of an example of the present invention.

FIG. 3 is a time chart of a conventional method.

FIG. 4 is a configuration diagram of a general input / output system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Central processing unit, 2 ... Channel controller, 3 ... Microprocessor, 4 ... Channel, 5 ... Input / output device, 6 ... Interrupt generation means by this invention, 7 ... Interrupt identification means by this invention, 8 ... Interrupt signal, 9 ... start acceptance processing, 10 ... monitoring loop, 11 ... interrupt acceptance processing, 12 ... start response code creation processing, 13 ... start response processing, 14 ... re-interruption request processing, 15 ... data transfer start processing.

Claims (1)

[Claims] 1. In a data processing system having a microprocessor having a function of accepting interrupts from a plurality of channels, interrupt generating means that can be arbitrarily set from the microprocessor side, and an interrupt from a channel or an interrupt by the interrupt generating means. An input / output control system characterized in that an interrupt identification means for distinguishing whether or not it is provided is provided, and interrupt processing performed by a microprocessor can be interrupted and restarted.