JP2003186936A - Method and device for executing operation verification simulation and its program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize certain operation verification simulation by accelerating overall (integral) operation verification simulation and preventing the simulation information from being lost. <P>SOLUTION: A CPU model part 203 is set in a stand-by state by a model operation setting part 205 in a prescribed timing (address value) after an I/O model part 204 is started to operate so that simulation can be omitted under the control of a simulation control part 201. Then, the CPU model part 203 is returned to the operating state by the model operation setting part 205 after event notice including an interrupt from the I/O model part 204 is recognized by the mode operation setting part 205 so that the simulation is resumed. Thus, when any loop which is meaningless in terms of processing is being processed by the CPU model part 203 in the interrupt stand-by state from the I/O model part 204, the simulation of the CPU model part 203 is omitted. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention verifies a control operation by a program execution of a control system (CPU, microcomputer, etc.) on a computer, and more specifically, speeds up an entire (comprehensive) simulation, In addition, the present invention relates to an operation verification simulation execution method, a simulation execution device, and a program for preventing the loss of simulation information.

[0002]

2. Description of the Related Art Conventionally, printers, facsimile machines (hereinafter referred to as electronic devices), etc., are controlled by a control system (only CPU, such as CPU or microcomputer).
It's doing that. This CPU executes a firmware program stored in a ROM or the like to execute various controls. At the development stage of such a firmware program, it is necessary to verify in advance whether the actual control operation by this program is normally performed.

As this verification, the actual control operation is modeled on a computer or a dedicated device (hereinafter, only the computer is shown), that is, a simulation for creating a simulated operation to optimize the control operation is repeated and verified. A simulation is performed (simulated). In this simulation, a partial simulation in which various model units that perform actual control operations of electronic devices are modularized on a computer is repeated, and the entire (comprehensive) operation verification simulation is executed.

FIG. 9 is a block diagram showing the structure of a conventional simulator. FIG. 9 is a simulator configuration example of an electronic device. The simulator of this example performs interface connection with a simulation control unit 101 for executing simulation control and a user device (computer or dedicated device for performing operation verification simulation). A user interface (I / F) unit 102 is connected to the bus line. In addition, this simulator is configured by connecting a CPU model unit 103 and I / O model units 104 provided corresponding to the number of peripheral I / O circuits of an electronic device that executes a simulation to a bus line.

Next, an operation verification simulation in this configuration will be described. When the simulation is started, the simulation control unit 101 causes the CPU to operate at regular intervals (generally, at each system clock frequency).
The model unit 103 is called. The CPU model unit 103
Each time it is called, the simulation is executed at the clock frequency of the calling interval. As a specific example, C
At a PU clock frequency of 400 MHz and a system clock frequency of 80 MHz, the CPU model unit 103 is called for each system clock frequency. Each time this is called, the CPU clock frequency is equivalent to 5 clock signals (4
(00 MHz / 80 MHz = 5 MHz) is executed.

The I / O model unit 104 is called by the CPU model unit 103 executing an I / O control command, and executes a simulation of a predetermined operation. At this time, if the predetermined operation does not end with the same clock signal, the simulation control unit 101 is set to the I / O model unit 1
04 notifies that it is in operation, and after this event notification, it is called from the simulation control unit 101 at regular intervals, as in the CPU model unit 103. When the predetermined operation ends, the I / O model unit 104 notifies the simulation control unit 101 of this end. After this I
The / O model unit 104 is the simulation control unit 101.
Will not be called from. In addition, the I / O model unit 104
When the simulation control unit 101 is interrupted by, the simulation control unit 101 notifies the CPU model unit 103 of the event of the interrupt.

Thus, the CPU model unit 103 and I
The / O model unit 104 apparently operates in parallel while executing the simulation. In the host computer in which a plurality of CPUs are arranged, in contrast to the simulator of FIG. 9 described above, the CPU model unit 103 and the I / O model unit 1
By performing simulation with 04 and a plurality of processes (or threads), high-speed simulation can be performed by actually operating in parallel instead of appearance.

[0008]

The above-mentioned conventional example has the following disadvantages (1), (2), and (3). (1) The CPU model unit 103 is always operating. Therefore, we are performing a wasteful loop simulation,
As a result, the simulation speed decreases. This is because in the actual electronic device, the CPU and the peripheral I / O circuit operate while establishing synchronization. That is, CP
After activating the peripheral I / O circuit, U may be waiting until the processing of the peripheral I / O circuit is completed when some processing is completed. In this case, the source code (source program) is looped.

FIG. 10 is a diagram for explaining a conventional source code. For example, the CPU of the electronic device performs the loop processing of the source code shown in FIG. In this example, when the interrupt from the peripheral I / O circuit occurs, the variable "Interrupt" is set to "true" in the interrupt routine, and then the loop is exited.

(2) If the simulation is performed on a host computer provided with a plurality of CPUs,
If the number of CPUs is larger than the number of generated processes (or threads), the simulation speed does not decrease. However, in the configuration in which the electronic device that executes the simulation includes a plurality of peripheral I / O circuits, the process (or thread) generated during the execution of the simulation is C
If the number is larger than the number of PUs, the simulation speed will decrease.

(3) For example, when the CPU model section is not executing the simulation, the simulation result is not updated, so that the simulation information may be lost during the standby of the CPU model section, resulting in a reliable simulation. May not be possible.

The present invention has been made in view of the above points, and an object thereof is to provide an operation verification simulation execution method, a simulation execution apparatus, and a program capable of accelerating the overall (comprehensive) simulation.

Another object of the present invention is to provide an execution method, a simulation execution device, and a program of an operation verification simulation, in which simulation information is not lost and a reliable simulation can be performed.

[0014]

In order to achieve the above object, the execution method of the operation verification simulation of the present invention is
A control system model part that models the processing of the control system, a model operation setting part that sets the operation to the control system model part, and at least one input / output model part that models the peripheral input / output of the simulation target device. In order to execute the operation verification simulation, the model operation setting unit sets the control system model unit to the standby state at a predetermined timing after the input / output model unit operates, and the simulation is skipped. A step in which the model operation setting section recognizes an event notification including an interrupt from the output model section; and a step in which after the model operation setting section is recognized, the control system model section is returned to the operating state by the model operation setting section and the simulation is restarted. In addition, a predetermined timing after the input / output model section is operated is set in the address storage section. It is characterized in that is based on the address value.

In the above-described method of the present invention, when the control system model section is executing a loop meaningless in processing in a waiting state for an interrupt from the input / output model section,
The simulation of the control system model part can be omitted. As a result, the whole operation verification simulation is speeded up.

Further, the execution method of the operation verification simulation of the present invention includes a simulation control section for controlling the simulation, a control system model section for modeling the processing of the control system, and statistical information for storing statistical information in the simulation execution. A memory unit and at least one input / output model unit that models the peripheral input / output of the simulation target device are used to execute the operation verification simulation. At a predetermined timing after the input / output model unit operates, A step of storing the simulation result of the control system model section in the statistical information storage section under the control of the simulation control section, and a simulation based on the stored information in the statistical information storage section after the storage, instead of executing the simulation of the control system model section. The result is controlled by the simulation controller. The step of updating, the step of the simulation control unit recognizing the event notification including the interrupt from the input / output model unit, and the recognition system is restarted after the recognition when the control system model unit is not executing the simulation. And a predetermined timing after the operation of the input / output model section is based on the address value set in the address storage section.

In the above-described method of the present invention, the control system model unit updates the simulation result using the stored information in the statistical information storage unit even when the simulation is not executed. While waiting, the simulation information that has been lost in the invention (claim 1) described above is not lost in the invention (claim 3), and the reliable operation verification simulation is executed.

The simulation execution apparatus of the present invention is a control system model means for modeling the processing of the control system, a simulation control means for executing the simulation control, and at least one modeled peripheral input / output of the simulation target apparatus. One input / output model means and an operation setting means for setting the operation of the control system model means in cooperation with the simulation control means. The simulation control means and the operation setting means provide predetermined timing after the operation of the input / output model means. Then, the control system model means is set to the standby state, the simulation is omitted, and the control system model means is set back to the operating state after the recognition of the event notification including the interrupt from the input / output model means. .

Further, the simulation executing apparatus of the present invention is a control system model means for modeling the processing of the control system, a simulation control means for executing the simulation control, and a statistic for storing statistical information of the result of the simulation execution. The control system model has an information storage unit and at least one input / output model unit that models the peripheral input / output of the simulation target device, and is controlled by the simulation control unit at a predetermined timing after the operation of the input / output model unit. The control system model means performs simulation after storing the simulation result of the means in the statistical information storage means, updating the simulation result based on the statistical information after the storage, and recognizing the event notification including the interrupt from the input / output model means. Is not running It is characterized by performing the setting for returning the control system model unit into operation.

In the above-described apparatus of the present invention, as in the case of the above-described method invention, the speed of the whole simulation is increased and a reliable operation verification simulation is executed.

Further, the program of the present invention causes a computer to execute the following control in the operation verification simulation. At a predetermined timing after the I / O model unit operates, the model operation setting unit sets the control system model unit to the standby state to omit the simulation, and the event notification including the interrupt from the I / O model unit is modeled Control recognized by the setting unit, control for returning the control system model unit to the operating state by the model operation setting unit and restarting simulation after the model operation setting unit is recognized.

Further, the program of the present invention causes a computer to substantially execute the following control in the operation verification simulation. At a predetermined timing after the operation of the input / output model unit, the simulation control unit controls the simulation result of the control system model unit to be stored in the statistical information storage unit. The simulation result based on the stored information in the statistical information storage unit,
Update control under the control of the simulation control unit, control in which the simulation control unit recognizes an event notification including an interrupt from the input / output model unit, and after this recognition, the control system model unit does not execute simulation In this case, control for returning the control system model section to the operating state.

With the above-described program of the present invention, the present invention can be provided as an information recording medium, for example, package software, and the operation verification simulation of the present invention can be executed by a computer or a dedicated device. The property is improved.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of an operation verification simulation executing method, a simulation executing apparatus, and a program of the present invention will be described in detail with reference to the drawings. <First Embodiment> This first embodiment corresponds to the above-described object (to speed up the overall (comprehensive) operation verification simulation). FIG. 1 is a block diagram showing the configuration of the simulator according to the first embodiment of the present invention. In FIG. 1, this example shows a simulation control unit 201 for executing control of operation verification simulation in an electronic device (printer or facsimile machine).
(Simulation control unit / means in claims), a user I / F unit 202 for interface connection with a user device (computer or dedicated device for performing operation verification simulation), and CPU model unit 203 (control system model in claims) Part / means) is connected to the bus line.

Further, this simulator is provided in correspondence with the number of peripheral I / O circuits of an electronic device having a CPU (corresponding to the control system in the claims / including a microcomputer and a dedicated control device) for executing a simulation. I
/ O model unit 204 (the input / output model unit in the claims /
Unit), a model operation setting unit 205 for setting a model operation, and an address storage unit 206 that stores in advance an address value at which an operation is omitted are connected to a bus line.

Next, the operation (processing) of the first embodiment will be described. The model operation setting unit 205, when the execution address of the CPU model unit 203 reaches the address value stored in the address storage unit 206 (corresponding to “the one based on the address value” in the claims), the CPU model The unit 203 is set to the standby state so that the simulation is not executed.

The model operation setting unit 205 is a CPU
While the model unit 203 is in the standby state, the I / O model unit 20
4 simulation is executed, and the interrupt event is sent from the I / O model unit 204 to the CPU model unit 2
When 03 is notified, the CPU model unit 203 is set to the operating state and the simulation of the CPU model unit 203 is restarted.

The address storage unit 206 preliminarily examines and stores the address value of the portion of the firmware program executed by the CPU that waits for the end of the operation of the I / O model unit 204, as the address value at which the above-described operation is omitted. ing.

Next, the whole (comprehensive) of the first embodiment
The operation verification simulation will be described in detail.
FIG. 2 is a flowchart showing the processing procedure of the operation verification simulation in the first embodiment. 1 and 2
In, the simulation control unit 201 executes the loop processing based on the advance of the clock signal at the set interval. First, in this loop, the simulation control unit 201 determines whether the clock signal for the set interval advances (step S301) and the CPU model unit 203 is operating or waiting (step S302). If it is determined that the operation is in progress (S302: Yes), the simulation control unit 201 calls the CPU model unit 203 and executes the A subroutine shown in FIG. 3 described later (step S303).

Next, the simulation controller 201
It is determined whether the I / O model unit 204 is in operation or in standby (step S304). Here, in the case of determination during operation (S
304: Yes), the simulation control unit 201
The I / O model unit 204 is called, and the B subroutine shown in FIG. 4 described later is executed (step S30).
5). Furthermore, it is determined whether or not the user (operation verification simulation executor) has designated the end of the simulation for the user device (the computer or the dedicated device that executes the operation verification simulation). Ends (step S306).

If the end is not designated in step S306 (S306: No), the process returns to step S301 to re-execute the subsequent processing. In addition, in steps S302 and S303, if each is not in operation (S
302: No, S303: No), and the process of step S306 (whether or not the simulation end is designated is determined) is executed.

Next, the A subroutine (call processing) in FIG. 2 will be described in detail. FIG. 3 is a detailed flowchart of the A subroutine in FIG. 1 to 3, in step S303 in FIG. 2, first, the CPU model unit 203 called by the simulation control unit 201 determines how many times the CPU can operate at a set clock interval (for example, a CPU clock frequency of 400 MHz).
/ System clock frequency 80 MHz = 5 MHz) is set in a counter not shown (step S303a), and I
It is determined whether or not the interrupt event is notified from the / O model unit 204 (step S303b), and if the event is notified here (Yes), the execution address value is changed to the interrupt processing address value (step S3).
03c).

Next, the simulation controller 201
The counter value is checked (step S303d), and if the value is not "zero" (No), CPU instruction execution is simulated (step S303e). In this case, the executed instruction is I / O controlled by the I / O control instruction.
When the model unit 204 is in the standby state, the simulation control unit 201 sets the I / O model unit 204 in operation. When the counter value is "zero" (S3
03d: Yes), and the processing of the CPU model unit 203 ends.

Further, the simulation controller 201
Determines whether the next execution address value is the address value stored in the address storage unit 206 (step S3).
03f). Here, the execution address value is the address storage unit 20.
If the address value is not stored in 6 (S303
f: No), the process returns to step S303d, and
In case of stored address value (S303f: Ye
s), the CPU model unit 203 is set to the standby state and the process ends (step S303g). Note that step S30
In 3f and S303g, the address storage unit 206 is compared with the current execution address value, and the CPU model unit 203
If the address value you want to skip is reached, the CPU
The model unit 203 is set to a standby state.

Next, the B subroutine (call processing) in FIG. 2 will be described in detail. FIG. 4 is a detailed flowchart of the B subroutine in FIG. 1, 2 and 4
2, in step S305 in FIG. 2, first, the I / O called by the simulation control unit 201 is called.
The model unit 204 sets the number of I / O operations possible in a counter (not shown) at clock signal intervals (step S30).
5a). Next, the counter value is checked (step S305
b), if the counter value is not "zero" (S305b:
No), the simulation of the I / O model unit 204 is executed (step S305c). Based on the simulation result, the simulation control unit 201 determines whether or not an interrupt event has occurred from the I / O model unit 204 (step S305d).

When an interrupt event occurs (S30
5d: Yes), the simulation control unit 201 displays C
The PU model unit 203 is notified of the interrupt event, and the CP
Step S30 after changing and setting the U model unit 203 to the operation
It returns to 5b (step S305e). In this case, when the CPU model unit 203 is on standby, the setting for returning to the operating state is made. If the counter value is “zero” in step S305c (Yes), the simulation control unit 2
01 determines whether or not the predetermined operation of the I / O model unit 204 is completed (step S305f), and if it is completed (Yes), the I / O model unit 204 is set to the standby state and then the operation is terminated. (Step S305g). In addition,
If the predetermined operation of the I / O model unit 204 is not completed in step S305f (No), the operation is also completed.

As described above, in the operation verification simulation of the first embodiment, the CPU model unit 203 makes the I / O
In the waiting state of the interrupt from the O model unit 204,
When processing a meaningless loop, CP
The simulation of the U model unit 203 can be omitted. As a result, the speed of the whole operation verification simulation can be increased.

<Second Embodiment> This second embodiment corresponds to the above-described other purpose (prevents loss of simulation information and enables reliable operation verification simulation). FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention. In FIG. 5, in the second embodiment, a user I / F unit 4 for performing interface connection with a user device is provided together with a simulation control unit 401 (simulation control unit / means in claims) for executing simulation control.
02, a CPU model unit 403 (control system model unit / means in claims), and a simulation,
For example, an I / O model unit 404 (input / output in the claims is provided corresponding to the number of peripheral I / O circuits of an electronic device having a CPU (corresponding to the control system in the claims / including a microcomputer and a dedicated controller)) An output model unit / means) is connected to the bus line.

Further, in the second embodiment, the statistical information storage unit (2) 405 (statistical information storage unit / means in claims) for temporarily storing statistical information, the address storage unit 406, and the entire simulation are used. The statistical information storage unit (1) 407 that collects and stores the statistical information of 1 is connected to each bus line.

The statistical information is the number of instructions executed by the firmware program for simulation, such as the number of executed instructions and the cache hit rate. The address storage unit 406 is a firmware program I executed by a CPU of an electronic device (not shown).
The standby state after the operation of the / O model unit 404 is stored as an address value, and the address value of the simulation program for which the simulation is to be omitted and the address value of the firmware program for which the simulation is to be ended are stored in advance.

Next, the operation (processing) of the second embodiment will be described. In FIG. 5, in the simulator of the second embodiment, when the execution address value of the CPU model unit 403 reaches the stored address value, the simulation is performed only during the first loop processing in the same repetitive processing. Run. The statistical information of this simulation result is stored in the statistical information storage unit 405. After this, C
The simulation is not executed when the PU model unit 403 is called, and only the simulation result is updated by the stored statistical information. The interrupt event from the I / O model unit 404 is the CPU model unit 403.
Is notified, the CPU model unit 403 restarts the simulation.

Next, the whole (comprehensive) of the second embodiment
The operation verification simulation will be described in detail. FIG. 6 is a flowchart showing the processing procedure of the operation verification simulation in the second embodiment. In FIGS. 5 and 6, the simulation control unit 401 executes the loop processing of steps S501 to S505 when the clock signal advances at the set interval. In this loop processing, first, the clock signal is advanced by the set interval (step S50).
1) Next, the simulation control unit 401
The PU model unit 403 is called, and the C subroutine shown in FIG. 7 described in detail below is executed (step S5).
02).

After this subroutine, the simulation control unit 401 determines whether the I / O model unit 404 is in operation (step S503). If it is in operation (Yes)
s), the I / O model unit 404 is called, and the D subroutine shown in FIG. 8 described in detail below is executed (step S504). After this D subroutine, the simulation control unit 401 determines whether or not the user has designated termination of the user device (step S50).
5) If the end is designated (Yes), the process ends. In addition, when it is not in operation in step S503 (No), in step S505, the end designation is judged from the user to the user device, and the process ends.

Next, the C subroutine (call processing) in FIG. 6 will be described in detail. FIG. 7 is a detailed flowchart of the A subroutine in FIG. 5 to 7, in step S502 in FIG. 6, the CPU model unit 40 called by the simulation control unit 401.
3 first sets the number of times the CPU can operate at the set clock interval in the counter of the user device (not shown) (step S504a), and determines whether or not an interrupt event is notified from the I / O model unit 404. (Step S504b), if the event notification is performed (Yes
s), the execution address value is changed to the interrupt processing address value (step S504c), and the operation state is set to a normal simulation that does not use statistical information.

Next, the simulation controller 401
The above-mentioned counter value is checked (step S504d), and if this counter value is not "zero" (Yes), the current operating state is sorted into the following (1), (2), and (3) (step S504e). (1) Operating state When the operating state is a normal simulation that does not use statistical information (steps S504f, S504g, S504)
h). (2) When the process after the address value set in the operating state address storage unit 406 is in the first state (step S50)
4i, S504j, S504k, S504l). (3) When it is in the state where the processing after the address value set in the operation state address storage unit 406 is performed for the second time (step S504)
m). (1) In the operating state, the simulation control unit 401 first simulates instruction execution (step S504f), and when this instruction execution is an I / O control instruction and the I / O model unit 404 is in a standby state, That I
The / O model unit 404 is set during operation. Further, it is determined whether or not the next execution address value is the address value stored in the address storage unit 406 (step S504).
g). When the execution address value is not the address value stored in the address storage unit 406 (S504g: No),
The process returns to step S504d. When the execution address value is the address value stored in the address storage unit 406 (S504g: Yes), the operation state is changed to the above-described operation state (steps S504i to S504l) and the step S50 is performed.
It returns to 4d (step S504h).

(2) In the operating state, the instruction execution is simulated (step S504i), and the simulation result is stored in the statistical information storage unit 405 (step S504j). Next, it is determined whether the execution address value is the address value stored in the address storage unit 406 (step S504k). When the execution address value is not the address value stored in the address storage unit 406 (S
504k: No), and returns to step S504d. When the execution address value is the address value stored in the address storage unit 406 (S504k: Yes), the operation state is changed to the above-described operation state (step S504m) and the process returns to step S504d (step S504l).

(3) In the operating state, the statistical information storage unit 40
The simulation result is updated based on the statistical information stored in step S5, and the process returns to step S504d (step S504m). When the counter value is "zero" by these processes (S504d: No), the process ends.

Next, the D subroutine (call processing) in FIG. 6 will be described in detail. FIG. 8 is a detailed flowchart of the D subroutine in FIG. 5, 6 and 8
In step S504 in FIG. 6, the called I / O model unit 404 sets the number of times the I / O circuit of the electronic device (not shown) can operate at the set clock interval in the counter (step S504a). . next,
The counter value of the user device (not shown) is checked (step S504b). If the counter value is not “zero” in this check (No), the operation of the I / O model unit 404 is simulated (step S504c).

Next, the simulation controller 401
It is determined from the simulation result whether or not an interrupt from the I / O model unit 404 has occurred (step S504).
d), if an interrupt occurs (step S504d:
Yes), the CPU model unit 403 is notified of the interrupt event (step S504e), and the process returns to step S504b. If the counter value is “zero” in step S504b (Yes), the simulation control unit 401
Determines whether or not the I / O model unit 404 has completed the predetermined operation (step S507f), and if it has completed (Yes), after setting the I / O model unit 404 to the standby state, The process ends (step S507).
g). In step S507f, the I / O model unit 40
Even when 4 has not finished the predetermined operation, the processing is finished.

As described above, in the second embodiment, the CP
When the U model unit 403 is in a standby state in which an interrupt signal is input from the I / O model unit 404 and is executing a meaningless loop, the simulation of the CPU model unit 403 can be omitted. Speedup of dynamic verification simulation.

Further, in the simulator of the second embodiment,
Even when the CPU model unit 403 is not performing a simulation, the simulation result is updated using the statistical information stored in the statistical information storage unit 407. Therefore, although the speed is slower than that of the simulator of the first embodiment, the simulation information that was lost while the CPU model unit 403 was waiting in the simulator of the first embodiment is not lost in the second embodiment.

[0052]

As is apparent from the above description, according to the present invention, the control system model unit (means) executes a meaningless loop in processing the interrupt waiting state from the input / output model unit (means). If so, the simulation of the control system model can be omitted. As a result, there is an effect that the whole (comprehensive) operation verification simulation can be speeded up.

Further, according to the present invention, even when the simulation is not performed by the control system model section (means),
The simulation result is updated using the storage information of the statistical information storage unit (means). Therefore, it is possible to prevent the simulation information, which has been lost while the control system model is waiting, from being lost in the present invention. As a result, there is an effect that a reliable operation verification simulation becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in a first embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure of an operation verification simulation in the first embodiment.

FIG. 3 is a detailed flowchart of a subroutine shown in FIG.

FIG. 4 is a detailed flowchart of another subroutine in FIG.

FIG. 5 is a block diagram showing a configuration according to a second exemplary embodiment of the present invention.

FIG. 6 is a flowchart showing a processing procedure of an operation verification simulation in the second embodiment.

7 is a detailed flowchart of a subroutine shown in FIG.

FIG. 8 is a detailed flowchart of another subroutine in FIG.

FIG. 9 is a block diagram showing a configuration of a conventional simulator.

FIG. 10 is a diagram for explaining a conventional source code.

[Explanation of symbols]

201,401 Simulation control unit 202,402 User I / F section 203,403 CPU model section 204,404 I / O model section 205 Model operation setting section 206, 406 Address storage unit 405, 407 Statistical information storage unit

Claims (7)

[Claims] 1. A control system model part that models the processing of the control system, a model operation setting part that sets the operation to the control system model part, and at least one input that models the peripheral input / output of the simulation target device. In a method of performing an operation verification simulation with an output model unit, at a predetermined timing after the input / output model unit operates,
A step in which the model operation setting section sets the control system model section to a standby state and omits simulation; a step in which the model operation setting section recognizes an event notification including an interrupt from the input / output model section; And a step of returning the control system model section to the operating state by the model operation setting section and restarting the simulation after the model operation setting section is recognized. 2. A simulation control unit for controlling simulation, a control system model unit that models processing of a control system, a statistical information storage unit for storing statistical information in simulation execution, and peripheral input / output of a simulation target device. In a method of performing an operation verification simulation having at least one input / output model unit that models the above, at a predetermined timing after the input / output model unit operates,
A step of storing the simulation result of the control system model section in the statistical information storage section under the control of the simulation control section; and a step of storing the simulation result of the control system model section in the statistical information storage section after execution of simulation of the control system model section. Updating the simulation result based on the stored information under the control of the simulation control unit; the simulation control unit recognizing an event notification including an interrupt from the input / output model unit; And a step of restarting the simulation when the control system model section is not executing the simulation, and a method of executing the operation verification simulation, comprising: 3. The operation verification simulation according to claim 1, wherein the predetermined timing after the operation of the input / output model section is based on the address value set in the address storage section. How to run. 4. In a device for executing simulation, control system modeling means for modeling processing of a control system, simulation control means for executing simulation control, and at least peripheral input / output of a simulation target device are modeled. One input / output model means and operation setting means for setting the operation of the control system model means in cooperation with the simulation control means, and the input / output model means by the simulation control means and the operation setting means. At a predetermined timing after the operation of, the control system model means is set to the standby state to omit the simulation, and the control system model means is put into the operation state after the recognition of the event notification including the interrupt from the input / output model means. Simulation execution characterized by setting to return Location. 5. In a device for executing a simulation, a control system model means for modeling processing of a control system, a simulation control means for executing a simulation control, and statistical information for storing statistical information of a result of the simulation execution. Storage means, and at least one input / output model means modeling the peripheral input / output of the device to be simulated, under the control of the simulation control means, at a predetermined timing after the operation of the input / output model means, The simulation result of the control system model means is stored in the statistical information storage means, the simulation result based on the statistical information is updated after this storage, and after the event notification including the interrupt from the input / output model means is recognized, Control system model means simulation A simulation executing apparatus, characterized in that the control system model means is set to return to an operating state when not executing. 6. A program for causing a substantial computer to execute the following control in the operation verification simulation. At a predetermined timing after the input / output model section operates,
Control of the control system model is set by the model operation setting section to the standby state and the simulation is skipped Control for recognizing event notification including interrupt from the input / output model section Recognition of the model operation setting section Control for returning the control system model unit to the operating state by the model operation setting unit and restarting the simulation later 7. A program for causing a substantial computer to execute the following control in the operation verification simulation. At a predetermined timing after the input / output model section operates,
Control of storing the simulation result of the control system model unit in the statistical information storage unit by the control of the simulation control unit After this, the simulation result based on the storage information in the statistical information storage unit replaced with the execution of the simulation of the control system model unit, Control updating by control of the simulation control unit The simulation control unit recognizes an event notification including an interrupt from the input / output model unit After this recognition, when the control system model unit is not executing a simulation , Control for returning the control system model means to the operating state