JPH0635988A - Logic simulation system - Google Patents

Abstract

PURPOSE:To prevent a program from stopping proceeding by generated fault by a specific instruction recognized to already have some problem at a logic simulator for simulating a gate level in a logic simulation system. CONSTITUTION:The specific instruction recognized to already have some problem is registered on a suppressing instruction registering means 22. When the program is executed by activating a software simulator 1 and a logic simulator transfer judging means 11 recognizes the instruction of a transfer to a logic simulator 2, the logic simulator 2 is activated, and state information at that point of time is set in the simulator. A suppressing instruction judging means 22 investigates that the next instruction is not registered instruction and when a software simulator transfer judging means 24 recognizes that the instruction is not the instruction of transfer to the software simulator, a logic simulator instruction executing means 25 executes the instruction and repeats the same processing by the next instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method, and more particularly to a logic simulator for performing gate level simulation for confirming the normality of a hardware logic model of a central processing unit and a software simulator for performing program instruction level simulation. Of the logic simulation method.

[0002]

2. Description of the Related Art Conventionally, in this type of logic simulation method, a transfer instruction for instructing the start and end of execution of the logic simulator is expanded on a program of a software simulator, and the execution of this instruction is used as a trigger for the logic simulator. It controls the start and end of execution.

[0003]

In the above-mentioned conventional logic simulation method, when a logic simulator including a known problem is executed to verify other problems,
Since the program is always executed by the logic simulator between transfer instructions, there is a drawback that the problem that a specific instruction due to a known problem causes a failure and the program cannot proceed further can not be avoided.

[0004]

The logic simulation method of the present invention is a logic simulation method comprising a logic simulator for performing gate level simulation for confirming the normality of a logic circuit and a software simulator for performing instruction level simulation. In the above, there are provided a restraint instruction registering means for registering before the execution of the instruction program for restraining the execution by the instruction of the logic simulator, and a software simulator for judging whether the instruction executed by the software simulator is a transfer instruction to the logic simulator. When the logic simulator transfer determination means determines a transfer instruction, the logic simulator transfer determination means determines whether the next instruction is an instruction registered in the inhibition instruction registration means, and This command A) Instructing means provided in the logic simulator for notifying the simulator to execute, and determining whether the instruction judged by the inhibiting instruction judging means is not the inhibiting instruction is not a transferring instruction to the software simulator. When judged, execute the command,
When the transfer instruction is a transfer instruction, the transfer is notified to the software simulator, and the software transfer determination means provided in the logic simulator that causes subsequent instructions to be executed by the software simulator and the instruction instructed by the software transfer determination means are executed. It comprises logic simulator instruction execution means for causing the inhibition instruction determination means to execute / inhibit the next instruction.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

In the embodiment shown in FIG. 1, a central processing unit software simulator 1 and a central processing unit logic simulator 2 are provided.
The software simulator 1 includes a logic simulator transfer determination means 11 for determining a transfer instruction for executing a program in the logic simulator, a software simulator instruction execution means 12 for executing an instruction, and information about the logic simulator. The logic simulator 2 comprises a software simulator information transmitting / receiving means 13 for transmitting / receiving, and the logic simulator 2 transmits / receives information to / from the software simulator 1.
1. Suppressing instruction registering means 22 for registering an instruction to be executed by the software simulator 1. Suppressing instruction determining means 23 for determining whether the instruction is registered by the inhibiting instruction registering means 22 during program execution. Software simulator transfer determination means 2 for determining whether a transfer instruction is to be executed by the simulator 1
4 and the logic simulator instruction executing means 25.

FIG. 2 is a flow chart of processing of the embodiment shown in FIG. The operation of the embodiment shown in FIG. 1 will be described below with reference to FIG. First, an instruction for which execution in the logic simulator 2 is known to be problematic in gate-level simulation is to be registered in the logic simulator 2 by the inhibition instruction registration means 22 (step 101). Next, the software simulator 1 is activated (step 102) and the program is executed. In the software simulator 1, the logic simulator transfer determination means 11 determines whether the instruction to be executed is a transfer instruction to the logic simulator 2 (step 103). At this time, if the execution instruction is not the transfer instruction, the software simulator instruction execution means 12 executes it (step 104). After the instruction is executed, it is judged whether the program is finished (step 105). If it is not finished, the process returns to the transfer instruction judgment processing of step 103. Step 1
When the transfer instruction to the logic simulator 2 is detected in the transfer determination processing of 03, the logic simulator transfer determination means 11 notifies the software simulator information transmitting / receiving means 13 that the transfer instruction is detected. The software simulator information transmitting / receiving means 13 activates the logic simulator 2 (step 106) and transfers the software simulator information indicating the state of the software simulator 1 at the time of detecting the transfer instruction to the logic simulator information transmitting / receiving 21 (step 107). The logic simulator information transmission / reception means 21 sets the transferred software simulator information, and informs the inhibition instruction determination means 23 of the transfer. The inhibition instruction determination means 23 restarts the processing from the instruction next to the transfer instruction, and the execution instruction is the inhibition instruction registration means 2
It is determined whether or not the instruction is registered in step 2 (step 108). If the execution instruction is not the instruction registered by the inhibition instruction registration means 22, then it is determined whether the instruction executed by the software simulator transfer determination means 24 is a transfer instruction to the software simulator 1 (step 109). If the execution instruction is not a transfer instruction, the logic simulator instruction execution means 25 executes it (step 110). After executing the instruction, the inhibition instruction determining means 23
However, the process returns to step 108 for determining whether the next command is a command registered by the inhibition command registration means 22.
When the software simulator transfer determination means 24 in step 109 detects the transfer instruction in the process of determining the transfer instruction to the software simulator 1,
The software simulator transfer determination means 24 notifies the logic simulator information transmission / reception means 21 that the transfer instruction has been detected. The logic simulator information transmitting / receiving means 21 activates the software simulator 1 (step 11
1) The logic simulator information indicating the state of the logic simulator at the time of detecting the transfer instruction is transferred to the software simulator information transmitting / receiving means 13 (step 112). The software simulator information transmission / reception means 13 sets the transferred logic simulator information and notifies the logic simulator transfer determination means 11 of the transfer. The logic simulator transfer determination means 11 returns to step 103, restarts processing from the instruction following the transfer instruction, and executes processing to determine whether the execution instruction is a transfer instruction. In step 108, the inhibition instruction determination means 2 of the logic simulator 2
When 3 detects the instruction registered by the inhibiting instruction registering means 22, it informs the logic simulator information transmitting / receiving means 21 that the inhibiting instruction is detected. The logic simulator information transmission / reception means 21 activates the software simulator 1 (step 113), and transfers the logic simulator information at the time when the instruction registered by the inhibition instruction registration means 22 is detected to the software simulator information transmission / reception means 13 (step 114). . The software simulator information transmission / reception means 13 sets the transferred logic simulator information, and the software simulator instruction execution means 12 executes the instruction registered by the inhibition instruction registration means 22 (step 115). After executing the instruction, the software simulator information transmitting / receiving means 13 returns to the processing of step 106 for starting the logic simulator 2. The above processing is repeated until the program ends.

[0008]

As described above, according to the present invention, an instruction having a problem is registered in advance in the logic simulator, and whether or not the execution which is registered when transferring from the software simulator to the logic simulator should be suppressed. Since the software simulator executes the instruction that suppresses the execution in the logic simulator, it is possible to solve the problem that a specific instruction fails due to a known problem and the subsequent instruction sequence cannot be processed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flow chart of processing of the embodiment of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 software simulator 2 logic simulator 11 logic simulator transfer determination means 12 software simulator instruction execution means 13 software simulator information transmission / reception means 21 logic simulator information transmission / reception means 22 inhibition instruction registration means 23 inhibition instruction determination means 24 software simulator transition determination means 25 logic Simulator instruction execution means

Claims (1)

[Claims] 1. In a logic simulation method comprising a logic simulator for performing gate level simulation for confirming the normality of a logic circuit and a software simulator for performing instruction level simulation, execution is suppressed by an instruction of the logic simulator. Suppressing instruction registering means for registering an instruction before execution of a program, logic simulator transfer judging means provided in a software simulator for judging whether an instruction executed by a software simulator is a transferring instruction to a logic simulator, and this logic. When the simulator transfer determination means determines a transfer instruction, it is determined whether the next instruction is an instruction registered in the inhibition instruction registration means, and if it is an inhibition instruction, this instruction is notified to the software simulator and executed. Logical simulation And a restraint instruction determining means provided in the computer, and whether the instruction determined by this restraint instruction determining means is not a restraint instruction is a transfer instruction to the software simulator, and when it is determined that it is not a transfer instruction, the instruction is executed, When the transfer instruction is a transfer instruction, the transfer is notified to the software simulator, the software transfer determination means provided in the logic simulator that causes subsequent instructions to be executed by the software simulator, and the instruction instructed by the software transfer determination means is executed. A logic simulation method comprising: a logic simulator instruction executing means for causing the inhibition instruction determining means to execute / inhibit the next instruction.