JP2828974B2 - Method for manufacturing compound semiconductor integrated circuit - Google Patents

Description

The present invention relates to a compound semiconductor MESFET, and particularly relates to a GaSFET.
The present invention relates to a method of manufacturing a semiconductor device in which As MESFETs are mainly integrated. [Prior art] Conventional GaAs MESFETs have high heat resistant gate electrodes (for example, tungsten silicide, WSi _x ) in order to improve the performance by minimizing the series resistance R _s8 of the gate electrode and the source electrode as much as possible.
It was made with a self-aligned structure using In order to form the n ⁺ − low resistance layer around the gate electrode in a self-aligned manner, a Si ion implantation technique and a selective growth technique are used. Selective growth layer is more than layer made by Si ion implantation.
It is easy to obtain a high impurity concentration, so it can reduce resistance.
The ion implantation requires an annealing temperature of 750 ° C. or higher, but the selective growth temperature can be as low as about 600 ° C. to 700 ° C., so that there is an advantage that deterioration of the shot junction of the gate electrode is small. However, selective growth also has disadvantages. For example, unit FE
For T and small-scale integrated circuits, what has not become a particular problem has become apparent in medium- and large-scale integrated circuits. That is, there is a problem that the selective growth depends on the coarse and dense patterns, and the thickness of the GaAs growth layer is large in the isolated pattern group and thin in the dense pattern group. At this film thickness, it exceeds the permissible limit for LSI fabrication.
800nm. Also, in the region of the isolated pattern that grows thick, crystal grains were precipitated in the unnecessary portions on the SiO ₂ film or the WSi _x film, resulting in poor appearance. This significantly reduces the yield of the wiring process, making it difficult to implement LSI. FETs obtained by n ⁺ selective growth are Japanese journals
Of Applied Physics 23,5 (1984) L342
From L345 Japanese Journal of Applied Physics, Vo
l.23, No. 5 (1984) PPL342-345). [Problems to be Solved by the Invention] The prior art described above does not consider the use of an LSI, and has a problem that the selectively grown film thickness has a coarse / fine dependence of the pattern. An object of the present invention is to solve the above-mentioned disadvantages and to manufacture an element by a selective growth technique suitable for LSI. [Means for Solving the Problems] For a technique for selectively growing GaAs only on the GaAs surface while avoiding the surface of SiO ₂ or WSi _x material, a growth method called MOCVD is mainly used. As a result of the experiment, the pattern
It turns out that there is a close dependency. In the experiment, using the isolated pattern A and the peripheral pattern B separated by a distance l as shown in FIG.
I asked. In the patterns A and B, the GaAs surface appears, and both are separated by SiO ₂ 40. The result is shown in FIG. The thickness d of the growth layer, when l is small, but the same thickness d ₀ and confluent thickness, l is rapidly growing thicker exceeds about 100 [mu] m, l is a thickness from about 250μm or more It has a tendency to saturate. Moreover, the growth conditions (temperature,
It was concluded that it was difficult to perform selective growth regardless of the coarseness and denseness of the pattern with flow rate, gas ratio, etc.). In order to solve this, it has been found that it is preferable to form a dummy pattern in which the pattern of the growth layer is uniformly dense in a rough region, and to perform crystal growth also on the dummy pattern. FIG. 5 shows that the distance between the present pattern and the dummy pattern must be at least within 100 μm. Also, since dummy patterns are grown on semi-insulating GaAs, care should be taken not to reduce the performance of integrated circuits. I used the arrangement of groups. As a result, even when the wiring layer passes over the dummy pattern, the wiring capacity does not increase as compared with the conventional structure without the dummy pattern. [Operation] By providing a dummy pattern close to the present pattern, the thickness of selective growth can be made uniform at any position on the wafer. EXAMPLES Hereinafter, one example of the present invention will be described below. FIG. 3 shows an element cross-sectional structure in the case where an FET, which is a key device of a GaAs LSI, is formed by self-alignment with an n ⁺ -GaAs selective growth layer. The gate electrodes 10 and 11 are WSi _x heat-resistant shot barriers, and windows for source and drain are formed in the SiO ₂ film on both sides of the gate, and the n ⁺ -GaAs layers 20 and 30 are selectively grown by MOCVD. I can. Unused portion is SiO ₂
Film 40, is on the SiO ₂ sidewalls 50 and WSi _x gate electrode 11. A memory circuit such as an SRAM is obtained by using a lot of such FETs. Although the pattern of the FET1 for selective growth is as shown in FIG. 3, in the memory circuit, a pattern region having a high density as shown in FIG. 1 (a) is locally arranged in the chip. I have. The hatched portion in FIG. 6A represents a memory cell portion pattern group 200 and peripheral circuit portion pattern groups 101 and 102. If the n ⁺ -GaAs layer is selectively grown with the pattern as shown in FIG. 4A, the layer becomes abnormally thick at the periphery of the dense pattern and cannot be used as an LSI. Therefore, as shown in FIG. 1 (b), a dummy pattern group 300 is arranged in a region where the growth pattern is unnecessary in the related art, and the patterns of FIGS. 1 (a) and (b) are formed on a wafer by overlapping. Selective growth is performed. FIG. 2 is an enlarged view of a boundary portion between the main pattern 300 and the dummy pattern 400 when the patterns of FIGS. 1A and 1B are overlapped. It is better that the distance 1 shown in this figure is reduced as long as it does not adversely affect the characteristics of the pattern, and is usually determined within the range of 5 to 50 μm. As shown in FIG. 2, the pattern of the dummy pattern is preferably the same as or close to that of the main pattern. Normally, a repeated pattern of the memory cell section 200 is used. Although the embodiment of the present invention has been described using the GaAs SRAM pattern, it is possible to obtain a uniform film thickness by selective growth by using a dummy pattern having the same purpose in various functional circuits including a single FET. Needless to say. According to the present invention [Effect of the Invention Since GaAs LSI has decreased to allow fabricated using n ⁺ -GaAs selective growth technique, as compared with the resistance of the n ⁺ layers to be formed by conventional ion implantation, about 1 A low resistance ratio of / 10 was achieved, which improved the series resistance of the FET to about 1/5. As a result, a memory element approximately twice as fast as the conventional one was obtained. This is a characteristic of the FET improved by the self-alignment of the n ⁺ -GaAs selective growth layer. However, in the conventional ion implantation, the short gate effect and the shot barrier are deteriorated by the heat treatment at 800 ° C. The performance was remarkably improved because nothing was done.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view of (a) the present pattern (b) of the dummy pattern according to one embodiment of the present invention, FIG. 2 is an enlarged view of a boundary between the present pattern and the dummy pattern, FIG. FIG. 4 shows the element diagram of the FET, FIG. 4 shows a pattern obtained by examining the coarse / fine dependency by selective growth, and FIG. 5 shows the result of an experiment using FIG. 1 ... GaAs substrate crystal, 101, 102 ... peripheral circuit part pattern, 200 ... memory cell part pattern, 300 ... dummy pattern.

Claims (1)

(57) [Claims] Forming a compound semiconductor on a compound semiconductor by using a selective growth technique, and forming a wiring layer after the selective growth of the compound semiconductor; Is applied to both the present pattern related to the function of the compound semiconductor integrated circuit and the dummy pattern not related to the function of the compound semiconductor integrated circuit having the divided repetitive pattern group, and the repetitive division of the wiring layer is performed. A method for manufacturing a compound semiconductor integrated circuit, wherein the method is formed so as to pass over a pattern group. 2. 2. The method according to claim 1, wherein the compound semiconductor formed by selective growth is GaAs. 3. The distance between the main pattern and the dummy pattern is 10
3. The method for manufacturing a compound semiconductor integrated circuit according to claim 1, wherein the thickness is within 0 μm. 4. 4. The method according to claim 1, wherein the pattern is a source and a drain of a field effect transistor.