JPH02210821A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the deposition of polycrystal grain of a mask on a mask by a method wherein a part of the mask is covered with a mask whose diffusion length is longer than the mask, and selective growth is performed by making the distance from the inside of the left mask to its peripheral selective growth layer smaller than the diffusion length of compound semiconductor on the mask. CONSTITUTION:Gate electrodes 10, 11 are made of heat-resistant Schottky metal. In SiO2 films 20, 20', windows for a source and a drain are formed on both sides of the gates, and an N<+> GaAs layer 30 is obtained by selective growth using MOCVD (organometallic chemical vapor deposition). The WSix gate electrode 11 is covered with the SiO2 film 20' because the deposition of GaAs polycrystal grain generates. The gate electrode 10 part is subjected to selective growth as it is, since the distance to the peripheral GaAs growth part is 1mum or less, and then the SiO2 film 20' covering the WSix gate electrode 11 is eliminated. After that, ohmic metal is deposited on the source.drain part, and wiring is formed. Thereby, an MESFET LSI can be manufactured without deposition of polycrystal grain.

Description

DETAILED DESCRIPTION OF THE INVENTION r Industrial Application Field The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for selective epitaxial growth of a compound semiconductor layer.

[Prior Art] Conventional GaAs MESFETs are described in Japanese Journal of Applied Physics (Japanese Journal of Applied Physics).
neeese Journal ofApplied
Physics) Vol, 23, No5 (19
84) As described in pp L342-345, using SiO2 and a heat-resistant gate electrode (e.g. tungsten silicide; WSix) as a mask, an n+ low resistance layer is grown as a source and drain around the gate electrode by selective growth technology. A self-alignment line was formed.

The selective growth layer is better than the layer made by Si ion implantation: ■ It is easier to obtain a high impurity concentration, so it can lower the resistance. ■ Ion implantation requires an annealing temperature of 750°C or higher, but the selective growth temperature is approximately 600 to 730°C. Since it can be made as low as ℃, there are advantages such as less deterioration of the Schottky junction of the gate electrode.

[Problem to be solved by the invention 1 However, in the selective growth described above, the gate material WSix
A problem arises in that polycrystalline grains of GaAs are precipitated thereon. If such precipitation occurs, the yield of the wiring process will be significantly lowered, making it difficult to fabricate into an LSI.

An object of the present invention is to eliminate such precipitation and to enable selective growth techniques to be applied, for example, to the fabrication of GaAs MESFET LSIs.

[Means for Solving the Problems] In the present invention, a part of the WSix mask whose distance from the inside to the surrounding GaAs growth part is 1 μm or more is covered with a SiO mask, and the remaining WSix part is covered with a surrounding GaAs growth part. The distance to the GaAs growth part on WSix is
The diffusion length should be equal to or less than the diffusion length of s.

A selective growth experiment was conducted by metal organic chemical vapor deposition (MOCVD method; normal pressure, growth temperature 700 to 730° C.) using a GaAs substrate with 5 inches of operation and WSix as a mask. As a result, the diffusion length of GaAs on the SiO2 mask was 20 μm, and on the WsiX mask was 1 μm. In the region where the distance from the inside of each mask to the peripheral selective growth region was less than the diffusion length of GaAs on that mask, precipitation of GaAs polycrystalline grains did not occur. To eliminate precipitation of polycrystalline grains, part of the WSix mask is made of Sin.

It can be seen that it is sufficient to further cover with a mask so that the distance from the inside of the remaining WSix mask to the peripheral selective growth portion is 1 μm or less. Furthermore, actual GaAs MES
Even if the size of the WSix mask used for manufacturing FET LSI is the largest, the distance from the inside to the surrounding selective growth part is less than 20 μm, and when covered with a SiO, GaAs polycrystalline grain. does not precipitate.

[Example] Hereinafter, one aspect of the present invention will be explained in detail.

Figure 2 shows FE, which is a key device of GaAs LSI.
The plan view and cross-sectional structure of an element in which T is formed using n'' GaAs selective growth technique are shown.

The gate electrodes 10 and 11 are made of WSix heat-resistant Schottky metal. Windows for sources and drains are opened in the SiO□ film on both sides of the gate, and an n'' GaAs layer 30 is obtained by selective growth using MOCVD.Growth Unused parts are Si
○2 membranes 20. Sin.

on the sidewalls 40 and the WSix gate electrode 10.11.

Many such FETs are used to provide memory modules such as SRAM.

The WSix gate electrode 11 shown in FIG. 2 has a distance of 1 μm or more from its inside to the surrounding GaAs growth area, and is selectively grown using the normal pressure MOCVD method (growth temperature 700 to 730°C). GaAs polycrystalline grains are precipitated.

Therefore, this part is as shown in Figure 1.

Even with the same gate electrode covered with 5in220', 1
The distance to the surrounding GaAs growth area is 1 for the 0 part.
Since it is less than μm, leave it as it is. After performing such treatment, selective growth is performed by MOCVD method. Next, the S i O covering the WSix gate electrode is removed. Thereafter, ohmic metal is deposited on the source and drain portions, wiring is formed, and a MESFET LSI is manufactured.

[Effects of the Invention] According to the present invention, the source and drain parts of a GaAs MESFET can be manufactured using n'' GaAs selective growth technology without precipitation of GaAs polycrystalline grains on the gate electrode WSix. Therefore, compared to the resistance of the n+ layer conventionally formed by ion implantation, it is possible to achieve a lower resistance of about 1710, and as a result, the source resistance of the FET can be reduced to about 175.As a result, a faster memory element than before can be obtained. be able to.

[Brief explanation of the drawing]

FIG. 1 is a plan view and a sectional view showing an FET pattern during selective growth according to an embodiment of the present invention, and FIG. 2 is a plan view and a sectional view showing an FET pattern used in the prior art during selective growth. Explanation of symbols 1...GaAs substrate crystal, lO...WSi gate, 11''・WS ix game h, 20.20'・
...S x Ox film. 1st eye

Claims (1)

[Claims] 1. In the step of selectively epitaxially growing the compound semiconductor 1 on the substrate of the compound semiconductor 2, as a mask material,
On top of that, a part of the mask 1 with a small diffusion length of the compound semiconductor 1 is covered with a mask 2 with a larger diffusion length, and the distance from the inside of the remaining mask 1 to the selective growth layer around it is A method for manufacturing a compound semiconductor device, characterized in that selective growth is performed with a diffusion length smaller than the diffusion length of the compound semiconductor 1 above. 2. GaAs as compound semiconductor 1, compound semiconductor 2
2. The method of manufacturing a compound semiconductor device according to claim 1, wherein GaAs is used as the compound semiconductor device. 3. GaAs as compound semiconductor 1, compound semiconductor 2
2. The method for manufacturing a compound semiconductor device according to claim 1, wherein AlGaAs is used as the material. 4. WSix as mask 1, SiO as mask 2
2. The method for manufacturing a compound semiconductor device according to claim 1, wherein _2 is used.