JP2822496B2 - Soldering lead pins to printed wiring board - Google Patents

Soldering lead pins to printed wiring board

Info

Publication number
JP2822496B2
JP2822496B2 JP1272308A JP27230889A JP2822496B2 JP 2822496 B2 JP2822496 B2 JP 2822496B2 JP 1272308 A JP1272308 A JP 1272308A JP 27230889 A JP27230889 A JP 27230889A JP 2822496 B2 JP2822496 B2 JP 2822496B2
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
semiconductor device
soldering
lead pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1272308A
Other languages
Japanese (ja)
Other versions
JPH03133166A (en
Inventor
陽一 笹沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1272308A priority Critical patent/JP2822496B2/en
Publication of JPH03133166A publication Critical patent/JPH03133166A/en
Application granted granted Critical
Publication of JP2822496B2 publication Critical patent/JP2822496B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔概 要〕 プリント配線板への半導体装置のリードピンの半田付
け方法に関し、 リードピンの先端を上向きに保持して半田付けを行う
場合の溶融半田の垂れ下がりを防止する確実な半田付け
方法の提供を目的とし、 上下両面に半導体装置を実装するプリント配線板のフ
ットプリントに半田を付着した後、該プリント配線板を
略水平に保持し、かつ下面側の該フットプリントに実装
する半導体装置のリードピンを、その先端部直下に予
め、半田垂れ下がり防止手段を設けて前記フットプリン
トに下から当接した状態で上下両面に同一工程で同時に
半田付けするように構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of soldering lead pins of a semiconductor device to a printed wiring board. To provide a soldering method, after attaching solder to a footprint of a printed wiring board on which semiconductor devices are mounted on both upper and lower surfaces, the printed wiring board is held substantially horizontally, and mounted on the footprint on the lower surface side The lead pins of the semiconductor device to be formed are provided with means for preventing solder dripping in advance immediately below the leading end thereof, and are simultaneously soldered to both the upper and lower surfaces in the same step in a state of contacting the footprint from below.

〔産業上の利用分野〕[Industrial applications]

本発明は、水平に保持した表面実装型プリント配線板
の上下両面にピン・グリッド・アレイ（Pin Grid Arra
y;以下PGAと略称する）型半導体装置を同時に半田付け
実装したプリント配線板に関する。The present invention provides a pin grid array (Pin Grid Arra) on both upper and lower surfaces of a horizontally mounted surface mount type printed wiring board.
y; hereinafter abbreviated as PGA) type semiconductor device.

〔従来の技術〕[Conventional technology]

第３図は従来のPGA型パッケージ構造の半導体装置の
正面概略図を示す。図において、１はPGA型パッケージ
構造の半導体装置であって、セラミックまたは樹脂モー
ルドで形成されるパッケージ２と、放熱フイン（発熱量
の少ない半導体の場合は付属しない）３と、丸棒状の導
電性部材をパッケージ２の裏面に格子状に植設して形成
された複数のリードピン４とから構成されている。FIG. 3 is a schematic front view of a conventional semiconductor device having a PGA type package structure. In the figure, reference numeral 1 denotes a semiconductor device having a PGA type package structure, a package 2 formed of a ceramic or resin mold, a heat radiation fin (not included in the case of a semiconductor having a small calorific value) 3, and a round bar-shaped conductive material. A plurality of lead pins 4 are formed by implanting members on the back surface of the package 2 in a lattice pattern.

第４図は従来の表面実装型PGAパッケージの半田付け
方法を説明するための要部断面図を示す。図において、
５は水平に保持されたプリント配線板、６はリードピン
４に接続されるべくプリント配線板５上に形成されたフ
ットプリントであって、このフットプリントの表面には
図示しない半田クリームを半田付けに先立って印刷して
おく。半導体装置１のリードピン４をそれぞれ半田付け
すべきフットプリント６に位置決めして配置し、この状
態を保持しながら例えば図示しない熱風炉に送り込み、
半田クリームを溶融することによりリードピン４の先端
部とフットプリント６との間に理想的な溶融半田による
フィレット７が形成される。FIG. 4 is a sectional view of a main part for describing a method of soldering a conventional surface mount type PGA package. In the figure,
Reference numeral 5 denotes a printed wiring board held horizontally, and 6 denotes a footprint formed on the printed wiring board 5 so as to be connected to the lead pins 4. Solder cream (not shown) is soldered on the surface of this footprint. Print it out first. The lead pins 4 of the semiconductor device 1 are respectively positioned and arranged on the footprints 6 to be soldered, and are sent to, for example, a hot stove (not shown) while maintaining this state.
By melting the solder cream, a fillet 7 made of ideal molten solder is formed between the tip of the lead pin 4 and the footprint 6.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

前述の方法によれば、水平に保持されたプリント配線
板５の上面側のフットプリント６にそれぞれ半田付けす
べき半導体装置１のリードピン４を位置決め配置した場
合の半田付けは容易に実施できるが、プリント配線板５
の下面側にも半導体装置１を位置決めの上スプリング等
にて保持して同時に半田付けを行う場合は、下面側のリ
ードピン４の先端は上向きにフットプリント６に位置決
めされているため半田クリームが溶融するとリードピン
４の表面に沿って流れ落ち、フィレット８に示すように
溶融半田はパッケージ側に寄ってしまい、フットプリン
ト６とリードピン４との回路接続が確実に出来ない欠点
がある。According to the above-described method, soldering can be easily performed when the lead pins 4 of the semiconductor device 1 to be soldered are respectively positioned and arranged on the footprints 6 on the upper surface side of the printed wiring board 5 held horizontally. Printed wiring board 5
When the semiconductor device 1 is also held on the lower surface side of the semiconductor device 1 by an upper spring or the like and soldering is performed at the same time, the tip of the lead pin 4 on the lower surface side is positioned upward on the footprint 6 so that the solder cream is melted. Then, the solder flows down along the surface of the lead pin 4, and the molten solder moves toward the package side as shown in the fillet 8, so that there is a disadvantage that the circuit connection between the footprint 6 and the lead pin 4 cannot be made reliably.

本発明は上記従来の欠点に鑑みてなされたもので、リ
ードピンの先端を上向きに保持して半田付けを行う場合
の溶融半田の垂れ下がりを防止する確実な半田付け方法
の提供を目的とする。The present invention has been made in view of the above-mentioned conventional drawbacks, and has as its object to provide a reliable soldering method for preventing dripping of molten solder when soldering is performed while holding the tips of lead pins upward.

〔課題を解決するための手段〕[Means for solving the problem]

第１図は本発明の半導体装置のリードピンの要部拡大
図であって、第１図（ａ）はリング状の溝を有する型、
第１図（ｂ）は螺旋状の溝を有する型を示し、第２図は
本発明の半導体装置の半田付け方法を説明するための要
部断面図を示す。プリント配線板５の上下両面のフット
プリント６に半田クリームを付着した後、プリント配線
板５を略水平に保持し、少なくとも下面側のフットプリ
ント６に実装するPGA型パッケージ構造の半導体装置１
は、リードピン４の先端部に形成されたリング状の溝
９、または螺旋状の溝10でなる半田垂れ下がり防止手段
を前記フットプリント６に下から当接した状態で前記半
導体装置１を上下両面に同一工程で半田付けするように
構成する。FIG. 1 is an enlarged view of a main part of a lead pin of a semiconductor device of the present invention. FIG. 1 (a) is a mold having a ring-shaped groove,
FIG. 1B shows a mold having a spiral groove, and FIG. 2 is a cross-sectional view of a main part for describing a method of soldering a semiconductor device according to the present invention. After applying solder cream to the footprints 6 on both the upper and lower surfaces of the printed wiring board 5, the printed wiring board 5 is held substantially horizontally, and is mounted on at least the footprint 6 on the lower surface side.
The semiconductor device 1 is placed on both the upper and lower surfaces in a state where the solder drip prevention means formed of a ring-shaped groove 9 or a spiral groove 10 formed at the tip of the lead pin 4 is in contact with the footprint 6 from below. It is configured to be soldered in the same process.

〔作 用〕 表面実装型のプリント配線板５の両面のフットプリン
ト６に先ず半田クリームを印刷し、次にプリント配線板
５の下面を反転させて上面側に水平に保持し、半田付け
すべきリードピン４の先端部をそれぞれ対応するフット
プリント６に位置決めした後、治具を用いてスプリング
等にて各半導体装置１をプリント配線板５に押圧保持
し、次に上下を元の位置に反転させた後、上面側に半田
付けすべき半導体装置１のリードピン４をそれぞれ対応
するフットプリント６に位置決めした状態で熱風炉に送
り込み、半田クリームを溶融すると、上面側の半田付け
は従来通りであり、下面側の半田付けは溶融半田がリン
グ状の溝９、または螺旋状の溝10の各表面張力に吸引さ
れて流れ落ちることがないため、下面側のリードピンの
先端が上向きになっていてもリードピン４の先端部とフ
ットプリント６との間に理想的な溶融半田によるフィレ
ット11が形成される。[Operation] First, solder cream is printed on the footprints 6 on both sides of the surface mount type printed wiring board 5, and then the lower surface of the printed wiring board 5 is turned upside down and held horizontally on the upper surface side to be soldered. After positioning the end portions of the lead pins 4 at the corresponding footprints 6, each semiconductor device 1 is pressed and held on the printed wiring board 5 with a jig using a spring or the like, and then turned upside down to the original position. After that, when the lead pins 4 of the semiconductor device 1 to be soldered on the upper surface are positioned in the corresponding footprints 6 and sent to a hot-blast furnace to melt the solder cream, the soldering on the upper surface is the same as the conventional method. In the soldering on the lower surface side, the molten solder is sucked by the surface tension of the ring-shaped groove 9 or the spiral groove 10 and does not flow down, so that the tip of the lead pin on the lower surface faces upward. In this case, a fillet 11 made of ideal molten solder is formed between the tip of the lead pin 4 and the footprint 6.

〔実施例〕〔Example〕

以下本発明の実施例を図面によって詳述する。なお、
構成、動作の説明を理解し易くするために全図を通じて
同一部分には同一符号を付してその重複説明を省略す
る。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition,
To facilitate understanding of the description of the configuration and operation, the same portions are denoted by the same reference numerals throughout the drawings, and redundant description will be omitted.

第１図は本発明の半導体装置のリードピンの要部拡大
図であって、第１図（ａ）はリング状溝を有する型、第
１図（ｂ）は螺旋状溝を有する型を示す。両図におい
て、９はリードピン４の先端部にリング状に削設した
溝、10は螺旋状の溝を示す。これらの溝は溶融半田を表
面張力により吸引するためのものであり、理想的なフィ
レット11が形成される位置に設ける。溝の深さはリード
ピン４の半径の1/3程度が好ましく、溝の断面形状は角
溝が好ましい。FIG. 1 is an enlarged view of a main part of a lead pin of a semiconductor device according to the present invention. FIG. 1 (a) shows a mold having a ring-shaped groove, and FIG. 1 (b) shows a mold having a spiral groove. In both figures, reference numeral 9 denotes a groove formed in a ring shape at the tip of the lead pin 4, and reference numeral 10 denotes a spiral groove. These grooves are for sucking the molten solder by surface tension, and are provided at positions where ideal fillets 11 are formed. The depth of the groove is preferably about 1/3 of the radius of the lead pin 4, and the cross-sectional shape of the groove is preferably a square groove.

第２図は本発明の半導体装置の半田付け方法を説明す
るための要部断面図を示す。以下第１図を参照しながら
第２図の説明を行う。FIG. 2 is a sectional view of a main part for describing a method of soldering a semiconductor device according to the present invention. FIG. 2 will be described below with reference to FIG.

第２図のプリント配線板５の上面側に位置決めされた
半導体装置１の作用については従来例で述べた通りであ
るから説明を省略する。下面側の半導体装置１の位置決
めはプリント配線板５を上下反転した状態で行い、図示
しない半田クリームを印刷したフットプリント６にそれ
ぞれ半田付けすべきリードピン４を位置決めし、治具を
用いてスプリング等にて各半導体装置１をプリント配線
板５に押圧保持し、元の状態にプリント配線板５を反転
させた後、上面側の半導体装置を同様の手順にて位置決
めした状態で熱風炉に送り込み、半田クリームを溶融す
ると、上面側の半田付けは従来通りであり、下面側の半
田付けは溶融半田がリング状の溝９、または螺旋状の溝
10の各表面張力に吸引されて流れ落ちることがないた
め、リードピン４の先端部とフットプリント６との間に
理想的な溶融半田によるフィレット11が形成される。The operation of the semiconductor device 1 positioned on the upper surface side of the printed wiring board 5 in FIG. 2 is the same as that described in the conventional example, and therefore the description is omitted. The positioning of the semiconductor device 1 on the lower surface side is performed with the printed wiring board 5 turned upside down, and the lead pins 4 to be soldered are respectively positioned on the footprints 6 on which solder cream (not shown) is printed. After pressing and holding each semiconductor device 1 on the printed wiring board 5 and inverting the printed wiring board 5 to the original state, the semiconductor device 1 on the upper surface side is sent to a hot blast stove while being positioned in the same procedure, When the solder cream is melted, the soldering on the upper surface side is the same as the conventional soldering method, and the soldering on the lower surface side is performed by using the ring-shaped groove 9 or the spiral groove.
Since each of the surface tensions of the lead pins 10 is not sucked and flows down, an ideal fillet 11 made of molten solder is formed between the tip of the lead pin 4 and the footprint 6.

上面側の半導体装置１のリードピン４には溝を設けな
い図にて説明したが、溝を設けたリードピン４を用いた
場合はプリント配線板５の上面側の半田付けは、リード
ピン４に対する溶融半田の過度の上昇を抑えて良好な結
果が得られる。Although the lead pins 4 of the semiconductor device 1 on the upper surface side have been described with reference to the drawings in which grooves are not provided, when the lead pins 4 having grooves are used, soldering on the upper surface side of the printed wiring board 5 is performed by melting solder to the lead pins 4. And an excellent result can be obtained by suppressing an excessive rise of

〔発明の効果〕〔The invention's effect〕

以上の説明から明らかなように本発明によれば、プリ
ント配線板の上下両面に半導体装置を同時実装する際
に、とくに下面側のリードピンの先端部には予め、半田
垂れ下がり防止手段が設けられていることにより、溶融
半田が半田垂れ下がり防止手段の表面張力に吸引されて
下方に流れ落ちることはないため、下面側のリードピン
の先端が上向きになっていてもリードピンとプリント配
線板のフットプリントと確実な半田接続が可能となり、
かつ製造工程の短縮ができる効果がある。As is apparent from the above description, according to the present invention, when the semiconductor devices are simultaneously mounted on the upper and lower surfaces of the printed wiring board, especially at the tips of the lead pins on the lower surface side, a solder droop preventing means is provided. Since the molten solder is not sucked down by the surface tension of the solder droop preventing means and does not flow downward, even if the tip of the lead pin on the lower surface side is directed upward, the footprint of the lead pin and the printed wiring board can be ensured. Solder connection becomes possible,
In addition, there is an effect that the manufacturing process can be shortened.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明の半導体装置のリードピンの要部拡大
図、 第２図は本発明の半導体装置の半田付け方法を説明する
ための要部断面図、 第３図は従来のPGA型パッケージ構造の半導体装置の正
面概略図、 第４図は従来の表面実装型のPGAパッケージの半田付け
方法を説明するための要部断面図を示す。 第１図と第２図において、１は半導体装置、４はリード
ピン、５はプリント配線板、６はフットプリント、９は
リング状の溝、10は螺旋状の溝をそれぞれ示す。FIG. 1 is an enlarged view of a main part of a lead pin of a semiconductor device of the present invention, FIG. 2 is a cross-sectional view of a main part for explaining a method of soldering a semiconductor device of the present invention, and FIG. 3 is a conventional PGA type package structure. FIG. 4 is a cross-sectional view of a principal part for describing a method of soldering a conventional surface mount type PGA package. 1 and 2, reference numeral 1 denotes a semiconductor device, 4 denotes a lead pin, 5 denotes a printed wiring board, 6 denotes a footprint, 9 denotes a ring-shaped groove, and 10 denotes a spiral groove.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】上下両面に半導体装置を実装するプリント
配線板のフットプリントに半田を付着した後、該プリン
ト配線板を略水平に保持し、かつ下面側の該フットプリ
ントに実装する半導体装置のリードピンを、その先端部
直下に予め、半田垂れ下がり防止手段を設けて前記フッ
トプリントに下から当接した状態で上下面に同一工程で
半田付けすることを特徴とするプリント配線板へのリー
ドピンの半田付け方法。1. A method of mounting a semiconductor device on a printed circuit board on which the semiconductor device is mounted on both upper and lower surfaces, after solder is attached to the printed circuit board, the printed circuit board is held substantially horizontally and the lower surface side is mounted on the footprint. Soldering the lead pins to the printed wiring board in the same step by providing solder dripping prevention means immediately below the front end thereof and abutting the footprint from below in the same step. Attachment method.
JP1272308A 1989-10-18 1989-10-18 Soldering lead pins to printed wiring board Expired - Fee Related JP2822496B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1272308A JP2822496B2 (en) 1989-10-18 1989-10-18 Soldering lead pins to printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1272308A JP2822496B2 (en) 1989-10-18 1989-10-18 Soldering lead pins to printed wiring board

Publications (2)

Publication Number Publication Date
JPH03133166A JPH03133166A (en) 1991-06-06
JP2822496B2 true JP2822496B2 (en) 1998-11-11

Family

ID=17512069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1272308A Expired - Fee Related JP2822496B2 (en) 1989-10-18 1989-10-18 Soldering lead pins to printed wiring board

Country Status (1)

Country Link
JP (1) JP2822496B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100389113B1 (en) * 2001-06-21 2003-06-25 주식회사 태화인서트 Device Adhering Method for FPCB
JP4799296B2 (en) * 2006-06-30 2011-10-26 株式会社東芝 Electronics

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4661887A (en) * 1985-10-31 1987-04-28 Motorola, Inc. Surface mountable integrated circuit packages having solder bearing leads
JPS62249465A (en) * 1986-04-23 1987-10-30 Hitachi Ltd Semiconductor device
JPS6471159A (en) * 1987-09-10 1989-03-16 Fujitsu Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH03133166A (en) 1991-06-06

Similar Documents

Publication Publication Date Title
KR910007103B1 (en) Cast solder leads for leadless semiconductor circuits
US4827611A (en) Compliant S-leads for chip carriers
US7675144B2 (en) Method of making wireless semiconductor device, and leadframe used therefor
US4582975A (en) Circuit chip
JPH04229693A (en) Surface mounting method for electronic device
US4645114A (en) Shaped solder pad for surface mounting electronic devices and a surface mounting position incorporating such shaped pads
US4506139A (en) Circuit chip
JP2822496B2 (en) Soldering lead pins to printed wiring board
JP2008171992A (en) Mounting method of semiconductor component
JP3709036B2 (en) Mounting method for weak heat-resistant electronic components
JPS61102089A (en) Mount structure of flat package ic
JPH0621110A (en) Assembling jig for semiconductor chip
JPS629722Y2 (en)
JPH0738225A (en) Semiconductor device and its manufacturing method
JPH01186269A (en) Soldering device
JP2571873B2 (en) Method of soldering semiconductor package to printed wiring board
JP3214009B2 (en) Semiconductor device mounting substrate and method
JP2751897B2 (en) Ball grid array mounting structure and mounting method
JP2000151091A (en) Method for mounting electric components
JP3063587B2 (en) Electronic component and method of manufacturing electronic component
JPS63194342A (en) Method of packaging semiconductor chip
JP2681702B2 (en) Mounting method for surface mount components
JPS6262533A (en) High-density mounting method for semiconductor element
JPH04268739A (en) Manufacture of semiconductor device
JPS5824940B2 (en) hand out hand

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees