JPH03133166A - Simultaneous soldering method of both surfaces of surface mounting type printed wiring board - Google Patents
Simultaneous soldering method of both surfaces of surface mounting type printed wiring boardInfo
- Publication number
- JPH03133166A JPH03133166A JP27230889A JP27230889A JPH03133166A JP H03133166 A JPH03133166 A JP H03133166A JP 27230889 A JP27230889 A JP 27230889A JP 27230889 A JP27230889 A JP 27230889A JP H03133166 A JPH03133166 A JP H03133166A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- soldering
- lead pin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005476 soldering Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 229910000679 solder Inorganic materials 0.000 abstract description 25
- 239000006071 cream Substances 0.000 abstract description 9
- 230000000717 retained effect Effects 0.000 abstract 1
- 238000003491 array Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3415—Surface mounted components on both sides of the substrate or combined with lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
水平に保持した表面実装型プリント配線板の上下両面に
ピン・グリッド・アレイ型半導体装置を同時に半田付は
実装する方法に関し、
リードピンの先端を上向きに保持して半田付けを行う場
合の溶融半田の垂れ下がりを防止する確実な半田付は方
法の提供を目的とし、
ピン・グリッド・アレイ型パッケージ構造の半導体装置
に植設されたリードピンの各先端部にリング状の溝、ま
たは螺旋状の溝を設け、水平に保持した表面実装型のプ
リント配線板の上下両面に形成された複数のフットプリ
ントにそれぞれ前記リードピンの各先端部を位置決め保
持した状態で上下両面同時に半田付けを行うように構成
する。[Detailed Description of the Invention] [Summary] A method for simultaneously soldering and mounting pin grid array type semiconductor devices on both upper and lower surfaces of a surface mount type printed wiring board held horizontally, in which the tips of lead pins are held upward. The purpose of the present invention is to provide a method for reliable soldering that prevents the molten solder from dripping when soldering is performed using a ring. A surface mount type printed wiring board is provided with a shaped groove or a spiral groove, and each tip of the lead pin is positioned and held in a plurality of footprints formed on both the upper and lower surfaces of a surface mount printed wiring board held horizontally. The configuration is such that soldering is performed at the same time.
本発明は、水平に保持した表面実装型プリント配線板の
上下両面にピン・グリッド・アレイ（ＰｉｎＧｒｉｄ
Ａｒｒａｙ ；以下ＰＧＡと略称する）型半導体装置を
同時に半田付は実装する方法に関する。The present invention provides pin grid arrays (PinGrid arrays) on both upper and lower surfaces of a surface-mounted printed wiring board held horizontally.
Soldering relates to a method for simultaneously mounting Array (hereinafter abbreviated as PGA) type semiconductor devices.
第３図は従来のＰＧＡ型パッケージ構造の半導体装置の
正面概略図を示す。図において、１はＰＧＡ型パッケー
ジ構造の半導体装置であって、セラミックまたは樹脂モ
ールドで形成されるパッケージ２と、放熱フィン（発熱
量の少ない半導体の場合は付属しない）３と、丸棒状の
導電性部材をパンケージ２の裏面に格子状に植設して形
成された複数のリードピン４とから構成されている。FIG. 3 shows a schematic front view of a semiconductor device having a conventional PGA type package structure. In the figure, 1 is a semiconductor device with a PGA type package structure, which includes a package 2 made of ceramic or resin mold, a radiation fin (not included in the case of a semiconductor with a low heat generation) 3, and a round bar-shaped conductive fin. It is composed of a plurality of lead pins 4 formed by planting members in a grid pattern on the back surface of the pan cage 2.
第４図は従来の表面実装型ＰＧＡパッケージの半田付は
方法を説明するための要部断面図を示す。FIG. 4 is a cross-sectional view of a main part for explaining a conventional soldering method for a surface-mounted PGA package.
図において、５は水平に保持されたプリント配線板、６
はリードピン４に接続されるべくプリント配線板５上に
形成されたフットプリントであって、このフットプリン
ト６の表面には図示しない半田クリームを半田付けに先
立って印刷しておく。半導体装置ｌのリードピン４をそ
れぞれ半田付けすべきフットプリント６に位置決めして
配置し、この状態を保持しながら例えば図示しない熱風
炉に送り込み、半田クリームを溶融することによりリー
ドピン４の先端部とフットプリント６との間に理想的な
溶融半田によるフィレット７が形成される。In the figure, 5 is a printed wiring board held horizontally, 6
is a footprint formed on the printed wiring board 5 to be connected to the lead pin 4, and a solder cream (not shown) is printed on the surface of the footprint 6 prior to soldering. The lead pins 4 of the semiconductor device 1 are positioned and placed on the footprint 6 to be soldered, and while this state is maintained, the tips of the lead pins 4 and the foot are sent, for example, to a hot air oven (not shown) to melt the solder cream. An ideal fillet 7 is formed between the print 6 and the molten solder.
〔発明が解決しようとする課題〕
前述の方法によれば、水平に保持されたプリント配線板
５の上面側のフットプリント６にそれぞれ半田付けすべ
き半導体装置１のリードピン４を位置決め配置した場合
の半田付けは容易に実施できるが、プリント配線板５の
下面側にも半導体装１１を位置決めの上スプリング等に
て保持して同時に半田付けを行う場合は、下面側のリー
ドピン４の先端は上向きにフットプリント６に位置決め
されているため半田クリームが溶融するとリードピン４
の表面に沿って流れ落ち、フィレット８に示すように溶
融半田はパッケージ側に寄ってしまい、フットプリント
６とリードピン４との回路接続が確実に出来ない欠点が
ある。[Problems to be Solved by the Invention] According to the above-described method, when the lead pins 4 of the semiconductor device 1 to be soldered are positioned on the footprints 6 on the upper surface side of the printed wiring board 5 held horizontally, Soldering can be carried out easily, but if the semiconductor device 11 is also held on the bottom side of the printed wiring board 5 by an upper spring for positioning and soldering is carried out at the same time, the tips of the lead pins 4 on the bottom side should face upward. Because it is positioned at footprint 6, when the solder cream melts, lead pin 4
The molten solder flows down along the surface of the lead pin 4, and as shown in the fillet 8, the molten solder tends toward the package side, which has the drawback that the circuit connection between the footprint 6 and the lead pin 4 cannot be reliably established.
本発明は上記従来の欠点に鑑みてなされたもので、リー
ドピンの先端を上向きに保持して半田付けを行う場合の
溶融半田の垂れ下がりを防止する確実な半田付は方法の
提供を目的とする。The present invention has been made in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a reliable soldering method that prevents molten solder from dripping when soldering is performed by holding the tip of a lead pin upward.
第１図は本発明の半導体装置のリードピンの要部拡大図
であって、第１図（ａ）はリング状の溝を有する型、第
１図（１））は螺旋状の溝を有する型を示し、第２図は
本発明の半導体装置の半田付は方法を説明するための要
部断面図を示す。ＰＧＡ型パッケージ構造の半導体装置
１に植設されたリードピン４の各先端部にリング状の溝
９、または螺旋状の溝１０を設け、水平に保持した表面
実装型のプリント配線板５の上下両面に形成された複数
のフットプリント６にそれぞれ前記リードピン４の各先
端部を位置決め保持した状態で上下両面同時に半田付け
を行うように構成する。FIG. 1 is an enlarged view of the main part of a lead pin of a semiconductor device according to the present invention, in which FIG. 1(a) is a type having a ring-shaped groove, and FIG. 1(1)) is a type having a spiral groove. FIG. 2 is a cross-sectional view of a main part for explaining the soldering method of a semiconductor device according to the present invention. A ring-shaped groove 9 or a spiral groove 10 is provided at each tip of a lead pin 4 implanted in a semiconductor device 1 having a PGA type package structure, and both upper and lower surfaces of a surface-mounted printed wiring board 5 held horizontally are provided. The configuration is such that soldering is performed simultaneously on both the upper and lower surfaces while positioning and holding the respective tips of the lead pins 4 on a plurality of footprints 6 formed in the .
表面実装型のプリント配線板５の両面のフットプリント
６に先ず半田クリームを印刷し、次にプリント配線板５
の下面を反転させて上面側に水平に保持し、半田付けす
べきリードピン４の先端部をそれぞれ対応するフットプ
リント６に位置決めした後、治具を用いてスプリング等
にて各半導体装置１をプリント配線板５に押圧保持し、
次に上下を元の位置に反転させた後、上面側に半田付け
すべき半導体装置１のリードピン４をそれぞれ対応する
フットプリント６に位置決めした状態で熱風炉に送り込
み、半田クリームを溶融すると、上面側の半田付けは従
来通りであり、下面側の半田付けは溶融半田がリング状
の溝９、または螺旋状の溝１０の各表面張力に吸引され
て流れ落ちることがないため、リードピン４の先端部と
フットプリント６との間に理想的な溶融半田によるフィ
レット１１が形成される。First, solder cream is printed on the footprints 6 on both sides of the surface-mounted printed wiring board 5, and then the printed wiring board 5 is
After inverting the bottom surface and holding it horizontally on the top side, and positioning the tips of the lead pins 4 to be soldered to the corresponding footprints 6, print each semiconductor device 1 using a jig with a spring or the like. Press and hold on the wiring board 5,
Next, after inverting the top and bottom to their original positions, the lead pins 4 of the semiconductor device 1 to be soldered on the top side are placed in the corresponding footprints 6 and sent into a hot air oven, and when the solder cream is melted, the top The soldering on the side is the same as before, and the soldering on the bottom side prevents the molten solder from flowing down because it is attracted by the surface tension of the ring-shaped groove 9 or the spiral groove 10. An ideal fillet 11 is formed between the molten solder and the footprint 6.
以下本発明の実施例を図面によって詳述する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
なお、構成、動作の説明を理解し易（するために全図を
通じて同一部分には同一符号を付してその重複説明を省
略する。In order to make the explanation of the configuration and operation easier to understand, the same parts are given the same reference numerals throughout the drawings and their repeated explanation will be omitted.
第１図は本発明の半導体装置のリードピンの要部拡大図
であって、第１図（ａ）はリング状渚を有する型、第１
図（ｂ）は螺旋状溝を有する型を示す。両図において、
９はリードピン４の先端部にリング状に削設した溝、１
０は螺旋状の溝を示す。これらの溝は溶融半田を表面張
力により吸引するためのものであり、理想的なフィレッ
ト１１が形成される位置に設ける。溝の深゛さはリード
ピン４の半径の１！３程度が好ましく、溝の断面形状は
角溝が好ましい。FIG. 1 is an enlarged view of the main part of the lead pin of the semiconductor device of the present invention, and FIG.
Figure (b) shows a mold with a spiral groove. In both figures,
9 is a ring-shaped groove cut into the tip of the lead pin 4;
0 indicates a spiral groove. These grooves are for attracting molten solder by surface tension, and are provided at positions where ideal fillets 11 are formed. The depth of the groove is preferably about 1:3 of the radius of the lead pin 4, and the cross-sectional shape of the groove is preferably a rectangular groove.
第２図は本発明の半導体装置の半田付は方法を説明する
ための要部断面図を示す。以下第１図を参照しながら第
２図の説明を行う。FIG. 2 shows a sectional view of a main part for explaining the method of soldering a semiconductor device according to the present invention. FIG. 2 will be explained below with reference to FIG. 1.
第２図のプリント配線板５の上面側に位置決めされた半
導体装置１の作用については従来例で述べた通りである
から説明を省略する。下面側の半導体装置１の位置決め
はプリント配線板５を上下反転した状態で行い、図示し
ない半田クリームを印刷したフットプリント６にそれぞ
れ半田付けすべきリードピン４を位置決めし、治具を用
いてスプリング等にて各半導体装置１をプリント配線板
５に押圧保持し、元の状態にプリント配線Ｆｉ、５を反
転させた後、上面側の半導体装置を同様の手順にて位置
決めした状態で熱風炉に送り込み、半田クリームを溶融
すると、上面側の半田付けは従来通りであり、下面側の
半田付けは溶融半田がリング状の溝９、または螺旋状の
溝１０の各表面張力に吸引されて流れ落ちることがない
ため、リードピン４の先端部とフットプリント６との間
に理想的な溶融半田によるフィレット１１が形成される
。The operation of the semiconductor device 1 positioned on the upper surface side of the printed wiring board 5 in FIG. 2 is the same as that described in the conventional example, so a description thereof will be omitted. The positioning of the semiconductor device 1 on the lower side is performed with the printed wiring board 5 upside down, and the lead pins 4 to be soldered are positioned on the respective footprints 6 printed with solder cream (not shown), and springs etc. are positioned using a jig. After pressing and holding each semiconductor device 1 against the printed wiring board 5 and inverting the printed wiring Fi, 5 to its original state, the semiconductor device on the top side is positioned in the same manner and sent into a hot air oven. , when the solder cream is melted, the soldering on the top side is the same as before, and the soldering on the bottom side is such that the molten solder is attracted to the surface tension of the ring-shaped groove 9 or the spiral groove 10 and flows down. Therefore, an ideal fillet 11 of molten solder is formed between the tip of the lead pin 4 and the footprint 6.
上面側の半導体装置１のリードピン４には溝を設けない
図にて説明したが、溝を設けたリードピン４を用いた場
合はプリント配線板５の上面側の半田付けは、リードピ
ン４に対する溶融半田の過度の上昇を抑えて良好な結果
が得られる。The explanation has been made using the figure in which the lead pins 4 of the semiconductor device 1 on the top surface side are not provided with grooves, but when the lead pins 4 with grooves are used, the soldering on the top surface side of the printed wiring board 5 is performed using molten solder on the lead pins 4. Good results can be obtained by suppressing excessive rise in
以上の説明から明らかなように本発明によれば、プリン
ト配線板のフットプリントと確実な半田接続が可能とな
り、かつ製造工程の短縮ができる効果がある。As is clear from the above description, according to the present invention, it is possible to make a reliable solder connection to the footprint of a printed wiring board, and the manufacturing process can be shortened.
第１図は本発明の半導体装置のリードピンの要部拡大図
、
第２図は本発明の半導体装置の半田付は方法を説明する
ための要部断面図、
第３図は従来のＰＧＡ型パッケージ構造の半導体装置の
正面概略図、
第４図は従来の表面実装型のＰＧＡパッケージの半田付
は方法を説明するための要部断面図を示す。
（Ｑ）リンｈ沃の工Ｕする９！ （１））螺
δ定状の・二急８損騎を際後略の神本殻１のリードピン
ψ要部η江大図第１図
第１図と第２図において、１は半導体装置、４はリード
ピン、５はプリント配線板、６はフットプリント、９は
リング状の溝、１０は螺旋状の溝をそれぞれ示す。
１部材面図
第２図Fig. 1 is an enlarged view of the main part of the lead pin of the semiconductor device of the present invention, Fig. 2 is a sectional view of the main part for explaining the soldering method of the semiconductor device of the present invention, and Fig. 3 is a conventional PGA type package. FIG. 4 is a schematic front view of a semiconductor device having the structure, and FIG. 4 is a sectional view of a main part for explaining a conventional soldering method for a surface-mounted PGA package. (Q) Rin's work is 9! (1)) The lead pin ψ of the main shell 1 of the main shell 1 with a spiral δ shape and two sudden 8 losses. 5 represents a lead pin, 5 represents a printed wiring board, 6 represents a footprint, 9 represents a ring-shaped groove, and 10 represents a spiral groove. Figure 2: 1-piece surface diagram
Claims (1)
（１）に植設されたリードピン（４）の各先端部にリン
グ状の溝（９）、または螺旋状の溝（１０）を設け、水
平に保持した表面実装型のプリント配線板（５）の上下
両面に形成された複数のフットプリント（６）にそれぞ
れ前記リードピン（４）の各先端部を位置決め保持した
状態で上下両面同時に半田付けを行うことを特徴とする
表面実装型プリント配線板の両面同時半田付け方法。A ring-shaped groove (9) or a spiral groove (10) is provided at each tip of a lead pin (4) implanted in a semiconductor device (1) having a pin grid array type package structure to hold it horizontally. Soldering is performed simultaneously on both the upper and lower surfaces of the surface-mounted printed wiring board (5), with each tip of the lead pin (4) positioned and held on a plurality of footprints (6) formed on both the upper and lower surfaces of the surface-mounted printed wiring board (5). A method for simultaneously soldering both sides of a surface-mounted printed wiring board, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1272308A JP2822496B2 (en) | 1989-10-18 | 1989-10-18 | Soldering lead pins to printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1272308A JP2822496B2 (en) | 1989-10-18 | 1989-10-18 | Soldering lead pins to printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03133166A true JPH03133166A (en) | 1991-06-06 |
| JP2822496B2 JP2822496B2 (en) | 1998-11-11 |
Family
ID=17512069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1272308A Expired - Fee Related JP2822496B2 (en) | 1989-10-18 | 1989-10-18 | Soldering lead pins to printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2822496B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100389113B1 (en) * | 2001-06-21 | 2003-06-25 | 주식회사 태화인서트 | Device Adhering Method for FPCB |
| JP2008010768A (en) * | 2006-06-30 | 2008-01-17 | Toshiba Corp | Electronic device and mounting structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62249465A (en) * | 1986-04-23 | 1987-10-30 | Hitachi Ltd | Semiconductor device |
| JPS63501254A (en) * | 1985-10-31 | 1988-05-12 | モトロ−ラ・インコ−ポレ−テッド | Surface mountable integrated circuit package with solder retention leads |
| JPS6471159A (en) * | 1987-09-10 | 1989-03-16 | Fujitsu Ltd | Semiconductor device |
-
1989
- 1989-10-18 JP JP1272308A patent/JP2822496B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63501254A (en) * | 1985-10-31 | 1988-05-12 | モトロ−ラ・インコ−ポレ−テッド | Surface mountable integrated circuit package with solder retention leads |
| JPS62249465A (en) * | 1986-04-23 | 1987-10-30 | Hitachi Ltd | Semiconductor device |
| JPS6471159A (en) * | 1987-09-10 | 1989-03-16 | Fujitsu Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100389113B1 (en) * | 2001-06-21 | 2003-06-25 | 주식회사 태화인서트 | Device Adhering Method for FPCB |
| JP2008010768A (en) * | 2006-06-30 | 2008-01-17 | Toshiba Corp | Electronic device and mounting structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2822496B2 (en) | 1998-11-11 |
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