JP2821123B2 - Microcomputer - Google Patents

Description

The present invention relates to a bus connection control circuit that controls connection of data input / output between an internal data bus such as a microcomputer and an external data bus of an external device. [Prior Art] FIG. 2 is a circuit diagram showing a conventional bus connection control circuit provided in a microcomputer having an internal data bus having a bus width of 8 bits. In the figure, DB0 to DB7 are data buses, and 1 is an input / output unit, which has eight input / output terminals P0 to P7 corresponding to the 8-bit data buses DB0 to DB7. Each of these data buses DB0 to DB7, input / output terminal P0
To P7, as shown in FIG.
To T7 and input / output control circuits CL0 to CL7 are provided in series. A mode switching signal A is applied to the transmission gates T0 to T7, and conduction / non-conduction is controlled by the mode switching signal A. When the mode switching signal A is "1", conduction is performed, and when the mode switching signal A is "0", non-conduction is performed. Become. Also, the input / output control circuit CL
The mode switching signal A is also applied to 0 to CL7. Normal input / output control is performed when the mode switching signal A is "0". When the mode switching signal A is "1", a data bus such as a memory of an external device is used. Connection mode. In such a configuration, the microcomputer has 8
By accessing the memory of an external device with a bus width of bits,
When reading or writing, the mode switching signal A of "1" is sent to the transmission gates T0 to T7 to make the transmission gates T0 to T7 conductive. As a result, the data buses DB0 to DB7 and the input / output terminals P0 to P7 are connected via the input / output control circuits CL0 to CL7. In such a state, the read / write is controlled by the input / output control circuits CL0 to CL7, so that the read / write with the memory of the external device is performed. Normally, by setting the mode switching signal A to “0”, the internal data buses DB0 to DB7 and the input / output control circuits CL0 to CL7 are set.
The input / output section 1 is shut off, and the input / output section 1 is used as a normal input / output section (that is, a desired signal other than data to be transferred between the internal and external data buses). FIG. 3 is a circuit diagram showing a bus connection control circuit provided in a microcomputer having an internal data bus of 16 bits. In the figure, DB0 to DB15 are 16-bit data buses, P0 to P15 are input / output terminals corresponding to the 16-bit data buses DB0 to DB15, and T0 to T15 and CL0 to CL15 are data buses DB0 to DB15.
DB15, transmission gate and input / output control circuit provided in series between input / output terminals P0 to P15.
It is the same as the bus connection control circuit of FIG. 2 except that it is 16 bits. [Problems to be Solved by the Invention] As described above, the conventional bus connection control circuit has input / output terminals in accordance with the bus width of the internal data bus. However, when the bus width of the internal data bus is larger than the bus width of an external data bus such as a memory of an external device,
The bus widths of the two do not match, and the simple connection as shown in FIGS. 2 and 3 is very inconvenient in application. For example, if the bus width of each of the internal data bus and the external data bus is 16
In the case of 8 bits, there is a problem that only 8-bit data of the internal data bus can be connected to the external data bus. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a microcomputer which can easily control connection of an external data bus having a bus width different from that of an internal data bus. [Means for Solving the Problems] A microcomputer according to the present invention includes n (even number of n ≧ 2) input / output terminals connectable to an external data bus, and the n input / output terminals are: It consists of k (= n / 2) lower input / output terminals and k upper input / output terminals, and k (=
an n-bit internal data bus consisting of an (n / 2) -bit lower internal data bus and a k-bit upper internal data bus;
K first transmission gates provided between each of the k lower input / output terminals and each bit of the k-bit lower internal data bus; each of the k upper input / output terminals and the k bit K second transmission gates provided between each bit of the high-order internal data bus, and k second transmission gates provided between each of the k low-order input / output terminals and each bit of the k-bit high-order internal data bus K third transmission gates, first control means for controlling conduction and non-conduction of the k second transmission gates based on an external control signal, and an external control signal different from the external control signal. Based on a control signal, one of the k first and third transmission gates is turned on, and the other is turned on. Second input / output terminals, wherein the input / output terminals are used as input / output terminals for desired signals other than data to be transmitted / received between the internal and external data buses when not connected to the internal data bus. It is possible. [Operation] In the present invention, under the first and second control means,
By conducting / non-conducting control of each of the k first to third transmission gates, connection of the n-bit input / output terminal to the n-bit internal data bus, k lower-order input / output terminals and k bit , And only the connection between the k lower input / output terminals and the k-bit upper internal data bus. FIG. 1 is a circuit diagram showing a microcomputer having a bus connection control circuit having a bus width of 16 bits of an internal data bus according to an embodiment of the present invention. In the figure, DB
Since 0 to DB15, P0 to P15, CL0 to CL15, and signal A are the same as those in the related art, the description is omitted. Transmission gates T8 to T15 are conventional (Fig. 3)
Similarly, data buses DB8 to DB15, input / output control circuits CL8 to CL15
The transmission gates T8 to T15 are connected in series, but their conduction and non-conduction are controlled by the output signal of the NOR gate NOR1.
The NOR gate NOR1 uses an inverted signal of the mode switching signal A and an inverted signal of a data bus width selection signal B described later as input signals. On the other hand, transmission gates T0 to T7 are also
Although the data buses DB0 to DB7 and the input / output control circuits CL0 to CL7 are connected in series, the transmission gates T0 to T7 are conventionally controlled by the output signal of the NOR gate NOR3 to control the conduction and non-conduction. And different. Further, a significant difference from the conventional example is that new transmission gates TG0 to TG7 are provided in series between data buses DB8 to DB15 and input / output control circuits CL0 to CL7 as shown in FIG. The conduction / non-conduction of TG7 is controlled by the output signal of NOR gate NOR4. The NOR gate NOR3 uses the inverted signal of the mode switching signal A and the output signal of the NOR gate NOR2 as input signals.
The NOR gate NOR4 uses as input signals an inverted signal of the mode switching signal A and an inverted signal of the output signal of the NOR gate NOR2 via the inverter G. The NOR gate NOR2 uses a data bus width selection signal B and an upper / lower switching signal C described later as input signals. The data bus width selection signal B is a signal for selecting the effective bit width of the input / output unit 1. When B = "1", the data bus width selection signal B has a 16-bit width (P0 to P1).
5 are all valid), and when B = "0", the width is 8-bit (only P0 to P7 are valid). The upper / lower switching signal C is input / output unit 1
Is required when the effective bit width of the data bus is 8 bits (that is, when B = "0"). When C = "1", the data bus DB
0 to DB7 are connected to input / output terminals P0 to P7 (lower connection), and C =
When “0”, the data buses DB8 to DB15 are connected to the input / output terminals P0 to P7
(Upper connection). = Table 1 shows the definitions of mode 0 to mode 3, and Table 2 shows the signals A, B, C,.
Table 3 shows the output signals of the NOR gates NOR1 to NOR4 and the inverter G in each mode. Hereinafter, the operation of the bus connection control device for each mode will be described with reference to these tables. In the case of mode 0 When the mode switching signal A is set to “0”, the inverted signal of the mode switching signal A (= “1”) is applied to one of the inputs of the NOR gates NOR1, NOR3, and NOR4 regardless of the values of the signals B and C. ), The output signals of the NOR gates NOR1, NOR3, NOR4 are all "0", and the transmission gates T0 to T15 and TG0 to TG7 are all non-conductive. ○ In the case of mode 1 When mode switching is performed, A is set to “1” and data bus width selection signal B is set to “1”.
Therefore, the output signal of the NOR gate NOR1 becomes “1”. On the other hand, the output signal of the NOR gate NOR2 is “0” regardless of the value of the signal C because the signal B (= “1”) is one input. Therefore, the output signal of the inverter G becomes "1", and the NOR gates NOR3 and NOR3 which make the input an inverted signal (= "0").
The output signals of 4 are “1” and “0”, respectively. As a result, the transmission gates T0 to T15 become conductive, the transmission gates TG0 to TG7 become nonconductive, and the data bus DB0
To DB15 and input / output terminals P0 to P15 are connected. In the case of mode 2 When the mode switching signal A is set to “1”, the data bus width selection signal B is set to “0”, and the upper and lower selection signals C are set to “1”, the inverted signals are “0” and “ Since it becomes "1", the output signal of the NOR gate NOR1 becomes "0". On the other hand, if the signals B and C are “0”,
Since the output signal of the NOR gate NOR2 becomes "0" and the output signal of the inverter G becomes "1", the output signal of the NOR gates NOR3 and NOR4 whose one input is an inverted signal (= "0") becomes It becomes “1” and “0”. As a result, the transmission gates T0 to T7 conduct, and the transmission gates T8 to T1
5, TG0 to TG7 become nonconductive, data buses DB0 to DB7 are connected to input / output terminals P0 to P7, and data buses DB8 to DB15 are not connected to input / output unit 1. ○ Mode 3 signal When the mode switching signal A is set to “1”, the data bus width selection signal B is set to “0”, and the upper and lower selection signals C are set to “0”, the inverted signals are “0” and “ Since it becomes "1", the output signal of the NOR gate NOR1 becomes "0". On the other hand, if the signals B and C are “0”,
Since the output signal of the NOR gate NOR2 is "1" and the output signal of the inverter G is "0" because the output signal is "0", the output signals of the NOR gates NOR3 and NOR4 whose one input is an inverted signal (= "0") are "0", "1". As a result, the transmission gates TG0 to TG7 conduct, and the transmission gates T0 to
T15 becomes non-conductive, data buses DB8 to DB15 and input / output terminals
P0 to P7 are connected, and the data buses DB0 to DB7 are not connected to the input / output unit 1. As described above, the bus connection control circuit in the microcomputer of the present embodiment has modes 2 and 3 in addition to the conventional operation (mode 0 and mode 1), so that the bus width of the external data bus is 8 bits. However, by connecting the external data bus to the input / output terminals P0 to P7 and realizing modes 2 and 3 alternately by the signals A, B and C, the upper 8 bits of the internal data bus whose bus width is 16 bits DB8 to DB15, lower 8 bits
Transmission and reception with DB0 to DB7 can be performed via input / output terminals P0 to P7. As a result, connection control between the 16-bit internal data bus and the 8-bit external data bus can be easily performed. Therefore, if the bus connection control circuit of this embodiment is provided in a microcomputer having an internal data bus having a high-performance bus width of 16 bits, for example, the bus width of the data bus is reduced.
It is possible to connect to an external device such as a microcomputer other than the 16-bit configuration as well as the 8-bit configuration, so that the application range is greatly expanded. When the system is constituted by relatively inexpensive microcomputers or the like having a data bus width of 8 bits, a high-performance 16-bit structure having the bus connection control circuit shown in this embodiment is used. A microcomputer with an internal data bus can be easily introduced because the bus connection control is simple in this system, and if introduced, the performance of the system itself can be enhanced. Further, the transmission gates T0 to T1 of this embodiment
Since each of 5 and TG0 to TG7 can be formed by one transistor, they can be realized with a relatively simple circuit configuration. In addition, by making the transmission gates T8 to T15 non-conductive by the NOR gate NOR1, the input / output terminal P8
To P15 can be made independent of the internal data buses DB8 to DB15.When data is transferred only between the external data bus and the internal data buses DB0 to DB7 via the input / output terminals P0 to P7, the input / output terminal P8 To P15, the risk of erroneous data transfer between the external data bus and the internal data buses DB8 to DB15 can be completely avoided, and stable data transfer can be performed. Even if the input / output terminals P8 to P15 are used as input / output terminals for another purpose, the internal data buses DB8 to DB15 will not be affected at all. In this embodiment, the internal data bus has a bus width of 16 bits. However, the present invention can be applied even if the number of bits of the internal data bus is appropriately increased or decreased. Also, the connection bit width of the input / output terminal is 8 bits (P0 to P
7) and 16 bits (P0 to P15), but the number of bits can be appropriately increased or decreased, and the method of dividing the internal data bus is not limited to the upper and lower steps. [Effects of the Invention] As described above, according to the present invention, the conduction and non-conduction control of each of the k first to third transmission gates is performed under the first and second control means. , Connection between n-bit input / output terminals and n-bit internal data bus (first connection), connection only between k lower-order input / output terminals and k-bit lower internal data bus (second connection) ), A connection (third connection) can be made only between the k lower input / output terminals and the k-bit upper internal data bus, so that the second connection and the third connection are repeated. , Using only k lower-order input / output terminals, data can be accurately transmitted and received between an external data bus of k bits and an internal data bus of n bits. In addition, since each transmission gate of the present invention can be formed by one transistor, k first to third transistors are provided by 3k (3n / 2) transistors for an n-bit internal data bus. The transmission gate can be configured, and can be realized with a relatively simple circuit configuration. Further, the first control means makes the k second transmission gates non-conductive, so that the upper input / output terminal can be made independent of the internal data bus, and the lower external data bus and the lower internal data bus are connected. At the time of data transfer, stable data transfer can be performed by completely avoiding the danger of erroneous data transfer between the upper external data bus and the upper internal data bus. Even if the upper input / output terminal is used as an input / output terminal for another purpose, there is no adverse effect on the internal data bus.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a bus connection control circuit in a microcomputer according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing a conventional bus connection control circuit. FIG. In the figure, T0 to T15, TG0 to TG7 are transmission gates, NOR1 to NOR4 are NOR gates, A is a mode switching signal,
B is a data bus width selection signal, C is an upper / lower switching signal, DB
0 to DB15 are data buses, and P0 to P15 are input / output terminals. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] It has n (even number of n ≧ 2) input / output terminals connectable to an external data bus, and the n input / output terminals are k (=
n-bit internal data consisting of n / 2) lower I / O terminals and k upper I / O terminals, and a k (= n / 2) -bit lower internal data bus and a k-bit upper internal data bus A bus; k first transmission gates provided between each of the k lower-order input / output terminals and each bit of the k-bit lower-order internal data bus; K second transmission gates provided between each bit of the k-bit upper internal data bus, and k second transmission gates each of the k lower input / output terminals and each bit of the k-bit upper internal data bus K number of third transmission gates provided therebetween, and first control means for controlling conduction / non-conduction of the k number of second transmission gates based on an external control signal; Based on an external control signal different from the external control signal, the k first and third transmission gates are both made non-conductive, or among the k first and third transmission gates, A second control unit that makes one conductive and the other non-conductive, wherein the input / output terminal is connected to the internal data bus in a non-connected state, and the input / output terminal is a device other than data to be transmitted and received between the internal and external data buses. A microcomputer that can be used as a signal input / output terminal.