JP2817690B2 - Display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device which includes a frame memory for storing drawing / display data, and enables drawing / display data of the same contents read from the frame memory to be displayed on both a CRT and an LCD. About.

[0002]

2. Description of the Related Art In the prior art, a frame memory for storing drawing / display data is provided, and the drawing / display data having the same contents read from the frame memory can be displayed on both a CRT and an LCD. Once the CRT output data from the CRT frame buffer is
It is necessary to take in the frame buffer for use and display the image on the LCD from this frame buffer using the LCD synchronization clock. That is, drawing performance is maintained by having a frame buffer for one screen for LCD display, but a large-capacity frame memory is required.

[0003] JP-A-5-303348 discloses LC
A method for reducing the memory capacity of the D frame buffer is disclosed, but the condition is that the frame frequency of the LCD and the frame frequency of the CRT need to be synchronized, and the frame frequency of the LCD and the CRT Does not hold when the frame frequency is asynchronous.

Japanese Patent Application Laid-Open No. 63-50893 discloses LC
A display control circuit that uses a FIFO buffer instead of the D frame buffer to reduce the capacity is disclosed. FIG. 4 is a block diagram showing the configuration of the display control circuit disclosed in the above publication. In the figure, reference numeral 401 denotes an image memory (VR)
AM), 402 is a display controller (GDC), 403
Is a parallel-serial conversion circuit, 404 is a timing generation circuit, 405 is a FIFO buffer for LCD, 406,
407 is a counter, 408 is an address latch, 409,
410, 411 are multiplexers, 412, 413, 4
Reference numeral 14 denotes an address signal, a write signal, and a control signal from a CPU (not shown).

[0005] Dual-Scan STN-LC of this publication
In the case of D, the data for the upper and lower panels is
When the image data is stored in the IFO buffer 405, the image memory (VRAM) 401 serving as the CRT frame buffer
Also in the l-Port-RAM, in addition to the display read access for the CRT, an additional display read access for the LCD is required for one of the upper and lower panels, and when the frame frequency of the LCD and the frame frequency of the CRT are asynchronous, the upper and lower panels need to be accessed. , The drawing performance is lower than that of the conventional method. Also, to keep the performance,
Dual-Port-R as RT frame buffer
Must be AM.

[0006]

In the conventional system, an LCD is used.
Although the drawing performance is maintained by having a frame buffer for one screen for display for display, a large-capacity frame memory is required for this. In order to reduce the capacity of the frame buffer, the frame frequency of the CRT and the L
It is necessary to limit the frame frequency of the CD to synchronization. Also, Dual- as a CRT frame buffer
The method of using the Port-RAM and the FIFO buffer instead of the LCD frame buffer has affected the drawing performance.

It is an object of the present invention to convert drawing / display data of the same contents read from a frame memory into a CRT and a LRT.
A display control device that enables display on any CD, saves memory and supports even if the LCD display clock is asynchronous, enabling simultaneous asynchronous LCD and CRT simultaneous display without deteriorating drawing performance. And a display control device.

[0008]

A display control device according to the present invention includes a frame memory for storing drawing / display data, and a drawing / display device having the same contents read from the frame memory.
In a display control device that enables display data to be displayed on both a CRT and an LCD, RGB data output from a palette that is converted from drawing and display data for CRT into a set color and output as RGB data is temporarily stored. LCD memory and RGB output from palette
LCD that stores data in LCD memory and controls LCD display leads according to the display cycle difference between CRT and LCD
Memory control circuit is provided.

In a display control device having a frame memory for storing drawing / display data and enabling the same drawing / display data read from the frame memory to be displayed on both a CRT and an LCD, a display control device for a CRT is provided. An LCD FIFO buffer for temporarily storing RGB data output from a pallet in which display data is converted to a set color and output as RGB data, a storage of RGB data output from the pallet in an LCD FIFO buffer, and a CRT And L according to the display cycle difference of LCD
An LCD FIFO buffer control circuit for controlling the CD display lead may be provided.

Therefore, an LCD memory or an LCD FI
FO buffer and dedicated LCD memory control circuit or L
By providing a FIFO buffer control circuit for CD,
By utilizing the difference in the dot display frequency between the LCD and the CRT, the memory is saved by that ratio, and even if the LCD display clock is asynchronous, the asynchronous LCD and CRT can be used simultaneously without deteriorating the drawing performance. Display becomes possible.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram for explaining the first embodiment of the present invention, and FIG. 2 is a timing chart for explaining the embodiment of the present invention.

In the figure, reference numeral 101 denotes a frame memory, 10
2 is a display controller, 103 is a display data buffer, 104 is a palette, 105 is an LCD memory, 10
6 is a memory control circuit for LCD, 107 is a gradation conversion circuit,
108 is a DA converter, 109 is an LCD (Dual-
(ScanSTN-LCD), 110 is a CRT.

As shown in FIG. 1, a display control apparatus according to a first embodiment of the present invention controls a frame memory 101 for storing drawing / display data, reading / display data reading from the frame memory 101, and buffer control. A display controller 102 for temporarily storing drawing / display data;
A display data buffer 103, a pallet 104, and an LC for temporarily storing data output from the pallet 104
D memory 105, storage of pallet 104 output data in LCD memory 105, CRT 110 and LCD 10
9L to control LCD display lead according to display cycle difference
CD memory control circuit 106 and gradation conversion circuit 107
, A DA converter 108 and an LCD (Dual-Sc)
an STN-LCD) 109 and a CRT 110.

Next, the operation of the first embodiment of the present invention will be described with reference to FIG.

As a CRT display sequence, first, the display controller 102
The drawing / display data for T is read, and the drawing / display data for CRT is stored in the drawing / display data buffer 103. Then, drawing / drawing is performed at the timing of the CRT display clock.
The drawing / display data for CRT stored in the display data buffer 103 is output to the palette 104, and the drawing / display data for CRT is converted into colors set in the palette by the palette 104 to become RGB data (digital data). , RGB data are converted into analog signals by the DA converter 108 and output to the CRT 110.

As an LCD display sequence, the RGB data output from the pallet 104
It is stored in the LCD memory 105 at the display clock timing. The data capacity to be stored is LCD109 and CRT11
0 when the display frequency ratio is 1/2 (CRT-VSYNC = 60 Hz and V on one side of the LCD as shown in the timing of FIG. 2).
SYNC (FL in Dual-Scan STN-LCD)
M) = 30 Hz), which is ／ of the memory capacity required for display on the upper and lower panels (memory capacity for storing the upper and lower ＲＴ of the CRT-DISP indicating the CRT display output timing in FIG. 2). Similarly, CRT-VSYNC = 90HZ, VSYNC on one side of LCD (LCD-FLM) = 30Hz
In the case of, the data capacity to be stored is １ ／ of the memory capacity required for displaying the upper and lower panels.

While the LCD memory control circuit 6 detects the address counter value of the drawing / display data read for CRT, the RCB data output from the pallet 104 to the DA converter 108 corresponds to the upper and lower panels. LCD within the address range for storing data to be stored
(The timing is L in FIG. 2).
CD-stored data).

Next, the LCD memory control circuit 106
The RGB data stored in the CD memory 105 is time-divided for the upper and lower panels at the LCD display clock timing and output to the gradation conversion circuit 107 (the timing is LCD-DISP in FIG. 2).

Then, the gradation is converted by the gradation conversion circuit 107 and output to the Dual-Scan STN-LCD (upper / lower panel) 109.

Next, for the remaining display, the above is repeated to complete the display.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram for explaining the second embodiment of the present invention.

In the figure, reference numeral 301 denotes a frame memory, 30
2 is a display controller, 303 is a display data buffer, 304 is a palette, 305 is an LCD FIFO buffer, 306 is an LCD FIFO buffer control circuit,
07 is a gradation conversion circuit, 308 is a DA converter, 309
Is LCD (Dual-ScanSTN-LCD), 3l
0 is a CRT.

As shown in FIG. 3, a display control apparatus according to a second embodiment of the present invention includes a frame memory 301 for storing drawing / display data, and a display controller for reading display data from the frame memory 301 and controlling a buffer. 3
02, a drawing / display data buffer 303 for temporarily storing drawing / display data, a pallet 304, and an LCD F for temporarily storing data output from the pallet 304.
IFO buffer 305 and LCD FIFO buffer 3
05 to store pallet 304 output data or CRT 31
0 and an LCD FIFO buffer control circuit 306 for controlling the LCD display read according to the display cycle difference between the LCD 309 and the LCD 309.
, A gradation conversion circuit 307, a DA converter 308,
LCD (Dual-Scan STN-LCD) 309
And a CRT 310.

The operation of the second embodiment of the present invention is the same as that of the above-described first embodiment of the present invention.
The same explanation can be given by replacing the LCD memory 105 with the LCD FIFO buffer 305 and the LCD memory control circuit 106 with the LCD FIFO buffer control circuit 306.

[0025]

As described above, the present invention relates to an LCD memory or an LCD FIFO buffer and a dedicated LCD.
By providing a memory control circuit for the LCD or a FIFO buffer control circuit for the LCD, the difference in the dot display frequency between the LCD and the CRT is used to save the memory by the ratio.
In addition, since the LCD display clock can be used even when the clock is asynchronous, it is generally possible to use an asynchronous LCD and C
There is an effect of enabling simultaneous display of RT.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the embodiment of the present invention.

FIG. 3 is a block diagram for explaining a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a display control circuit disclosed in the official gazette.

[Explanation of symbols]

101, 301 Frame memory 102, 302, 402 Display controller 103, 303 Drawing / display data buffer 104, 304 Palette 105 LCD memory 106 LCD memory control circuit 107, 307 Gradation conversion circuit 108, 308 DA converter 109 , 309 LCD (Dual-ScanSTN)
-LCD) 110, 310 CRT 305, 405 FIFO buffer for LCD 306 FIFO buffer control circuit for LCD 401 Image memory (VRAM) 403 Parallel-serial conversion circuit 404 Timing generation circuit 406, 407 Counter 408 Address latch 409, 410, 411 Multiplexer 412 Address signal from CPU 413 Write signal from CPU 414 Control signal from CPU

Claims (2)

(57) [Claims] 1. A display control device comprising a frame memory for storing drawing / display data, wherein said drawing / display data of the same content read from said frame memory can be displayed on both a CRT and an LCD. An LCD memory for temporarily storing the RGB data output from a pallet in which the drawing / display data is converted into a set color and output as RGB data; and an L for the RGB data output from the pallet.
A display control device, comprising: an LCD memory control circuit that controls LCD display leads in accordance with storage in a CD memory or a display cycle difference between a CRT and an LCD. 2. A display control device comprising: a frame memory for storing drawing / display data, wherein said drawing / display data having the same contents read from said frame memory can be displayed on both a CRT and an LCD. A FIFO buffer for LCD for temporarily storing the RGB data output from a pallet in which the drawing / display data is converted into a set color and output as RGB data; and an L buffer for the RGB data output from the pallet.
LCD that controls display lead for LCD according to storage in FIFO buffer for CD and display cycle difference between CRT and LCD
A display control device, comprising: a first-use FIFO buffer control circuit.