JP2817213B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bipolar transistor having a shallow base region.

[Conventional technology]

Conventionally, as a method of forming a base region of a bipolar transistor, there are a method of implanting impurity atoms into a collector region by an ion implantation method and a method of diffusing impurity atoms from a polycrystalline silicon film or the like by a thermal diffusion method.

2 (a) and 2 (b) show the latter method of forming a base region in the order of steps.

First, as shown in FIG. 2A, an N-type collector region 22 is formed on a P-type silicon substrate 21, an N-type epitaxial growth layer 23 is further grown thereon, and a thick silicon oxide film 24 is formed on a part thereof. It is selectively formed to separate the elements. And
A P-type polycrystalline silicon film 25 and a silicon oxide film 26 are formed on the silicon oxide film 24, and are selectively etched. A side wall 27 of the silicon oxide film is formed on a side surface of the polycrystalline silicon film 25. After that, the P-type impurity atoms are diffused from the polycrystalline silicon film 25 and the compensation base region 28 is formed.
To form Thereafter, a polycrystalline silicon film 29 is formed in a region including between the side walls.

Next, as shown in FIG.
A base region 30 is formed by adding a P-type impurity atom, for example, a boron atom to the epitaxial growth layer 29 by an ion implantation method and diffusing the same into the epitaxial growth layer by a thermal diffusion method.

Subsequently, an N-type impurity atom, for example, an arsenic atom is added to the polycrystalline silicon film 29 by an ion implantation method, and is added to a base region by a thermal diffusion method to form an emitter region 31. At this time, it is necessary to determine the diffusion conditions so that the base region 30 is connected to the compensation base region 28 by lateral diffusion.

[Problems to be solved by the invention]

The above-described conventional method for manufacturing a bipolar transistor has the following problems.

When the base region is formed by the former ion implantation method, a tail occurs in the P-type impurity profile as shown by a curve a in FIG. 3 due to the channeling phenomenon of the ion implantation, and it is difficult to form a shallow junction.

In the latter method of forming a base region by diffusing impurity atoms from the polycrystalline silicon film shown in FIG. 2, impurity atoms are introduced from the polycrystalline silicon film 29 by thermal diffusion. A shallow base layer without a tail can be formed as shown by the curve b. However, since the effective film thickness at the peripheral portion of the polycrystalline silicon film 29 is large, diffusion of impurity atoms is suppressed, and the base depth at the peripheral portion of the base region is further reduced. For this reason, the connection between the compensation base region 28 and the base region 30 is weakened, and a problem such as an increase in base resistance occurs.

In this case, if the polycrystalline silicon film 29 is made thin to promote the diffusion of impurity atoms in the peripheral portion, when arsenic atoms are diffused from the same polycrystalline silicon film to form an emitter, a high concentration of arsenic atoms is reduced. The diffusion causes an increase in the arsenic concentration in the peripheral portion, the diffusion proceeds in the lateral direction, and the effective base film thickness in the peripheral portion is reduced, thereby causing a problem that punch-through occurs between the collector and the emitter.

An object of the present invention is to solve the above-mentioned problems and to provide a method for manufacturing a bipolar transistor having a suitable shallow base region.

[Means for solving the problem]

According to the method of manufacturing a semiconductor device of the present invention, after forming a compensation base region using a first polycrystalline silicon film, a region surrounded by a side wall formed on a side surface of the first polycrystalline silicon film has a reverse conductivity. Forming a second polycrystalline silicon film containing an impurity of a type, forming a base region by diffusing impurities from the second polycrystalline silicon film into a semiconductor layer, and forming a second polycrystalline silicon film. Forming a third polycrystalline silicon film on top of the substrate, introducing an impurity of one conductivity type into the third polycrystalline silicon film, and passing the impurity through the second polycrystalline silicon film to form a base region. To form an emitter region.

[Action]

In this manufacturing method, the second region is formed when forming the base region.
In forming the emitter region, the second and third polycrystalline silicon films are used, so that the film thickness of the polycrystalline silicon film at the time of forming the emitter region is reduced. It can be thicker than it is, suppressing emitter diffusion and preventing punch-through.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (e) are sectional views showing one embodiment of the manufacturing method of the present invention in the order of steps.

First, as shown in FIG. 1A, an N-type collector region 2 is formed by selectively diffusing arsenic atoms into a P-type silicon substrate 1, and an N-type epitaxial growth layer 3 is formed thereon to a thickness of 1 μm. . On the surface of the N-type epitaxial growth layer 3, a silicon oxide film 4 for element isolation is formed by a selective oxidation method.

Next, as shown in FIG. 1 (b), a first polycrystalline silicon film 5 is deposited to a thickness of 2500.degree. By a CVD method, and is selectively oxidized to form a silicon oxide film 6. The film 5 is isolated. Then, boron atoms are added to a part of the first polycrystalline silicon film 5 by an ion implantation method,
A P-type polycrystalline silicon film 5a is formed. Similarly, an arsenic atom or a phosphorus atom is added to another portion of the polycrystalline silicon film 5 by an ion implantation method or a diffusion method to form an N-type polycrystalline silicon film 5b. Thereafter, a silicon oxide film 7 is deposited to a thickness of 2000 mm over the entire surface by the CVD method.

Next, as shown in FIG. 1C, a heat treatment is performed to diffuse boron atoms from the P-type polycrystalline silicon film 5a into the epitaxial growth layer 3 to form a P-type compensation base region 9.
At this time, arsenic atoms or phosphorus atoms are simultaneously diffused from the N-type polycrystalline silicon film 5b into the epitaxial growth layer 3 to form the collector connection layer 10.

Further, holes are selectively opened in the base formation regions of the silicon oxide film 7 and the P-type polycrystalline silicon film 5a by anisotropic etching.
The epitaxial growth layer 3 is exposed. Then, after a silicon oxide film is deposited to a thickness of 3000 mm on the entire surface by the CVD method, the silicon oxide film is etched by an anisotropic etching method, and the sidewall 8 is formed leaving the silicon oxide film on the side surface of the opening. Further, a second polycrystalline silicon film 11 is deposited to a thickness of 1000 mm over the entire surface including the opening by the CVD method, and boron atoms are added to the polycrystalline silicon film 11 by an ion implantation method. Then, a heat treatment at 950 ° C. is performed to diffuse boron atoms from the second polycrystalline silicon film 11 into the epitaxial growth layer 3 to form a base region 12.

Next, as shown in FIG.
The polycrystalline silicon film 13 is deposited to a thickness of 2000 mm and integrated with the second polycrystalline silicon film 11. Then, arsenic atoms are added to the third polycrystalline silicon film 13 by an ion implantation method, and a heat treatment at 900 ° C. is performed to remove arsenic atoms from the third polycrystalline silicon film 13 to the second polycrystalline silicon film 11. And diffuses through it into the base region 12 to form the emitter region 14. This heat treatment is controlled so that the arsenic concentration around the opening is lower than the center of the opening.
Then, the third and second polycrystalline silicon films are formed by photolithography.
13, 11 are selectively etched sequentially.

Thereafter, as shown in FIG. 1 (e), a silicon oxide film 15 as an interlayer insulating film is deposited to a thickness of 1000.degree. By a CVD method, a hole is selectively formed in the silicon oxide film 15, and an aluminum electrode 16 is selectively formed. It is formed and used as each electrode of a collector, a base, and an emitter.

According to this manufacturing method, when forming the base region 12,
Since boron atoms are ion-implanted into the second polycrystalline silicon film 11 and then diffused, the boron atoms are diffused through a relatively thin polycrystalline silicon film, and the boron atom concentration is not significantly reduced. The compensation base region 9 and the base region 12 are connected well to prevent an increase in the base resistance.
On the other hand, when forming the emitter region 14, a third polycrystalline silicon film 13 is formed so as to overlap with the second polycrystalline silicon film 11,
As a result, arsenic atoms and the like are ion-implanted into the thick polycrystalline silicon film and diffused, so that the diffusion distance of the arsenic atoms in the polycrystalline silicon film in the peripheral portion increases, and the arsenic concentration decreases. I do. This suppresses arsenic diffusion around the base region and prevents punch-through between the collector and the emitter.

〔The invention's effect〕

As described above, according to the present invention, since only the second polycrystalline silicon film is used in forming the base region, the base diffusion is promoted, and the connection between the base region and the compensation base region is made sufficient. , Preventing an increase in base resistance. In forming the emitter region, the second and third
The use of a polycrystalline silicon film makes it possible to increase the thickness of the polycrystalline silicon film, suppress the concentration of atoms forming the emitter around the base region, and prevent the punch-through phenomenon between the collector and emitter. Can be.

[Brief description of the drawings]

1 (a) to 1 (e) are cross-sectional views showing one embodiment of the present invention in the order of manufacturing steps, FIGS. 2 (a) and 2 (b) are cross-sectional views showing some steps of a conventional manufacturing method, FIG. 3 is a profile diagram of the impurity concentration in the base region. 1 .... P-type silicon substrate, 2 .... N-type collector region, 3
... N-type epitaxial growth layer, 4 silicon oxide film, 5 first polycrystalline silicon film, 5a P-type polycrystalline silicon film, 5b N-type polycrystalline silicon film, 6 silicon oxide Film 7, silicon oxide film 8, side wall 9,
... compensation base region, 10 ... collector connection layer, 11 ... second
A polycrystalline silicon film, 12 ... a base region, 13 ... a third polycrystalline silicon film, 14 ... an emitter region, 15 ... a silicon oxide film, 16 ... an aluminum electrode, 21 ... a P-type silicon substrate, 22 N-type collector region, 23 N-type epitaxial growth layer, 24 silicon oxide film, 25 polycrystalline silicon film, 26 silicon oxide film, 27 sidewall, 28
Compensation base region, 29: polycrystalline silicon film, 30: base region, 31: emitter region.

Claims (1)

(57) [Claims] A step of selectively forming a first polycrystalline silicon film containing an impurity of the opposite conductivity type on the semiconductor layer on which the collector region of one conductivity type is formed; Forming a compensation base region by diffusing impurities into the substrate, forming a side wall of the insulating film on the side surface of the polycrystalline silicon film, and forming a second region containing an impurity of the opposite conductivity type in a region surrounded by the side wall. Forming a base region by diffusing impurities from the second polycrystalline silicon film into the semiconductor layer; and forming a third region on the second polycrystalline silicon film. Forming a polycrystalline silicon film in an overlapping manner, introducing one conductivity type impurity into the third polycrystalline silicon film, and diffusing the impurity into the base region through the second polycrystalline silicon film. Form emitter region The method of manufacturing a semiconductor device which comprises a step.