JP2920912B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a step of forming a semiconductor region by diffusing impurities from a polycrystalline silicon (Si) film doped with impurities. It is suitable for application to the manufacture of a semiconductor device including:

[Summary of the Invention]

The method for manufacturing a semiconductor device according to the present invention forms an insulating film having an opening on a semiconductor substrate, is doped with impurities,
A step of forming a first semiconductor film by chemical vapor deposition with a film thickness equal to or less than half of the diameter of the opening at least inside the opening, and performing a heat treatment to form a first semiconductor film in the first semiconductor film. Forming a semiconductor region by diffusing the impurity into the semiconductor substrate; and forming a second region on the first semiconductor film.
Forming the first semiconductor film and the second semiconductor film at the same time, and filling the second semiconductor film in the opening to form a substantially flat surface. Forming a reaction prevention film and a wiring on the second semiconductor film, wherein an impurity of the same conductivity type as the impurity is doped in the second semiconductor film.
Thereby, the controllability of the junction depth of the semiconductor region formed by impurity diffusion from the semiconductor film can be improved, and the problem caused by poor coverage of the reaction suppression film and the wiring in the opening of the insulating film. Can be eliminated.

[Conventional technology]

Conventionally, various attempts have been made to achieve high speed and high integration of a bipolar transistor as an element constituting a bipolar LSI. As a result, a method of manufacturing a bipolar transistor has been developed in which an emitter region is formed using impurity diffusion from an impurity-doped polycrystalline Si film, thereby miniaturizing an element and reducing parasitic capacitance. .

According to the manufacturing method using the impurity diffusion from the polycrystalline Si film doped with the impurity, the bipolar transistor is manufactured as follows. That is, as shown in FIG. 8, first, for example, a p-type intrinsic base region 102 is formed in an n ⁻ -type silicon (Si) epitaxial layer 101, and then an insulating film 103 is formed on the epitaxial layer 101. . Next, after forming an opening 103a in the insulating film 103, a polycrystalline Si film 104 heavily doped with n-type impurities is formed.
Next, by performing a heat treatment, the n-type impurities in the polycrystalline Si film 104 are diffused into the intrinsic base region 102 so that n ⁺
A mold emitter region 105 is formed. Next, the polycrystalline Si
A barrier metal film 106 and a wiring 107 made of, for example, aluminum (Al) are formed on the film 104. This barrier metal film 106
Is the junction depth x _je of the emitter region 105 for the purpose of speeding up.
Is considered to be indispensable for suppressing the reaction between the polycrystalline Si film 104 and the Al wiring 107.

In recent years, with the progress of miniaturization, the emitter width W _E of 1 μm or less
Accordingly, the aspect ratio of the opening 103a of the insulating film 103 has become extremely large. As a result, the coverage of the barrier metal film 106 and the wiring 107 in the opening 103a is poor. Poor coverage of the wiring 107 leads to poor reliability against electromigration. In addition, poor coverage of the barrier metal film 106 causes breakage of the barrier metal film 106 during heat treatment of a sinter or the like performed after the formation of the wiring 107, so that the emitter region 105 through the barrier metal film 106 decrease in DC current gain h _FE of the transistor due to Al penetration to the side, the emitter - leads to characteristic defects such as base junction.

Japanese Patent Application Laid-Open No. Sho 62-73711 proposes the following method for manufacturing a bipolar transistor for the purpose of solving the above-mentioned problems. That is, according to this method, after forming the opening 103a in the insulating film 103 as shown in FIG. 8, a thick polycrystalline Si film is formed on the entire surface. Next, the polycrystalline Si film is etched back by reactive ion etching (RIE) to fill the inside of the opening 103a with the polycrystalline Si film to the same height as the thickness of the insulating film 103. Next, after arsenic (As) is ion-implanted into the polycrystalline Si film, heat treatment is performed to reduce As in the polycrystalline Si film to the intrinsic base region 102.
The emitter region 105 is formed by being diffused therein.

[Problems to be solved by the invention]

However, when the above-described manufacturing method proposed in Japanese Patent Application Laid-Open No. 62-73711 is used, the accuracy of etching by RIE is not so good, so that the polycrystalline Si embedded in the opening 103a of the insulating film 103 is not used. Variations in film thickness are inevitable. Therefore, the emitter region 10 formed by diffusing the impurity doped in the polycrystalline Si film is formed.
There was a problem that the controllability of the junction depth x _je of 5 was not good.

It is therefore an object of the present invention to provide a doped polycrystalline
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of improving controllability of a junction depth of a semiconductor region formed by impurity diffusion from a Si film.

Another object of the present invention is to provide a method of manufacturing a semiconductor device that can solve the problem caused by poor coverage of a reaction suppression film and wiring in an opening of an insulating film.

[Means for solving the problem]

According to the present invention, an insulating film (3) having an opening (3a) is formed on a semiconductor substrate (1), and is doped with impurities and has a thickness of not more than half the diameter of the opening (3a). Forming a first semiconductor film (4) at least inside the opening (3a) by a growth method, and diffusing impurities in the first semiconductor film (4) into the semiconductor substrate (1) by performing heat treatment. Forming a semiconductor region (5), forming a second semiconductor film (6) on the first semiconductor film (4), and forming a first semiconductor film (4) and a second semiconductor film. The film (6) is simultaneously etched back, and the second semiconductor film (6) is formed in the opening (3a).
Forming a substantially flat surface, and forming a reaction prevention film (7) and a wiring (8) on the second semiconductor film (6), and having the same conductivity type as the impurity. This is a method for manufacturing a semiconductor device in which an impurity is doped in the second semiconductor film (6).

[Action]

According to the above-described means, the first semiconductor film serving as an impurity diffusion source can be formed by a film forming technique such as a CVD method having good controllability of the film thickness. The controllability of the junction depth of the semiconductor region formed by diffusion can be improved. Further, since the reaction suppressing film and the wiring are formed on the flat surface formed by filling the opening of the insulating film with the second semiconductor film, the coverage of the reaction suppressing film and the wiring in this opening is good. Yes, so the problem caused by poor coverage can be eliminated.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIGS. 1 to 5 show a bipolar transistor according to Embodiment I of the present invention.
FIG. 4 is a cross-sectional view illustrating a method of manufacturing an LSI in a process order.

In this embodiment I, as shown in FIG. 1, first, for example, n ^- type Si formed on a semiconductor substrate (not shown)
After forming, for example, a p-type intrinsic base region 2 in the epitaxial layer 1 by ion implantation or the like, a film thickness of, for example, 2000 to 700 is formed on the Si epitaxial layer 1 by, for example, a CVD method.
An insulating film 3 such as a SiO ₂ film of about 0 ° is formed. next,
After a predetermined portion of the insulating film 3 is removed by etching to form an opening 3a, an intrinsic (i-type) polycrystalline Si film 4 having a thickness equal to or less than 1/2 of the diameter of the opening 3a is formed on the entire surface by, for example, a CVD method. Form. Specifically, the diameter of the opening 3a is, for example, about 1.2 μm, and the thickness of the polycrystalline Si film 4 is, for example, 500 to 2000.
About Å. Thereafter, the polycrystalline Si film 4 is ion-implanted with, for example, As as an n-type impurity at a high concentration to make it n ⁺ -type.
As a method of doping As into the polycrystalline Si film 4, for example, after forming an arsenic silicate glass (AsSG) film on the polycrystalline Si film 4, As in the AsSG film is A method of diffusing the film 4 may be used.

Next, by performing a heat treatment, the polycrystalline Si film 4
As is diffused into the intrinsic base region 2 in contact with the polycrystalline Si film 4, and as shown in FIG. 2, an n ⁺ -type emitter region 5 is self-aligned with the opening 3a. Form. The emitter region 5 and the intrinsic base region 2
And the collector region composed of the Si epitaxial layer 1 constitutes an npn-type bipolar transistor.

Next, as shown in FIG. 3, a sufficiently thick polycrystalline Si film 6 is formed on the entire surface by, for example, a CVD method. The thickness of the polycrystalline Si film 6 on the insulating film 3 is, for example, about 1 to 2 μm.

Next, the polycrystalline Si films 6 and 4 are etched back until the surface of the insulating film 3 is exposed by, for example, RIE. Thereby, as shown in FIG. 4, the opening 3a of the insulating film 4 is filled with the polycrystalline Si films 6, 4 having the same height as the insulating film 3 to form a flat surface.

Thereafter, as shown in FIG.
Denotes a barrier metal film 7 and a wiring 8 of, for example, Al on a flat surface.
To complete the target bipolar LSI.
The wiring 8 and the polycrystalline Si films 6 and 4 are formed by the barrier metal film 7.
The reaction with is suppressed. As the barrier metal film 7, for example, a titanium nitride (TiN) film having a thickness of about 1000Å or a titanium tungsten (TiW) film having a thickness of about 3000Å can be used.

According to the embodiment I, there are various advantages as follows.
That is, the polycrystalline Si film 4 used to form the emitter region 5 can be formed by a film forming technique such as a CVD method having good controllability of the film thickness. Controllability of the junction depth x _je of the emitter region 5 formed by impurity diffusion can be improved. Since the barrier metal film 7 and the wiring 8 are formed on the flat surface formed by filling the opening 3a of the insulating film 3 with the polycrystalline Si film 6, these barrier metal films in the opening 3a are formed. 7 and the wiring 8 have good coverage. Since the coverage of the barrier metal film 7 is good, there is no possibility that the barrier metal film 7 is broken or the like during heat treatment of a sinter or the like performed after the formation of the wiring 8.
Al can be prevented from entering the emitter region 5 from the side. This reduction and the emitter of the h _FE due to the penetration of the Al - it is possible to prevent variations in the base junction, the failure and the like. Further, since the coverage of the wiring 8 is good, the reliability against electromigration can be improved. In other words, the conventional problem caused by poor coverage of the barrier metal film 7 and the wiring 8 in the opening 3a can be solved.

Embodiment II FIG. 6 is a cross-sectional view for explaining a method of manufacturing a bipolar LSI according to Embodiment II of the present invention.

In this embodiment II, as shown in FIG. 6, first, for example, an n ⁺ -type buried layer 10 and a p ⁺ -type channel stopper region are provided in a semiconductor substrate 9 such as a p-type Si substrate.
After the formation of 11, for example, an n ^- type
The Si epitaxial layer 1 is formed. Next, by selectively thermally oxidizing the surface of the Si epitaxial layer 1, a field insulating film 12 such as an SiO ₂ film is formed to perform element isolation and element isolation. Next, for example, phosphorus (P) is selectively ion-implanted into a predetermined portion of the epitaxial layer 1 and then heat treatment is performed to diffuse the P to form, for example, an n ⁺ -type collector extraction region 13.

Next, after forming, for example, a polycrystalline Si film on the entire surface, the polycrystalline Si film is doped with a p-type impurity such as, for example, boron (B) at a high concentration by ion implantation or the like to form ap ⁺ type. This p ⁺ -type polycrystalline Si film is patterned into, for example, a square shape. Next, an insulating film such as a SiO ₂ film is formed on the entire surface. Next, predetermined portions of the insulating film and the p ⁺ -type polycrystalline Si film are removed by etching to form a base lead electrode 14 and an insulating film covering the base lead electrode 14. next,
A p-type impurity such as B is ion-implanted into the epitaxial layer 1 through the opening 14a formed in the base extraction electrode 14 to form, for example, a p-type intrinsic base region 2, and then heat treatment is performed. This implanted impurity is electrically activated. During this heat treatment,
A p-type impurity is diffused into the epitaxial layer 1 from the p ⁺ -type polycrystalline Si film constituting the base extraction electrode 14. This allows, for example, a p ⁺ type graft base region 15
Are formed continuously with the intrinsic base region 2. next,
After an insulating film such as a SiO ₂ film is formed on the entire surface, the insulating film is anisotropically etched by RIE, for example, to form a side wall (side wall) made of an insulator on the side surface of the opening 14 a of the base lead electrode 14. To form Thereby, the insulating film 3 having the opening 3a having an extremely small diameter is formed.

Next, a polycrystalline Si film 4 doped with an n-type impurity is formed inside the opening 3a of the insulating film 3 in the same manner as in Example I, and then heat treatment is performed to remove the polycrystalline Si film 4 from the polycrystalline Si film 4. An n-type impurity is diffused into the intrinsic base region 2 to form an emitter region 5 in a self-aligned manner with respect to the opening 3a.
Next, the opening 3a is filled with a polycrystalline Si film 6 to form a flat surface. Next, predetermined portions of the insulating film 3 are removed by etching to form openings 3b and 3c. Next, a barrier metal film is formed on the entire surface, an Al film is further formed on the barrier metal film, and the Al film and the barrier metal film are sequentially patterned by etching to form a barrier metal film having a predetermined shape. 7a to 7c and wirings 8a to 8c are formed. As a result, the intended bipolar LSI is completed.

According to Example II, as in Example I, polycrystalline Si
An emitter region 5 is formed by impurity diffusion from the film 4;
Since the barrier metal film 7a and the wiring 8a are formed on the flat surface formed by filling the opening 3a with the polycrystalline Si film 6, the controllability of the junction depth x _je of the emitter region 5 is improved. it is possible to achieve reduction and emitter of h _FE for coverage is good barrier metal film 7a and the wiring 8a of the opening 3a - it is possible to solve the conventional problems of poor characteristics or the like of the base junction. Further, since the diameter of the opening 3a can be reduced to, for example, 1 μm or less,
μm can be achieved following a fine emitter width W _E.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, in the above Examples I and II, after the polycrystalline Si film 4 doped with impurities is formed, the polycrystalline Si film 4 is patterned by etching to leave only the opening 3a, and then the portion of the opening 3a is formed. By selectively growing a polycrystalline Si film on the remaining polycrystalline Si film 4, the opening 3a
It is also possible to fill in. Also, this opening 3a is made of polycrystalline
After forming a flat surface by filling with a Si film, it is possible to lower the resistance by doping the polycrystalline Si film with an n-type impurity at a low temperature.

Further, in the above-described Examples I and II, the case where the present invention is suitable for manufacturing a bipolar LSI has been described.
The present invention can be applied to the manufacture of a semiconductor device other than the bipolar LSI. For example, FIG.
An example applied to the manufacture of SLSI is shown. As shown in FIG.
In this MOSLSI manufacturing method, for example, a field insulating film 16 is formed on the surface of a semiconductor substrate 15 (or p-well) such as a p-type Si substrate to perform element isolation, and then surrounded by the field insulating film 16. A gate insulating film 17 such as a SiO ₂ film and a gate electrode 18 formed of a polycrystalline Si film are formed on the surface of the active region. Next, in order to form low impurity concentrations 20a and 21a of a source region 20 and a drain region 21 described later, the semiconductor substrate 15 is formed using the gate electrode 18 as a mask.
An n-type impurity such as P is ion-implanted at a relatively low concentration. Next, after forming an insulating film such as a SiO ₂ film on the entire surface, the insulating film is anisotropically etched by RIE, for example, to form side walls 19 on the side surfaces of the gate electrode 18. Next, using the side wall 19 as a mask, the semiconductor substrate
An n-type impurity such as As is ion-implanted at a relatively high concentration. Thereby, for example, an n ⁺ -type source region 20 and a drain region 21 having, for example, n ⁻ -type low impurity concentration portions 20a, 20a are formed in a self-aligned manner with respect to the gate electrode. Next, after an insulating film 22 such as a boron phosphorus silicate glass (BPSG) film is formed on the entire surface, predetermined portions of the insulating film 22 are removed by etching to form openings 22a and 22b. Next, by performing a heat treatment, the insulating film
22 is reflowed so that these openings 22a and 22b are tapered. Next, after forming thin polycrystalline Si films 23a and 23b doped with n-type impurities inside these openings 22a and 22b,
By performing heat treatment, the n-type impurities in these polycrystalline Si films 23a and 23b are removed from the source region 20 and the drain region 21a.
Diffused into these source region 20 and drain region.
The n ⁺ -type semiconductor regions 24a and 24b having an impurity concentration higher than 21 are formed. Next, the openings 22a and 22b are formed through the polycrystalline Si films 25a and 25b.
To form a substantially flat surface. Thereafter, barrier metal films 26a, 25b and wirings 27a, 27b are formed on these polycrystalline Si films 25a, 25b. In the case of this example, the semiconductor regions 24a and 24b having a higher impurity concentration than the source region 20 and the drain region 21 can stably obtain an ohmic contact of the polycrystalline Si films 23a and 23b with the source region 20 and the drain region 21. be able to.

〔The invention's effect〕

According to the present invention, an insulating film having an opening is formed on a semiconductor substrate, is doped with impurities, and is 1 / (the diameter of the opening).
A step of forming a first semiconductor film having a thickness of 2 or less by a chemical vapor deposition method at least inside the opening, and performing a heat treatment to remove the impurities in the first semiconductor film into the semiconductor substrate. Forming a semiconductor region by diffusion, forming a second semiconductor film on the first semiconductor film, etching back the first semiconductor film and the second semiconductor film simultaneously, A step of burying the second semiconductor film in the opening to form a substantially flat surface; and a step of forming a reaction prevention film and a wiring on the second semiconductor film, wherein the same conductivity type as that of the impurity is provided. Impurities of the second
Is doped into the semiconductor film, the controllability of the junction depth of the semiconductor region formed by impurity diffusion from the semiconductor film can be improved, and the reaction suppressing film and the wiring cover at the opening of the insulating film can be improved. Problems caused by bad ledges can be eliminated.

[Brief description of the drawings]

1 to 5 show a bipolar LS according to Embodiment I of the present invention.
FIG. 6 is a cross-sectional view illustrating a method of manufacturing a bipolar LSI according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a modification of the present invention. FIG. 8 is a cross-sectional view for explaining a conventional method for manufacturing a bipolar LSI. Explanation of the main symbols in the drawings 1: Si epitaxial layer, 2: intrinsic base region, 3: insulating film,
3a: opening, 4, 6: polycrystalline Si film, 7: barrier metal film (reaction suppressing film), 8: wiring.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/331 H01L 21/28 H01L 21/3205 H01L 21/336 H01L 29/73 H01L 29/78

Claims (1)

(57) [Claims] An insulating film having an opening is formed on a semiconductor substrate, and at least a first semiconductor film formed by a chemical vapor deposition method, which is doped with impurities and has a thickness equal to or less than half the diameter of the opening, is formed. Forming the semiconductor region inside the opening; performing heat treatment to diffuse the impurity in the first semiconductor film into the semiconductor substrate to form a semiconductor region; and forming a semiconductor region on the first semiconductor film. A step of forming a second semiconductor film, and simultaneously etching back the first semiconductor film and the second semiconductor film to fill the opening with the second semiconductor film to form a substantially flat surface. And a step of forming a reaction prevention film and a wiring on the second semiconductor film, wherein an impurity of the same conductivity type as the impurity is doped in the second semiconductor film. A method for manufacturing a semiconductor device.