JPH0371770B2 - - Google Patents
Info
- Publication number
- JPH0371770B2 JPH0371770B2 JP56062092A JP6209281A JPH0371770B2 JP H0371770 B2 JPH0371770 B2 JP H0371770B2 JP 56062092 A JP56062092 A JP 56062092A JP 6209281 A JP6209281 A JP 6209281A JP H0371770 B2 JPH0371770 B2 JP H0371770B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- film
- opening
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 8
- 241000293849 Cordylanthus Species 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に三
重拡散型集積回路装置（IC）の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a triple-diffused integrated circuit device (IC).
三重拡散型ICは例えばｐ型のシリコン基板に
ｎ型及びｐ型の不純物を交互に拡散してコレク
タ、ベース及びエミツタ領域を形成するので、シ
リコン基板上にエピタキシヤル成長層を形成する
必要がなく、近年に至り中・高速バイポーラトラ
ンジスタに使用される傾向にある。 For example, in a triple diffusion type IC, n-type and p-type impurities are alternately diffused into a p-type silicon substrate to form the collector, base, and emitter regions, so there is no need to form an epitaxial growth layer on the silicon substrate. In recent years, there has been a trend toward use in medium- to high-speed bipolar transistors.
上記三重拡散型ICの製造方法として従来第１
図に示すような窒化シリコン膜を用いる方法が提
唱されている。即ち同図ａに示すようにｐ型シリ
コン基板１表面に窒化シリコン（Si3N4）膜２を
形成し、これをパターニングして所定の開口３を
設け、次いで上記Si3N4膜２をマスク層として燐
（Ｐ）のようなｎ型不純物を上記開口３部に拡散
しｎ型のコレクタ領域４を形成する。なお図示は
していないがSi基板１とSi3N4膜２との間には通
常二酸化シリコン（SiO2）膜を介在せしめる。 The first conventional manufacturing method for the above triple diffusion type IC
A method using a silicon nitride film as shown in the figure has been proposed. That is, as shown in FIG. 1A, a silicon nitride (Si 3 N 4 ) film 2 is formed on the surface of a p-type silicon substrate 1, this is patterned to form a predetermined opening 3, and then the Si 3 N 4 film 2 is An n-type impurity such as phosphorus (P) is diffused into the opening 3 as a mask layer to form an n-type collector region 4. Although not shown, a silicon dioxide (SiO 2 ) film is usually interposed between the Si substrate 1 and the Si 3 N 4 film 2.
次いで同図ｂに見られるごとく上記開口３部表
面に加熱酸化法によりSiO2膜５を形成し、これ
を選択的に除去して所定の開口６を設け、該開口
６部にボロン(B)のようなｐ型不純物を拡散してｐ
型のベース領域７を形成する。この工程において
SiO2膜５は、上記開口３の一方の端部において
Si3N4膜と接続するように残留せしめ、残りの部
分は除去する。従つて上記ボロン(B)の拡散工程に
おいてもSiO2膜２はベース領域７を画定するマ
スク層として用いられる。 Next, as shown in Figure b, a SiO 2 film 5 is formed on the surface of the opening 3 by a thermal oxidation method, and this is selectively removed to form a predetermined opening 6, and boron (B) is applied to the opening 6. By diffusing p-type impurities such as
A base region 7 of the mold is formed. In this process
The SiO 2 film 5 is placed at one end of the opening 3.
The remaining portion is left so as to be connected to the Si 3 N 4 film, and the remaining portion is removed. Therefore, the SiO 2 film 2 is also used as a mask layer for defining the base region 7 in the boron (B) diffusion step.
次いで同図ｃに示す如く、上述したのと同様に
SiO2膜８を開口３内に選択的に形成し、SiO2膜
８の開口９，９′部にｎ型不純物を拡散してｎ型
のエミツタ領域１０及びコレクタのコンタクト層
１１を形成する。 Next, as shown in Figure c, in the same manner as described above.
A SiO 2 film 8 is selectively formed in the opening 3, and n-type impurities are diffused into the openings 9 and 9' of the SiO 2 film 8 to form an n-type emitter region 10 and a collector contact layer 11.
上述した従来の製造方法は、Si3N4膜２を固定
的なマスク層として用い、これを基準としてコレ
クタ、ベース、エミツタ領域４，７，１０及びコ
レクタコンタクト層１１の位置を決定するいわゆ
る自己整合法により製作するので、位置合せ余裕
を設ける必要がない。従つて素子の微細化及び高
密度化が可能となると目されていた。 The conventional manufacturing method described above uses the Si 3 N 4 film 2 as a fixed mask layer, and uses this as a reference to determine the positions of the collector, base, emitter regions 4, 7, and 10, and the collector contact layer 11. Since it is manufactured using the alignment method, there is no need to provide alignment margin. Therefore, it was expected that it would be possible to miniaturize and increase the density of elements.
所が上述の工程において開口３部基板表面を繰
り返し酸化するが、SiO2膜を形成したときSi3N4
膜２の端部には第２図〔第１図ａのＡ部拡大断面
図〕に示すごとくいわゆるバードビーク１２が形
成される。そのため、このあとに引き続く拡散工
程で形成されるベース領域７等の形状は上記バー
ドビーク１２部で乱れ、各接合間の間隔が所望の
如く制御できない等の問題があり、上記製造方法
は再現性の点で十分満足し得るとは言い難い。 However, in the above process, the substrate surface at the opening 3 is repeatedly oxidized, but when the SiO 2 film is formed, Si 3 N 4
A so-called bird's beak 12 is formed at the end of the membrane 2, as shown in FIG. 2 (enlarged sectional view of section A in FIG. 1a). Therefore, the shape of the base region 7 etc. formed in the subsequent diffusion process is disturbed at the bird's beak 12 portion, and there are problems such as the interval between each bond cannot be controlled as desired, and the above manufacturing method has poor reproducibility. It is difficult to say that we are fully satisfied with this point.
本発明の目的は上述の問題点を解消して、製造
工程の制御容易な、従つて再現性の良い三重拡散
型半導体装置の製造方法を提供することにあり、
そのため本発明の特徴は、一導電型を有する半導
体基板表面に、各々該半導体基板表面が露出した
第１の領域、および第２の領域を各々画定する第
１の絶縁膜を選択的に形成する工程と、
該第１の絶縁膜表面、該第１の領域表面、およ
び該第２の領域表面を覆うように、半導体層を形
成する工程と、
該第１の領域表面に開口部を有し、かつ該第２
の領域表面を覆うように、該半導体層表面に、第
１のマスクを形成する工程と、
該第１のマスクを用いて、該第１の領域内に逆
導電型不純物を添加し、逆導電型不純物領域を形
成する工程と、
該第１の領域表面には選択的に開口を有して覆
うように、また該第２の領域表面を覆うように、
耐酸化性の第２の絶縁膜を該第１の領域および該
第２の領域の各々の表面に形成する工程と、
該第２の絶縁膜をマスク層として用い、該第２
の絶縁膜が形成されない該第１の領域表面にある
該半導体層を酸化膜に変換することによつて、該
第１の領域を第３の領域と第４の領域とに分離画
定する工程と、
該第２の絶縁膜を除去する工程と、
該第４の領域表面を覆い、該第２の領域表面お
よび該第３の領域表面に開口部を有する第２のマ
スクを形成する工程と、
該第２のマスクを用いて、該第２の領域内およ
び該第３の領域内に各々一導電型不純物を添加
し、該第２の領域内および該第３の領域内に前記
逆導電型不純物領域に比し浅い一導電型不純物領
域形成する工程を含むことにある。 An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a triple diffusion type semiconductor device in which the manufacturing process can be easily controlled and therefore has good reproducibility.
Therefore, a feature of the present invention is to selectively form, on the surface of a semiconductor substrate having one conductivity type, a first insulating film defining a first region and a second region, respectively, where the semiconductor substrate surface is exposed. a step of forming a semiconductor layer so as to cover a surface of the first insulating film, a surface of the first region, and a surface of the second region; having an opening on the surface of the first region; , and the second
forming a first mask on the surface of the semiconductor layer so as to cover the surface of the region; using the first mask, doping an impurity of a reverse conductivity type into the first region; forming a type impurity region, selectively opening and covering the surface of the first region and covering the surface of the second region;
forming an oxidation-resistant second insulating film on each surface of the first region and the second region; using the second insulating film as a mask layer;
dividing the first region into a third region and a fourth region by converting the semiconductor layer on the surface of the first region where no insulating film is formed into an oxide film; , a step of removing the second insulating film, and a step of forming a second mask covering the surface of the fourth region and having openings on the surface of the second region and the surface of the third region, Using the second mask, impurities of one conductivity type are added into the second region and the third region, and impurities of the opposite conductivity type are added into the second region and the third region. The present invention includes a step of forming an impurity region of one conductivity type which is shallower than the impurity region.
以下本発明を実施例により詳細に説明する。 The present invention will be explained in detail below with reference to Examples.
第３図は本発明の一実施例を製造工程の順に示
す要部断面図である。本実施例ではシリコンnpn
型ウオールド・エミツタ構造のバイポーラ・トラ
ンジスタ素子をｐ型シリコン基板に作成する例を
掲げて説明する。 FIG. 3 is a cross-sectional view of a main part showing an embodiment of the present invention in the order of manufacturing steps. In this example, silicon npn
An example will be described in which a bipolar transistor element with a wall-emitter structure is fabricated on a p-type silicon substrate.
第３図ａに見られる如く、ｐ型シリコンSi基板
１表面に加熱酸化法により厚さ凡そ5000〔Å〕の
二酸化シリコンSiO2膜２１を形成し、これを所
定のパターンに従つて選択的に除去し、開口２
２，２２′を設ける。 As shown in FIG. 3a, a silicon dioxide SiO 2 film 21 with a thickness of approximately 5000 Å is formed on the surface of a p-type silicon Si substrate 1 by a thermal oxidation method, and this is selectively applied according to a predetermined pattern. Remove and open 2
2, 22' are provided.
次いで同図ｂに示す如く上記開口２２，２２′
部を含むSi基板上全面に凡そ1000〔Å〕の厚さの
シリコン多結晶層２３を形成する。 Next, the openings 22, 22' are opened as shown in FIG.
A silicon polycrystalline layer 23 with a thickness of about 1000 [Å] is formed over the entire surface of the Si substrate including the parts.
このシリコン多結晶層２３上に、同図ｃに示す
ように上記開口２３部を開口部とするレジスト膜
２４を形成し、イオン注入法により燐（Ｐ）のよ
うなｎ型不純物を注入し、レジスト膜２４を除去
したのち約1200〔℃〕で凡そ60〔分〕アニールして
ｎ型のコレクタ領域２５を形成する。本工程にお
いて上記イオン注入時における注入エネルギーを
凡そ120〔KeV〕とすることにより、不純物の燐
（Ｐ）はシリコン多結晶２３は透過するがSiO2膜
２１及びレジスト膜２４は透過しない。従つて燐
（Ｐ）は開口２３部にのみ注入され、更にアニー
ルされて基板１の深さ方向及び横方向に拡散し、
図示の如くコレクタ領域２５が形成される。なお
レジスト膜２４は開口２２′部にイオンが注入さ
れるのを防止するためのマスク層であるから開口
２２′が存在しない場合にはレジスト膜２４も不
要である。またレジスト膜２４の開口パターンは
前記開口２２より小さくなければよく、従つてそ
の寸法及び位置の双方共厳しい精度は必要ない。 On this polycrystalline silicon layer 23, a resist film 24 is formed with the opening 23 as an opening, as shown in FIG. After the resist film 24 is removed, an n-type collector region 25 is formed by annealing at about 1200° C. for about 60 minutes. In this step, by setting the implantation energy during the ion implantation to approximately 120 [KeV], the impurity phosphorus (P) passes through the silicon polycrystal 23 but does not pass through the SiO 2 film 21 and the resist film 24. Therefore, phosphorus (P) is injected only into the opening 23, and is further annealed to diffuse in the depth direction and the lateral direction of the substrate 1.
A collector region 25 is formed as shown. Note that since the resist film 24 is a mask layer for preventing ions from being implanted into the opening 22', the resist film 24 is also unnecessary if the opening 22' does not exist. Further, the opening pattern of the resist film 24 need not be smaller than the opening 22, and therefore, strict accuracy is not required in both its size and position.
次いで同図ｄに示すようにSi基板１上全面に化
学気相成長CVD法によりSi3N4膜２６を被着し、
これを選択的に除去して前記開口２２内の所定位
置に開口２７を設ける。このとき本実施例では開
口２２，２２′を画定するSiO2膜２１上にも開口
２７′を形成した。 Next, as shown in Figure d, a Si 3 N 4 film 26 is deposited on the entire surface of the Si substrate 1 by chemical vapor deposition (CVD).
This is selectively removed to provide an opening 27 at a predetermined position within the opening 22. At this time, in this embodiment, an opening 27' was also formed on the SiO 2 film 21 defining the openings 22, 22'.
次いで同図ｅに示すように上記残留せるSi3N4
膜２６をマスク層として酸化性雰囲気中で加熱処
理を施こし、前記シリコン多結晶層２３の開口２
７，２７′部で表面を露出せる部分をSiO2膜２
８，２８′に変換する。次いで前記マスク層とし
て用いたSi3N4膜２６を除去した後、開口２２部
のうちベース領域を形成すべき部分を除く他の区
域をレジスト膜２９で被覆し、イオン注入法によ
りボロン(B)のようなｐ型不純物を導入し、アニー
ルを行なつてｐ型のベース領域３０と基板コンタ
クト領域３１を形成する。 Then, as shown in Figure e, the remaining Si 3 N 4
Using the film 26 as a mask layer, heat treatment is performed in an oxidizing atmosphere to open the opening 2 in the silicon polycrystalline layer 23.
SiO 2 film 2 is applied to the exposed surface at 7, 27' part.
Convert to 8,28'. Next, after removing the Si 3 N 4 film 26 used as the mask layer, the other area of the opening 22 except for the part where the base region is to be formed is covered with a resist film 29, and boron (B) is added by ion implantation. ) is introduced, and annealing is performed to form a p-type base region 30 and a substrate contact region 31.
本工程においてベース領域３０は横方向にも拡
散が進行するが、コレクタ領域２５より浅く形成
されているので横方向の拡がりはコレクタ領域の
それよりは小さい。また本実施例ではSiO2膜２
１の端部近傍のシリコン層を酸化することがない
ので、従来の製造方法の場合のようにバードビー
クを生じない。従つてSiO2膜２１の端部直下に
おいて接合３２，３３の形状が乱れることも、両
者が交叉することもない。 In this step, diffusion also progresses in the lateral direction in the base region 30, but since it is formed shallower than the collector region 25, the lateral spread is smaller than that of the collector region. In addition, in this example, the SiO 2 film 2
Since the silicon layer near the edge of the semiconductor device 1 is not oxidized, bird's beaks do not occur as in the case of conventional manufacturing methods. Therefore, the shapes of the junctions 32 and 33 are neither disturbed nor do they intersect directly under the edge of the SiO 2 film 21.
次いで同図ｆに示すようにレジスト膜２９を除
去した後、前記同図ｄ，ｅにおいて説明したのと
同様の方法を用いてベース領域３０内の所定の部
分にSiO2膜３４を形成し、次いでエミツタ領域
３５及びコレクタ・コンタクト領域３６を形成す
る。このあと図示はしていないが、アルミニウム
Alのような金属を残留せるシリコン多結晶層２
３上に選択的に被着せしめ、エミツタ、ベース、
コレクタ及び基板コンタクト電極を形成して、本
実施例による三重拡散型シリコン・バイポーラ半
導体装置が完成する。なお残留せるシリコン多結
晶層２３は上記説明及び図より明らかな如く、各
領域の境界部がSiO2膜に変換されているので、
シリコン多結晶層２３は上記SiO2膜２８，２
８′，３４によりそれぞれ他と分離され、各領域
上に独立して形成される。従つてこのシリコン多
結晶層２３により各領域間が短絡することはな
い。また本実施例ではSiO2膜２１上のシリコン
多結晶層２３を前記第３図ｄ及びｅに示す工程で
酸化したが、これは第３図ｆに示す工程で行なつ
てもよく、特に限定する必要はない。 Next, after removing the resist film 29 as shown in FIG. Next, an emitter region 35 and a collector contact region 36 are formed. Although not shown below, aluminum
Silicon polycrystalline layer 2 where metals such as Al can remain
3. selectively applied on the emitter, base,
A collector and a substrate contact electrode are formed to complete the triple diffusion type silicon bipolar semiconductor device according to this example. As is clear from the above explanation and diagram, the remaining silicon polycrystalline layer 23 has been converted into an SiO 2 film at the boundary between each region.
The silicon polycrystalline layer 23 is the SiO 2 film 28, 2
8' and 34, respectively, and are formed independently on each region. Therefore, this polycrystalline silicon layer 23 prevents short circuits between the regions. Furthermore, in this example, the silicon polycrystalline layer 23 on the SiO 2 film 21 was oxidized in the steps shown in FIG. 3 d and e, but this may also be done in the step shown in FIG. do not have to.
上述の本実施例ではシリコン基板１表面は全工
程を通して最初に形成したSiO2膜２１とシリコ
ン多結晶２３により被覆され、各領域の形成に際
しては上記SiO2膜２１とシリコン多結晶層２３
を酸化して形成したSiO2膜２８，３４とにより
各領域の位置を決定している。つまりSiO2膜２
１の開口２２パターンを基準として自己整合させ
るので、位置合せ余裕が不要となる。しかも
SiO2膜２１の端部直下にはバードビークを生じ
ないので従来のような接合形状の乱れを生じるこ
ともない。 In the present embodiment described above, the surface of the silicon substrate 1 is covered with the SiO 2 film 21 and the silicon polycrystalline layer 23 that are formed first throughout the entire process, and when forming each region, the SiO 2 film 21 and the silicon polycrystalline layer 23 are covered with the silicon substrate 1 surface.
The position of each region is determined by the SiO 2 films 28 and 34 formed by oxidizing. In other words, SiO 2 film 2
Since self-alignment is performed using the opening 22 pattern of No. 1 as a reference, no alignment margin is required. Moreover,
Since no bird's beak is generated directly under the edge of the SiO 2 film 21, the bonding shape is not disturbed as in the conventional case.
なお前記一実施例はnpnウオールドエミツタ構
造の半導体装置を製作する例を掲げて説明した
が、pnp型半導体装置を製作する場合には前述の
説明中ｎ型とｐ型をすべて反対にすればよく、ま
たウオールドエミツタ構造でない場合には、イオ
ン注入工程におけるレジスト膜よりなるマスク層
のパターンを適宜選択することにより各領域を任
意の位置に形成すればよい。加えて、半導体基板
上に形成される半導体層としては上述の実施例の
如き多結晶半導体層に限定されるものではなく、
非晶質半導体層であつてもよい。 The above embodiment has been explained using an example of manufacturing a semiconductor device with an npn wall emitter structure, but when manufacturing a pnp type semiconductor device, all n-type and p-type in the above explanation should be reversed. If the structure is not a wall emitter structure, each region may be formed at an arbitrary position by appropriately selecting a pattern of a mask layer made of a resist film in the ion implantation step. In addition, the semiconductor layer formed on the semiconductor substrate is not limited to the polycrystalline semiconductor layer as in the above embodiments.
It may be an amorphous semiconductor layer.
以上説明したごとく本発明により、制御性及び
再現性のよい三重拡散型の半導体装置の製造方法
が提供される。 As described above, the present invention provides a method for manufacturing a triple diffusion type semiconductor device with good controllability and reproducibility.
第１図は従来の半導体装置の製造方法の説明に
供するための要部断面図、第２図は第１図ａのＡ
部拡大断面図、第３図は本発明の一実施例を工程
の順に示す要部断面図である。
図において、１は一導電型を有する半導体基
板、２１は第１の絶縁膜、２２は開口、２３は半
導体多結晶層、２４，２９はレジスト膜、２５は
逆導電型領域、２６は第２の絶縁膜、２７，２
７′は開口、２８，２８′，３４は半導体酸化膜、
３０，３１は一導電型領域、３５，３６は逆導電
型領域を示す。
FIG. 1 is a sectional view of a main part for explaining a conventional method of manufacturing a semiconductor device, and FIG. 2 is an A in FIG. 1a.
FIG. 3 is a cross-sectional view of a main part showing an embodiment of the present invention in the order of steps. In the figure, 1 is a semiconductor substrate having one conductivity type, 21 is a first insulating film, 22 is an opening, 23 is a semiconductor polycrystalline layer, 24 and 29 are resist films, 25 is an opposite conductivity type region, and 26 is a second semiconductor substrate. insulating film, 27,2
7' is an opening, 28, 28', and 34 are semiconductor oxide films,
30 and 31 are regions of one conductivity type, and 35 and 36 are regions of opposite conductivity type.
Claims (1)
半導体基板表面が露出した第１の領域、および第
２の領域を各々画定する第１の絶縁膜を選択的に
形成する工程と、 該第１の絶縁膜表面、該第１の領域表面、およ
び該第２の領域表面を覆うように、半導体層を形
成する工程と、 該第１の領域表面に開口部を有し、かつ該第２
の領域表面を覆うように、該半導体層表面に、第
１のマスクを形成する工程と、 該第１のマスクを用いて、該第１の領域内に逆
導電型不純物を添加し、逆導電型不純物領域を形
成する工程と、 該第１の領域表面には選択的に開口を有して覆
うように、また該第２の領域表面を覆うように、
耐酸化性の第２の絶縁膜を該第１の領域および該
第２の領域の各々の表面に形成する工程と、 該第２の絶縁膜をマスク層として用い、該第２
の絶縁膜が形成されない該第１の領域表面にある
該半導体層を酸化膜に変換することによつて、該
第１の領域を第３の領域と第４の領域とに分離画
定する工程と、 該第２の絶縁膜を除去する工程と、 該第４の領域表面を覆い、該第２の領域表面お
よび該第３の領域表面に開口部を有する第２のマ
スクを形成する工程と、 該第２のマスクを用いて、該第２の領域内およ
び該第３の領域内に各々一導電型不純物を添加
し、該第２の領域内および該第３の領域内に前記
逆導電型不純物領域に比し浅い一導電型不純物領
域を形成する工程と を有する半導体装置の製造方法。[Claims] 1. A first insulating film is selectively formed on the surface of a semiconductor substrate having one conductivity type, each defining a first region and a second region where the surface of the semiconductor substrate is exposed. a step of forming a semiconductor layer so as to cover a surface of the first insulating film, a surface of the first region, and a surface of the second region; having an opening on the surface of the first region; , and the second
forming a first mask on the surface of the semiconductor layer so as to cover the surface of the region; using the first mask, doping an impurity of a reverse conductivity type into the first region; forming a type impurity region, selectively opening and covering the surface of the first region and covering the surface of the second region;
forming an oxidation-resistant second insulating film on each surface of the first region and the second region; using the second insulating film as a mask layer;
dividing the first region into a third region and a fourth region by converting the semiconductor layer on the surface of the first region where no insulating film is formed into an oxide film; , a step of removing the second insulating film, and a step of forming a second mask covering the surface of the fourth region and having openings on the surface of the second region and the surface of the third region, Using the second mask, impurities of one conductivity type are added into the second region and the third region, and impurities of the opposite conductivity type are added into the second region and the third region. A method for manufacturing a semiconductor device, comprising: forming an impurity region of one conductivity type that is shallower than the impurity region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6209281A JPS57176764A (en) | 1981-04-23 | 1981-04-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6209281A JPS57176764A (en) | 1981-04-23 | 1981-04-23 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57176764A JPS57176764A (en) | 1982-10-30 |
| JPH0371770B2 true JPH0371770B2 (en) | 1991-11-14 |
Family
ID=13190058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6209281A Granted JPS57176764A (en) | 1981-04-23 | 1981-04-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57176764A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164463A (en) * | 1986-12-26 | 1988-07-07 | Fujitsu Ltd | Manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5140866A (en) * | 1974-10-04 | 1976-04-06 | Nippon Electric Co | HANDOTA ISOCHI |
-
1981
- 1981-04-23 JP JP6209281A patent/JPS57176764A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5140866A (en) * | 1974-10-04 | 1976-04-06 | Nippon Electric Co | HANDOTA ISOCHI |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57176764A (en) | 1982-10-30 |
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