JP2800864B2 - Multilayer electronic components - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer electronic component, and more particularly to a power divider or a combiner comprising a combination of two or more transmission lines and a resistor.

[0002]

2. Description of the Related Art FIGS. 3A and 3B show a basic configuration of a power divider. The type shown in FIG.
The characteristic impedance of the transmission line 1 becomes Z ₀ , and the two branched transmission lines 2 and 3 each have a characteristic impedance as shown by the _equation 1, and the line length is １ ／ of the signal wavelength to be distributed or combined. Has become.

[0003]

(Equation 1)

In the type shown in FIG. 1B, the characteristic impedance of the transmission line 1 is as shown in Expression 2, and the two branched transmission lines 2 and 3 have the characteristic impedance of Expression 3 respectively.
, And the line length is １ ／ of the signal wavelength to be distributed or combined.

[0005]

(Equation 2)

[0006]

(Equation 3)

In each case, the transmission lines 2 and 3
A resistor R of 2Z ₀ is connected between the two, and the characteristic thereof is out 2
a and 3a are theoretically distributed and output by 3dβ, and the output 2a and 3a can theoretically have an isolation of −20dβ or less.

Conventionally, as shown in FIG. 4, a power divider using the above-described basic circuit has a single dielectric substrate 4.
On one plane of the dielectric substrate 4, the transmission lines 1 and
2 and 3 are formed by microstrip lines, and a resistor R is formed between the transmission lines 2a and 3a.
a, the outs 2a, 3a and the ground portion 5 were taken out by the pin terminals 6, 7, 8, and 9.

By using the in 1a and the out 2a, 3a of the transmission lines 1, 2, 3 in reverse, a combiner is obtained.

[0010]

In the conventional power divider as described above, since transmission lines 1, 2, and 3 having different characteristic impedances are formed on one dielectric substrate 4, only the line width is required. Impedance must be designed, and a wide line is required to realize a low-impedance transmission line. As a result, there is a problem that the wiring efficiency is deteriorated and the overall shape is enlarged.

Further, since the in and out and ground portions are taken out by pin terminals, there is a problem that it is difficult to carry out mounting using an automatic mounting machine.

Further, since the out portions of the transmission lines are close to each other, there is a problem that the isolation performance is deteriorated.

It is an object of the present invention to provide a multilayer electronic component which can greatly improve wiring efficiency, can be reduced in size and can be automatically mounted, and can improve isolation performance. I do.

[0014]

Means for Solving the Problems To solve the above problems,
Therefore, the present invention uses a line having a predetermined impedance on the surface.
A ceramic green sheet with a pattern and a
A set of ceramic green sheets with land patterns
Stacking multiple transmission line blocks consisting of
The laminate is fired to form a laminate, and a resistor is provided on the surface of the laminate.
The ground patterns of the transmission line blocks and
Side electrode with line pattern and resistor provided on the laminate
Is the one that adopts the configuration of conduction using via holes.
is there.

[0015]

[Function] By reducing the number of transmission line blocks to multiple layers,
It is possible to use a wide line for the transmission line.
There is no need to greatly improve wiring efficiency, and transmission lines
No C-coupling or M-coupling between them, resulting in isolation performance
Is improved. In addition, since the whole is formed into a chip by a laminated body and the transmission line and the ground pattern are taken out by the side electrode or the via hole, it becomes a surface mounting component, and the automatic mounting on the circuit board can be performed using an automatic mounting machine.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 3 is a block diagram of the power divider shown in FIG.
(A) and (b) in which both types of the basic configuration of the power divider are implemented, and transmission line blocks A, B, and
C corresponds to the transmission lines 1, 2, 3 in FIGS. 3 (a) and 3 (b).

Each of the transmission line blocks A, B, and C is a strip line composed of line patterns 11, 12, and 13 and each ground pattern 14, and the characteristic impedance thereof is the line width of the line patterns 11, 12, and 13. And the thickness between the line pattern and the ground pattern 14.

The line lengths of the line patterns 11, 12, and 13 in each of the transmission line blocks A, B, and C are as follows:
The length is の of the signal wavelength to be distributed or combined.

Next, a specific method of manufacturing the power divider will be described.

As shown in FIG. 1, ceramic green sheets 21, 22, 23 on which line patterns 11, 12, 13 are printed on one surface, and ground patterns 1 on one surface.
4 are prepared, a ceramic green sheet 25 for the surface layer block D, and a ceramic green sheet for a dummy as required.

Sheet 21 on which line pattern 11 is printed
Sheet 24 with ground pattern 14 printed above and below
24 and transmission line block A,
2 is a transmission line block B on which a sheet 24 on which the ground pattern 14 is printed is superimposed, and a transmission line block C on which a sheet 23 on which the line pattern 13 is printed and a sheet 24 on which the ground pattern 14 is printed are superimposed.
Are sequentially stacked, and a surface layer block D is further stacked thereon.

After brace-cutting the periphery of the above-mentioned stacked body, side electrodes 31, 32, 33, 3 are provided on both side surfaces.
4 and 31a, 32a, 33a, and 34a are formed by means such as printing, and then fired to form a chip-shaped laminate 26 as shown in FIG. Note that each side electrode may be formed after firing the laminate.

A power divider 27 is formed by forming a resistor R between the side electrodes 32 and 32a on both sides on the surface of the surface block D in the fired laminate 26.

[0025] The resistor R is formed using the printed resistor or chip resistor 2Z _0.

FIG. 2 shows the connection state of the power divider 27. The input end of the line pattern 11 is connected to the side electrode 3 for input.
1 and the output end is electrically connected to the intermediate side electrode 31a.

The input end of the line pattern 12 is electrically connected to the side electrode 31a, and the output end is electrically connected to one of the output side electrodes 32a.

The input end of the line pattern 13 is electrically connected to the intermediate side electrode 31a, and the output end is electrically connected to the other output side electrode 32.

Each of the ground patterns 14 is a lead portion provided on both sides thereof, and the side electrodes 3 on both sides serving as grounds.
3, 34 and 33a, 34a, and the surface layer block D
The upper resistor R is connected to the side electrodes 32 and 32a for output on both sides.
To be connected between the output terminals of the line patterns 12 and 13. Note that the number of lead portions of each ground pattern is not limited to four as shown in the figure, and may be one or more.

As shown in FIG. 1, the power divider 27 is a chip type in which each transmission path block is multilayered, and the input / output and ground are taken out through side electrodes.
It becomes a surface mount component and can be used for mounting automation.

In the case of the drawing, the input / output and the ground are taken out by the side electrodes. However, the use of a via hole is also effective, and the power divider 27 uses its input and output in reverse. As described above, it becomes a combiner.

[0032]

As described above, according to the present invention, since a plurality of transmission line blocks are multilayered to form a power divider or a combiner, a chip type can be realized, and the size can be reduced. Since the extraction is performed by the side surface electrode or the via hole, it becomes a surface mounting component, and automatic mounting becomes possible.

In addition, since the transmission line block has a multilayer structure, the line pattern can be adjusted not only by the line width but also by the thickness, so that a wide line is not required and the wiring efficiency can be greatly improved. .

Further, since each line pattern is formed by a strip line and is multi-layered with a ground pattern interposed therebetween, it is possible to suppress the penetration of noise from the surroundings by the ground pattern, and the C coupling and the M coupling between the line patterns are reduced. Since this does not occur and a sufficient out or in distance of the line pattern can be ensured, the isolation performance is improved.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view showing a configuration of a multilayer electronic component according to the present invention.

FIG. 2 is a plan view of the above.

FIGS. 3A and 3B are explanatory diagrams of different types showing a basic configuration of a power divider. FIGS.

FIG. 4 is a front view showing a conventional power divider.

[Explanation of symbols]

11, 12, 13 Line pattern 14 Ground pattern 21, 22, 23, 24, 25 Ceramic green sheet 27 Power divider 31, 32, 33, 34 Side electrode 31a, 32a, 33a, 34a Side electrode A, B, C Transmission line Block D Surface block R Resistance

Claims (1)

(57) [Claims] Claims: 1. As a power divider or combiner
In the laminated electronic component to be used , a plurality of transmission line blocks each composed of a combination of a ceramic green sheet provided with a line pattern having a predetermined impedance on the surface and a ceramic green sheet provided with a ground pattern on the surface are stacked, fired and stacked. A body is formed, a resistor is provided on a surface layer of the laminated body, and the ground pattern of each of the transmission path blocks and the line pattern and the resistance are conducted by using side electrodes or via holes provided in the laminated body. Laminated electronic components.