JP2797820B2 - Reference voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit used for generating a reference voltage in a constant voltage circuit, and more particularly to a reference voltage generating circuit suitable for a CMOS integrated circuit.

[0002]

2. Description of the Related Art As is well known, a conventional reference voltage generating circuit is a Widlar transistor composed of bipolar transistors.
Bandgap reference circuits are common and M
No practical reference voltage generation circuit composed of only OS transistors is known. That is, enhancement MOS
An example of an NMOS reference voltage generation circuit utilizing the difference between the threshold voltages of the transistor and the depletion MOS transistor was published in a paper (1978, ISSCC, paper number WAM3.5). I can't get it.

[0003]

However, MOS transistors also have various advantages, and it is desired to develop a reference voltage generation circuit that can be realized on a CMOS integrated circuit. At this time, it should be noted that the temperature characteristics must be good, but the MOS transistor has a large manufacturing deviation,
Further, since the temperature characteristics are not linear but curved like bipolar, how to control these characteristics becomes a problem.

An object of the present invention is to provide a reference voltage generating circuit having a structure suitable for realizing a CMOS integrated circuit and having good temperature characteristics .

[0005]

In order to achieve the above object, a reference voltage generating circuit according to the present invention has the following configuration. That is, the reference voltage generation circuit of the first invention has a gate width W
: K ₁ is the capability ratio expressed by the ratio W / L of the gate length L
And the ability ratio and two MOS transistors having different;
Said two MOS ratio of different current values, respectively of the transistor K _2: the two MOS transistors to be driven by a
The motor and Karen <br/> Tomira circuit with two MOS transistors of the opposite polarity; includes a reference to the CMOS integrated circuit
A CMOS type reference voltage generating circuit for generating a voltage.
Thus , between the two MOS transistors, the drain of one transistor and the gate of the other transistor are connected in common;
A gate is connected to one current output terminal of the current mirror circuit via a first resistor or directly, and a drain is
Connected to the first resistor or the one current output terminal
That the second through the resistor connected to the gate; the other transistor, a drain connected to the other current output terminal of said current mirror circuit, a source Ru grounded directly
With the gate connected to the drain of the one transistor.
An output terminal is provided at a connection end between the first resistor and the current mirror circuit or at a connection end between the gate of one transistor and the current mirror circuit.

A reference voltage generating circuit according to a second aspect of the present invention is the reference voltage generating circuit according to the first aspect of the present invention; wherein the one transistor has the drain directly connected to the gate by removing the first and second resistors. The other transistor is interposed in such a manner that the source transfers the second resistor.
Grounded through a third resistor.

A reference voltage generation circuit according to a third invention is the reference voltage generation circuit according to the first invention or the second invention; wherein the output terminal is connected to a drain of the one transistor. Provided on a gate;

According to a fourth aspect of the present invention, in the reference voltage generating circuit according to the first aspect of the present invention, the output terminal is provided at a middle point of the second resistor.

A reference voltage generation circuit according to a fifth invention is the reference voltage generation circuit according to the first invention or the second invention; wherein the other transistor has a drain connected to the other end of the current mirror circuit via a fourth resistor. The output terminal is provided at the drain of the other transistor.

[0010]

Next, the operation of the reference voltage generating circuit of the present invention configured as described above will be described. In the present invention, the performance ratios are different, that is, expressed by the ratio W / L of the gate width W and the gate length L.
The ability ratio of the 1: 2 one MOS transistor as K ₁ at different gate-source voltage (MOS FET)
Are respectively opposite in polarity to these MOS transistors.
Of two MOS transistors having a current ratio of K ₂ : 1
Output of different current values of one and the other of the current mirror circuit
Drive with current . As a result, the temperature characteristic of the mobility and the temperature characteristic of the threshold voltage can be canceled each other, and the temperature characteristic of the output reference voltage can be improved.

Therefore, according to the present invention, it is possible to provide a reference voltage generating circuit having a configuration suitable for being realized on a CMOS integrated circuit.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a reference voltage generating circuit according to a first embodiment of the present invention. In FIG. 1, this reference voltage generation circuit
It is basically composed of two n-channel MOS transistors (M1, M2) provided on the ground side and two p-channel MOS transistors (M3, M4) provided on the DC power supply _VDD side. That is, it has a CMOS configuration.

[0013] M1 and M2, capacity ratio (gate width / gate length) is, M1: M2 = 1: a K _1. The drain of M1 and the gate of M2 are commonly connected. And M1 is
The source is directly grounded, the gate is connected to the source of M3 via a (first) resistor R1, and the drain is (second)
It is connected to the resistor R1 via the resistor R2. That is, the gate and the drain are connected via the resistor R2, and the drain is a current mirror via the series circuit of the resistor R2 and the resistor R1.
It is connected to the source of M3 , one of the current output terminals of the circuit . In M2, the source is directly grounded, and the drain is
It is connected to the source of M4, which is the other power output terminal of the current mirror circuit .

Next, M3 and M4 are expressed by the current value of the output current.
The capacity ratio that appears is M3: M4 = K ₂ : 1. In both cases, the drains are commonly connected to the DC power supply _VDD , and the gates are commonly connected. In M4, the gate and the source are directly connected. In short, M3 and M4 constitute a well-known current mirror circuit, and M1 and M2 have a current ratio of K ₂ : 1.
Is driven.

In FIG. 1, the resistor R1 can be omitted. At this time, the gate of M1 is directly connected to the source of M3. Therefore, the output terminal of the output voltage of the reference voltage generating circuit is connected to the resistor R1 when there is the resistor R1.
Provided at the connection end of the resistor M1 and the source of the resistor M3 (shown as V _REF ). When there is no resistor R1, provided at the connection end of the resistor R2 and the source of the resistor M3, that is, at the gate of the transistor M1 (shown as V _REF1 ). ). In the configuration of FIG. 1 or the configuration in which the resistor R1 is omitted, an output terminal can be provided to the gate of M2 (shown as V _REF2 ).

In the configuration of FIG. 1, the resistor R1 may or may not be omitted. However, the configuration in which the resistor R2 is moved between the source of M2 and the ground, that is, as shown in FIG. The gate and the drain may be directly connected, and the source of M2 may be grounded via the (third) resistor R2. FIG.
Here, the resistor R1 is omitted.

Further, as a method of providing the output terminal, in the configuration of FIG. 1, the resistor R1 may or may not be omitted, but it can be provided at the middle point of the resistor pattern of the resistor R2. 3 example is a configuration in which interchanging the p-channel and n-channel, and the resistor R2 _A resistor R2 _B resistance R
2 divided into two, and an output terminal is provided at the midpoint (V
_REF3 ).

In the configuration of FIG. 1, the resistor R1 may or may not be omitted, but the drain of M2 is connected to the source of M4 via a (fourth) resistor, and the fourth resistor is connected to the source of M4. An output terminal can be provided at the connection end between the transistor and the source of M4. For example, FIG. 4 shows a configuration in which the p-channel and the n-channel are interchanged, but an output terminal is provided at the connection end between the (fourth) resistor R4 and the source of M4 (shown as V _REF4 ).

The operation will be described below with reference to FIG. M
_Assuming that the difference voltage between the gate-source voltage V _{GS1 of} No. 1 and the gate-source voltage V _{GS2 of} M2 is ΔV _GS , the output reference voltage V _REF can be expressed by Expression 1.

[0020]

(Equation 1)

The drain current I ₁ of M ₁ and the drain current I _{2 of} M ₂ are equal to M 3 and M 4 forming a current mirror circuit.
The ratio of the capacity ratio: determined by (K ₂ 1), is a I ₁ = K ₂ I _2, the drain current I ₁ of M1 has a gate-source voltage V _GS1 of the threshold voltage V _THN and conductance beta _N The drain current I of M2
₂ is expressed as Equation 3 using the conductance K ₁ beta _N and gate-source voltage V _GS2 and the threshold voltage V _THN. Note that the conductance β _N is the mobility μ
Equation 4 is expressed using _N , the gate oxide film capacitance C _OX per unit area, the gate width W, and the gate length L.

[0022]

(Equation 2)

[0023]

(Equation 3)

[0024]

(Equation 4)

Accordingly, the differential voltage ΔV _GS is given by equation (5), and when this is rearranged, equation (6) is obtained. Since I ₁ ≠ 0 in operation, the drain current I ₁ is finally obtained by equation (7).

[0026]

(Equation 5)

[0027]

(Equation 6)

[0028]

(Equation 7)

Then, V _GS1 obtained from Expression 2 and Expression
Using ΔV _{GS of} 5 and √I ₁ obtained from Equation 7
When V _REF of Expression 1 is obtained by using Expression 1 , the output reference voltage V _REF is expressed by Expression 8.

[0030]

(Equation 8)

Here, the temperature characteristics of the output reference voltage V _REF will be examined. In the SPICE model, the conductance β _N
Is expressed by Expression 9 and mobility μ _N is expressed by Expression 10. In Equations 9 and 10, β _N0 and μ _N0 represent the values of β _N and μ _N at T = T ₀ .

[0032]

(Equation 9)

[0033]

(Equation 10)

Therefore, 1 / β _N is expressed by the following equation (11).
The temperature characteristic of 1 / β _N when T ₀ = 300 ° K is 5,
000 ppm / deg.

[0035]

[Equation 11]

On the other hand, the threshold voltage V _THN is given by
2 is modeled in the literature "MOS Integrated Circuits
Theory, Fabrication, Design, and Systems Application
sof MOS LSI '' (WMPenney and L. Lau, VAN NOSTR
According to AND COMPANY), α in Equation 12 is α =
-4mV / deg (standard V _THN process), α = -2.7mV
/ Deg (low V _THN process).

[0037]

(Equation 12)

Therefore, when Equations 11 and 12 are substituted into Equation 8, the output reference voltage V _REF becomes Equation 13, and when this is differentiated with respect to the temperature T using T and R as variables , Equation 14 is obtained, and the room temperature T ₀ = Output reference voltage V at 300 ° K
The temperature coefficient of the _{REF (fractionaltemperature} coefficient)
TC _F (V _REF ) can be expressed by Expression 15. In Equation 15, V _REF0 is the value of V _REF at T = T ₀ = 300 ° K. Note that, as described above, in Expression 15 starting from Expression 13,
The derivation is described in detail below in paragraph number [0063].
I do.

[0039]

(Equation 13)

[0040]

[Equation 14]

[0041]

(Equation 15)

[0042] Therefore, as the TC _F (V _REF) = 0 Temperature characteristics
In order to improve the expression, the expression 15 needs to be the expression 16 from the expression 15.

[0043]

(Equation 16)

For example, V _THN0 = 0.8 V, α = 2.7 m
V / deg, TC _F (R) = 600 ppm / deg, TC
_The reference output voltage V _{REF0 at} which _F (V _REF ) = 0 is _given by the following equation 1.
It looks like 7.

[0045]

[Equation 17]

Next, equation 7 holds even if R1 = 0. In this case, V _REF1 in FIG. 1 becomes the output reference voltage, which is V _REF = V _GS1 from Equation 1 , and
2 to V _GS1 I _1, expressed in beta _N and V _THN, it
Equation 18 is obtained using I ₁ obtained from Equation 5, and is equal to the case where R1 = 0 in Equation 8.

[0047]

(Equation 18)

By substituting equations (11) and (12) into equation (18), V _REF1 becomes equation (19).
It becomes 0. That is, Equation 19 replaces R ₁ in Equation 14 with:
In this case, Equations 15 and 16 can be applied, and the value represented by Equation 17 is obtained.

[0049]

[Equation 19]

[0050]

(Equation 20)

If a reference voltage is taken out from the gate of M2, V _REF2 = V _GS2 Is the output reference voltage,
This is obtained by _adding I ₁ = K ₂ I ₂ to V _GS2 obtained from equation (3).
Equation 21 is obtained using the relationship with Equation 5 .

[0052]

(Equation 21)

Then, when this Expression 21 and Expression 18 are compared, Expression 22 is established, so that the output reference voltage V _REF2 is expressed by Expression 2
It becomes 3.

[0054]

(Equation 22)

[0055]

(Equation 23)

From equation (23), when TC _F (V _REF1 ) = 0, V obtained by taking the differential coefficient of equation (23 )
The temperature coefficient of the _REF2 TC _F (V _REF2), settings such as K _1, K ₂
In TC _F (V _REF2) <0 and Ru can be set der. Similarly, TC
When the _F (V _REF1)> 0 can be set with the _{TC F (V REF2) <0} .

Therefore, _assuming that the intermediate voltage of the resistor R2 is the output reference voltage V _REF3 , TC
_F (V _REF3 ) = 0 and TC _F (V _REF1 )> 0, TC
_F (V _REF2 ) <0 can be set, and a voltage having a positive, negative, or zero temperature characteristic can be obtained. Here, V _REF1 > V _REF3 > V _REF2 where K ₁ > 1 and K ₂ > 1. FIG. 3 shows a MOS transistor.
Transistors M1 and M2 are p-channel MOS transistors
And MOS transistors M3 and M4 are n-channel
M1 and M2 are connected to the DC power supply V _DD as S transistors ,
M3 and M4 are arranged on the ground side and R1 is eliminated.
This is an example.

Further, as shown in FIG. 4, a fourth resistor R4
Connected to the other current output terminal of the current mirror circuit via
Output terminal (output reference voltage V _REF4 ) to the drain of M2
Is set, the drain current I ₂ is obtained according to Equation 7.
The output reference voltage V _REF4 becomes V _REF4 =
V _GS4 + R ₄ I _2, which is shown based on Equation 3.
V _GS4 obtained from I ₂ = K ₂ β _N (V _GS4 −V _THN ) ²
If, the equation 25 by using the I ₂ determined from Equation 24. Here, β _P is the capacitor of the n-channel MOS transistor.
P-channel MOS transistor expressed in accordance with the conductance
It expresses the conductance of the resistor.

[0059]

(Equation 24)

[0060]

(Equation 25)

Therefore, the output reference voltage V _REF4 can be set to TC _F (V _REF4 ) = 0.

Next, FIG. 5 shows a SPICE simulation result. When V _DD > 2.5V, the output reference voltage V _REF
It can be understood that the temperature characteristic of is almost zero.
Note that K ₁ = 1, K ₂ = 2, R1 = 3KΩ, R2 = 4K
Ω, TC _F (R) = 600 ppm / deg, W / L = 50 μm
/ 5 μm and oxide film thickness t _OX = 280 Å.

It should be noted that the derivation of Equation 15 described above and Equation 1
The features shown in FIG. 5 will be described in detail below. Immediately
By substituting T ₀ into T in Equation 13, the following Equation 26 is obtained.
Can be

[0064]

(Equation 26)

[0065] Therefore, V _REF0 -V _THN0 Equation 27
Indicated by

[0066]

[Equation 27]

[0067] T of Expression 14 is given by T = T ₀  Then the next number
Equation 28 is obtained.

[0068]

[Equation 28]

[0069] Substituting Equations 27 and 28 into Equation 15 gives
The following equation 29 is obtained.

[0070]

(Equation 29)

[0071] T ₀  = 300 ° K, 1 / T ₀  Is 3,33
3.33 ... × 10 ^-6 And therefore 3 / 2T ₀  Is 5,0
00 ppm and the resistance R _Two  Temperature coefficient TC _F (R _Two )
Is a primary characteristic (linear), 1 / R _Two  × dR _Two
/ DT = TC _F (R _Two ), And substitute these into Equation 29.
Equation 15 is obtained by the following equation. The resistance R ₁ , R _Two  Are both
Since they are formed on an integrated circuit, the temperature coefficients are equal, ie, T
C _F (R ₁ ) = TC _F (R _Two ) = TC _F (R)
You.

[0072] Further, the output group of at room temperature T ₀ = 300 ° K
Temperature coefficient of the reference voltage V _REF TC _F (V _REF), the unit voltage per
_Derivative of V _REF at T = T ₀ with respect to temperature It can be expressed as

[0073] The output reference voltage V shown in Expression 15 _REF  Temperature
Coefficient TC _F (V _REF ) Is V _REF0 , Ie T = T ₀  = 300 °
V in K _REF  Is a function of the value of _REF0 Itself
Is, for example, T = T in Expression 13. ₀  And K
₁  , K _Two  And R ₁  , R _Two  Is specified.

[0074] Thus, the reference voltage V _REF  Temperature clerk
Number TC _F (V _REF ) Shows a reference voltage generation circuit having a CMOS configuration.
The capacity ratio of two MOS transistors to be formed is 1: K ₁  Passing
MOS transistors forming a current mirror circuit
Star current ratio K _Two  : 1, and the configuration of the reference voltage generation circuit
Element resistance R ₁  And R _Two  Will be determined by
You.

[0075]

【The invention's effect】 As described above, the reference voltage of the present invention
According to the generation circuit, the capability ratio is different, that is,
Of two MOS transistors having different source-to-source voltages.
Each is driven by a different current value.
Temperature characteristics of threshold voltage and temperature characteristics of threshold voltage.
Can cancel each other, and the temperature characteristics of the output reference voltage
Can be good. Therefore, according to the present invention, CMOS integration
A reference voltage generation circuit with a configuration suitable for realizing on a circuit
There are effects that can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a reference voltage generating circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a reference voltage generation circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a reference voltage generation circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a reference voltage generation circuit according to a fourth embodiment of the present invention.

FIG. 5 is a temperature characteristic diagram (SPICE simulation diagram) of an output reference voltage.

[Explanation of symbols]

K ₁ capacity ratio was K ₂ the ability ratio M1 to M4 MOS transistor R1~R4 resistor R2 _A resistor R2 a 2-minute resistance R2 _B resistance R2 to 2 minutes resistance V _DD DC power source V _REF output reference voltage V _REF1 output reference voltage V _REF2 output reference voltage V _REF3 output reference voltage V _REF4 output reference voltage

Claims (5)

(57) [Claims] 1. The ratio of the gate width W to the gate length L, W / L,
The ability ratio to express 1: K ₁ and to the ability ratio and two MOS transistors having different is; ratio K of each different current value of the two MOS transistors _2: before driving in 1
Two MOS transistors with opposite polarities to the two MOS transistors
Comprise; a current mirror circuit of the transistors
CMOS format for generating a reference voltage on a CMOS integrated circuit
A reference voltage generation circuit of, in the mutual two MOS transistors with the gate of the drain and the other transistor of the one transistor are connected in common;
One transistor has a gate connected to one current output terminal of the current mirror circuit via a first resistor or directly, and a drain connected to the first resistor or the first resistor.
Is connected to the gate via a second resistor to be connected to the one current output; the other transistor, a drain connected to the other current output terminal of said current mirror circuit, the source is grounded directly Rutotomoni The gate is the gate of the one transistor.
Is connected to the rain; is provided with output terminals in the connection end between the gate and the current mirror circuit connection end or one transistor of said first resistor and said current mirror circuit; that a reference voltage generator, wherein circuit. 2. The reference voltage generating circuit according to claim 1, wherein the one transistor includes the first and second transistors .
The drain is directly connected to the gate by removing the resistance of the second transistor;
Via a third resistor interposed in the form of relocating the resistor
A reference voltage generating circuit, which is grounded ; 3. The reference voltage generating circuit according to claim 1, wherein the output terminal is connected to the one of the first and second transformers.
A reference voltage generating circuit provided at a gate of the other transistor connected to a drain of the transistor. 4. The reference voltage generating circuit according to claim 1, wherein the output terminal is provided at a middle point of the second resistor. 5. The reference voltage generating circuit according to claim 1, wherein the other transistor has a drain connected to the other current output terminal of the current mirror circuit via a fourth resistor; The reference voltage generating circuit, wherein the output terminal is provided at a drain of the other transistor.