JP2001255950A - Bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the influence of substrate effect. SOLUTION: In a current mirror circuit 1, the drain and gate of a pMOS transistor 14 are short-circuited, and the gates of pMOS transistors 13 and 14 are connected to each other, and the both sources are connected to a power source VDD. One terminal of a resistor 15 is connected to the drain of the pMOS transistor 13 and the gate of an nMOS transistor 11, and the other material of the resistor 15 is connected to the drain of the nMOS transistor 11, and the source of the nMOS transistor 11 is connected to ground VSS. The drain of an nMOS transistor 12 is connected to the drain of the nMOS transistor 14, and the source of the nMOS transistor 12 is connected to the ground, and the gate of the nMOS transistor 12 is connected to the drain of the nMOS transistor 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit.

[0002]

2. Description of the Related Art A conventional bias circuit is shown in FIG.
Things are known. pMOS transistors 33, 3
4 by the current mirror circuit composed of nMOS transistors.
The resistors 31, 32 are designed so that the ratio of the drain current becomes constant.
Is controlled. Gate of nMOS transistor 32
Has a voltage V_GS2Is applied. Voltage V_GS2Is nMO
Gate bias voltage V of S transistor 31_GS1And
It is equal to the sum of the voltages between the resistors of the anti-35. Current between resistors 35
The voltage is the drain current I of the nMOS transistor 31.
_DS1And the resistance 35.

[0003]

However, this is not the case.
Circuit constructed on P-type silicon substrate
In this case, the nMOS
The source voltage of the transistor 31 is an nMOS transistor
32, unlike the nMOS transistor 31
Threshold V_t1Is affected by the substrate effect and the nMOS transistor
The threshold V of the star 32 _t2And a difference may occur.

For this reason, in low power supply voltage applications where it is required to keep the bias voltage VGS2 low, nMO
There is a problem in that the variation in the conductance _gm2 of the S transistor 32 with respect to the process variation and the temperature variation increases.

An object of the present invention is to solve the above-mentioned problems and to provide a bias circuit which is not affected by the body effect.

[0006]

According to a first aspect of the present invention, there is provided a current mirror circuit, one terminal of a resistor and a first nMOS.
The drain of the transistor is connected in series, and the other terminal of the resistor is connected to the gate of the first nMOS transistor. One current from the current mirror circuit is used as a drain current, and the drain voltage is used as a main bias. A circuit as an output of the circuit, and a second nMOS transistor in which the other current from the current mirror circuit is used as a drain current and a drain voltage of the first nMOS transistor is applied to a gate. .

According to a second aspect of the present invention, one terminal of the resistor and the drain of the first pMOS transistor are connected in series, and the other terminal of the resistor is connected to the first pMOS transistor.
A second transistor connected to the gate of the transistor and having a drain voltage as an output of the bias circuit; and a second pMOS transistor, the gate of which is connected to the first pMOS transistor.
Second pMOS to which a drain voltage of a transistor is applied
A transistor and a current mirror circuit that uses the drain current of the first pMOS transistor as one current and the drain current of the second pMOS transistor as the other current.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. <First Embodiment> FIG. 1 shows a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a current mirror circuit which short-circuits the drain and gate of a pMOS transistor 14 and connects the gates of pMOS transistors 13 and 14 to each other.
Sources 3 and 14 are both connected to the power supply _VDD .

Reference numeral 15 denotes a resistor, and 11 denotes an nMOS transistor. One terminal of the resistor 15 is connected to the drain of the pMOS transistor 13 and the gate of the nMOS transistor 11, and the other terminal of the resistor 15 is connected to the nMOS transistor 11. It is connected to the drain, and the source of the nMOS transistor 11 is connected to the ground ( _VSS ).

Reference numeral 12 denotes an nMOS transistor, the drain of which is connected to the drain of the pMOS transistor 14, the source of which is connected to ground, and the gate of which is nM.
It is connected to the drain of the OS transistor 11.

[0011] nMOS transistors 11 and 12, operating at different gate bias voltages V _{GS 1,} V _GS2 respectively. The reason why the nMOS transistors 11 and 12 have different gate bias voltages is that the nMOS transistors 11 and 12
12 is changed or the mirror ratio of the currents I _DS1 and I _DS2 from the current mirror circuit 1 is changed.

_Assuming that the current I _DS1 and the current I _DS2 have a current mirror ratio of 1: N, the current I _DS1 and the current I _DS2
The relationship is

[0013]

[Expression 1] I _DS1 × N = I _DS2 (1)

Assuming that the resistance value of the resistor 15 is R, the current I
_DS1 and I _DS2 , between the voltages V _GS1 and _VGS2 ,

[0015]

[Formula 2] _{I DS1 = (V GS1 -V GS2} ) / R ... (2) I DS1 = β 1 × (V GS1 -V t1) 2/2 ... (3) I DS2 = β 2 × (V GS2 - V _t2) the relationship of the ^2/2 (4) is satisfied.

Here, β ₁ and β ₂ are the MOS transistor gain coefficients of the nMOS transistors 11 and 12, where μ is the inversion layer mobility, C is the gate unit area capacitance, and nM
Assuming that the vertical and horizontal size ratios of the OS transistors 11 and 12 are W ₁ / L ₁ and W ₂ / L ₂ respectively,

[0017]

Equation 3 can be expressed as β ₁ = μCW ₁ / L ₁ β ₂ = μCW ₂ / L ₂ .

The transfer conductance g _m2 of the nMOS transistor 12 is

[0019]

[Expression 4] g _m2 = β ₂ × (V _GS2 −V _t2 ) (5) is obtained by substituting Expressions (1) to (4) into Expression (5).

[0020]

(Equation 5)

## EQU2 ##

Here, the nMOS transistors 11 and 12
Since the source voltages are equal, the respective thresholds V _t1 and V _t2 are equal, and

[0023]

V _t1 −V _t2 = 0 (7)

Therefore, from equations (6) and (7), the transfer conductance g _m2 is

[0025]

Equation 7

## EQU2 ##

From equation (8), the transfer conductance g
It can be seen that _m2 is not affected by the process variation and temperature change of the MOS transistor. <Second Embodiment> FIG. 2 shows a second embodiment of the present invention. The bias circuit according to the present embodiment is different from the first embodiment in that the pMOS transistor is replaced with the nMOS transistor s and the nMOS transistor is replaced with pMO.
Was replaced with S transistor, together with to replace the power supply VDD and the ground (V _SS), it was substituted for ground and power supply V _DD.

That is, the current mirror circuit 2 has nM
The drain and gate of the OS transistor 24 are short-circuited, and the gates of the nMOS transistors 23 and 24 are connected.
Are connected to the ground ( _VSS ).

One terminal of the resistor 25 is connected to the drain of the nMOS transistor 23 and the gate of the pMOS transistor 21, and the other terminal of the resistor 25 is connected to the pMOS transistor 23.
Connected to the drain of transistor 21
The source of the transistor 21 is connected to the power supply _VDD .

The pMOS transistor 22 has a drain of n
The drain is connected to the drain of the MOS transistor 24, the source is connected to the power supply V _DD , and the gate is connected to the drain of the pMOS transistor 21.

Since the bias circuit of the present embodiment is configured as described above, it performs essentially the same operation as the bias circuit of the first embodiment. Therefore, the transfer conductance g _m2 of the pMOS transistor 22 is It is not affected by the process variation and temperature change of the MOS transistor.

[0032]

As described above, according to the present invention,
With the above configuration, it is not affected by the substrate effect.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example of a bias circuit.

[Explanation of symbols]

 1, 2, current mirror circuit 11, 12, 21, 22 nMOS transistor 13, 14, 23, 24 pMOS transistor 15, 25 resistance

Continued on front page F term (reference) 5H420 NA27 NB02 NB22 NB25 NC02 NE23 5J090 AA01 AA43 AA58 CA02 CA14 CN01 FA16 HA10 HA16 HA25 KA09 MA21 5J091 AA01 AA43 AA58 CA02 CA14 FA16 HA10 HA16 HA25 KA09 MA21

Claims (2)

[Claims] 1. A current mirror circuit, comprising: connecting one terminal of a resistor and a drain of a first nMOS transistor in series, and connecting the other terminal of the resistor to a gate of the first nMOS transistor. A circuit using one current from the current mirror circuit as a drain current and using the drain voltage as an output of the bias circuit; and using the other current from the current mirror circuit as a drain current and a gate as the first nMOS transistor. And a second nMOS transistor to which a drain voltage is applied. 2. The method according to claim 1, wherein one terminal of the resistor is connected in series to the drain of the first pMOS transistor, and the other terminal of the resistor is connected to the gate of the first pMOS transistor. A circuit serving as an output of the bias circuit; a second pMOS transistor having a gate to which a drain voltage of the first pMOS transistor is applied; and a drain current of the first pMOS transistor. A current mirror circuit that uses one of the currents and uses the drain current of the second pMOS transistor as the other current.