JP2785557B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a self-aligned contact hole having a smooth side wall surface.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIG.
P-type Si substrate 30 on which functional elements such as transistors are formed
A 200 nm (nanometer) -thick SiO ₂ is deposited on 1 by LPCVD to form a first insulating layer 304, followed by a 400 nm-thick BPSG deposited by LPCVD and flowed by heat treatment to form a second insulating layer 305. I do. Then, after forming a contact hole in a predetermined position, the WSix by sputtering to 200nm is deposited, and a second conductive layer 307 is patterned into a desired shape, by depositing a SiO ₂ of 200nm by CVD, the 3 insulating layers 30
6 is assumed. Further, a BP of 500 nm is formed by LPCVD.
SG is deposited, heat-treated and flowed to form a fourth insulating layer 3
08.

Next, the photoresist is patterned into a desired shape, a part of the fourth insulating layer 308 is removed with a hydrofluoric acid-based etchant using the photoresist as a mask, and then anisotropic dry etching is performed. The remaining fourth insulating layer 308, third insulating layer 306, and second insulating layer 3
05, the first insulating layer 304 is continuously etched to form a contact hole.

Further, 100 nm of SiO ₂ is deposited by LPCVD, and the bottom of the contact hole is exposed by anisotropic dry etching, and etching is performed until SiO ₂ remains on the side wall of the contact hole.
The fifth insulating layer 309 is formed. Next, aluminum is deposited to a thickness of 1 μm by a sputtering method and patterned into a desired shape to obtain the structure of FIG. 3 as the third conductive layer 310.

[0005]

As described above, according to the conventional technique, a contact hole is opened through an inter-wiring insulating layer in which a plurality of insulating layers are stacked, and SiO ₂ is deposited by an LPCVD method. Since SiO ₂ is left on the side wall surface of the contact hole by anisotropic dry etching, aluminum must be deposited by the next sputtering method in a state where the unevenness on the side wall surface of the contact hole remains, and There is a problem that the aluminum is disconnected.

[0006] It is very difficult to stably prevent the occurrence of irregularities on the side wall surface of a contact hole penetrating an inter-wiring insulating layer in which a plurality of insulating layers are stacked. After the opening of the contact hole, when performing a wet surface treatment, unevenness occurs due to the difference in the etching rate of each of the laminated insulating layers. It greatly varies depending on the composition of the insulating layer and the film forming conditions of each insulating layer.

[0007] For example, in FIG.
And the third insulating layer 306 is made of SiO ₂ ,
And when the fourth insulating layer 308 is BPSG, SiO ₂ tends to be a convex portion for an ammonia-based solution, and BPSG tends to be a convex portion for a hydrofluoric acid-based solution. The degree of unevenness greatly depends on the boron concentration and the phosphorus concentration of BPSG.
It is inevitable that irregularities of about 0 to 30 nm remain.

[0008]

According to a method of manufacturing a semiconductor device of the present invention, an insulating layer made of SiO ₂ to which impurities are added is formed.
A plurality of insulating layers including stacked, uppermost is doped
Forming an insulating layer between wirings as a first insulating layer made of SiO ₂
Forming the first insulating layer with a hydrofluoric acid-based etching solution.
By etching the film thickness above the edge layer
Is etched into a bowl shape, followed by anisotropic drying.
Etching to form the first insulation under the bowl shape
The contact hole reaching the substrate through the remaining film thickness portion of the layer and another insulating layer located thereunder is cut off from the wiring.
Step of opening to the edge layer , the upper part is the bowl shape
Depositing a second insulating layer made of SiO ₂ added with impurities on the entire surface including the side wall surface and the bottom surface of the contact hole are, the surface of the second insulating layer by heat treatment
And the bowl of the first insulating layer at the same time.
Steps to make the shape smooth without corners, and then
Etching the second insulating layer until the bottom surface of the contact hole is exposed by isotropic dry etching .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are longitudinal sectional views of an embodiment of the present invention in the order of manufacturing steps.

[0011] n ⁺ formed with a functional element such as a transistor
It has a layer 103. LPCVD on P-type Si substrate 101
A 200-nm-thick SiO ₂ is deposited by a method to form a first insulating layer 104 covering the first conductive layer 102. Subsequently, BPSG having a thickness of 400 nm is deposited by the LPCVD method, heat-treated, and allowed to flow to form the second insulating layer 105. Next, a contact hole is opened at a predetermined position,
A second conductive layer 107 is formed by depositing 200 nm of WSix by a sputtering method and patterning it into a desired shape. Next, a 200 nm-thick SiO ₂ and a 500 nm-thick BPSG are deposited by LPCVD, heat-treated and flown, and a third layer covering the second conductive layer 107 is formed.
The insulating layer 106 and the fourth insulating layer 108 are used.

Next, the photoresist is patterned into a desired shape, and a part of the BPSG (the fourth insulating layer 108) is etched with a hydrofluoric acid-based etchant using the photoresist as a mask. The remaining BPSG (fourth insulating layer 108), SiO ₂ (third insulating layer 106), BPSG (second insulating layer 105), S
iO ₂ (first insulating layer 104) is continuously etched to open a contact hole. Next, the photoresist used as a mask is ashed and subjected to surface treatment with an ammonia-based solution and a sulfuric acid-based solution to obtain the structure in FIG.

Subsequently, a thickness of 100
A BPSG of nm is deposited to form a fifth insulating layer 109 to obtain the structure of FIG.

Next, a heat treatment is performed, and BPSG (fifth
BPSG (fifth insulating layer 1)
09) Smoothing the surface. At this time, the bowl-shaped shape formed on the fourth insulating layer 108 is simultaneously reflowed by the hydrofluoric acid-based etchant at the time of opening the contact hole, and becomes a smooth shape without corners. Here, etching is performed by anisotropic dry etching until the bottom surface of the contact hole is exposed, and the structure of FIG. 1C is obtained.

Further, a surface treatment is performed, and an aluminum alloy having a thickness of 1 μm is deposited by a sputtering method, thereby forming a third conductive layer 110 to obtain a structure shown in FIG.

Next, a technique related to the present invention will be described with reference to the drawings. FIGS. 2A and 2B show this technology.
FIG. 4 is a longitudinal sectional view in the order of the manufacturing steps.

The structure of the present invention shown in FIG.
The fourth insulating layer 208, the third insulating layer 206, the second insulating layer 205, and the first insulating layer 204 are formed by the same procedure as in the embodiment and are subjected to only anisotropic dry etching by photolithography.
A contact hole penetrating through is formed.

Subsequently, the thickness is 100 nm by the LPCVD method.
m of BPSG is deposited to form a fifth insulating layer 209. Here, the concentration of boron and the concentration of phosphorus are adjusted so that the BPSG can flow at a lower temperature than the BPSG used for the fourth insulating layer 208 and the second insulating layer 205.

Next, the fifth insulating layer 209 is flowed, the fourth insulating layer 208 and the second insulating layer 205 are subjected to a heat treatment at a temperature at which no reflow is performed, and are etched by anisotropic dry etching until the bottom of the contact hole is exposed. 2A is obtained.

Subsequently, Ti is deposited to a thickness of 50 nm by sputtering.
The region in contact with the n ⁺ layer 203 is deposited by RTP to TiSi ₂ ,
The third conductive layer 210 is formed by depositing 0 nm of TiN. Next, 500 nm of W is deposited by the LPCVD method, and the structure of FIG. 2B is obtained as the fourth conductive layer 211.

In FIG . 2 , W can be buried without voids by smoothing the side wall surface without damaging the entire shape of the vertically opened contact hole only by anisotropic dry etching . effective.

[0022]

As described above, according to the present invention, a contact hole is opened through a wiring insulating layer in which a plurality of insulating layers are stacked, and impurities are added to the entire surface including the side wall surface and the bottom surface of the contact hole. depositing a SiO _2, and the flow of SiO ₂ added with impurities by heat treatment, SiO ₂ added with impurities to the bottom of the contact hole is exposed
Etching has an effect that the side wall surface of the contact hole can be smoothed and the step coverage of the conductive layer deposited by the sputtering method can be improved to near the theoretical limit.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a manufacturing method according to an embodiment of the present invention in the order of steps.

FIG. 2 is a longitudinal sectional view showing a manufacturing method of a technique related to the present invention in the order of steps.

FIG. 3 is a longitudinal sectional view showing a conventional manufacturing process in the order of processes.

[Explanation of symbols]

101, 201, 301 P-type Si substrate 102, 202, 302 First conductive layer 103, 203, 303 n ⁺ layer 104, 204, 304 First insulating layer 105, 205, 305 Second insulating layer 106, 206, 306 Third insulating layer 107, 207, 307 Second conductive layer 108, 208, 308 Fourth insulating layer 109, 209, 309 Fifth insulating layer 110, 210, 310 Third conductive layer 211 Fourth conductive layer

Claims (2)

(57) [Claims] An insulator made of SiO ₂ to which impurities are added.
Stack multiple insulating layers including layers and add impurities at the top
The first inter-metal dielectric layer as an insulating layer of SiO ₂ was
Forming the first layer with a hydrofluoric acid-based etchant.
By etching the film thickness above the insulating layer
This is etched away in a bowl shape, followed by anisotropic
The first etching under the bowl shape is performed by performing light etching.
The remaining thickness of the insulation layer and other insulation beneath it
The wiring contact hole through the layer reaching the substrate
Forming an opening in the inter-insulation layer, and forming the upper portion into the bowl shape.
A second insulating layer made of SiO ₂ doped with impurities on the entire surface including the side wall surface and the bottom surface of the contact hole,
Depositing a layer of said second insulating layer by heat treatment
At the same time as smoothing the surface, the first insulating layer
Steps to make the bowl shape smooth with no corners
After, a method of manufacturing a semiconductor device which comprises a step of etching the second insulating layer to the bottom surface of the contact hole by anisotropic dry etching is exposed. 2. The method according to claim 1, wherein said first and second insulating layers are BPSG .