JP2647026B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device useful for forming a bonding pad.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described with reference to FIG. An insulating film 302 is formed on the main surface of the semiconductor substrate 301 on which the impurity regions 314 of the semiconductor element are formed.
For example, after forming a two-layer structure of a silicon oxide film having a thickness of 1.4 μm and a plasma silicon nitride film having a thickness of 1800 angstroms, Ti having a thickness of 500 angstroms and TiN having a thickness of 1000 angstroms are used as barrier metals 303. It is formed in a laminated structure, and is patterned by sputtering aluminum having a thickness of 6500 angstroms to be the first layer wiring 304 together with the barrier metal 303. The presence of the TiN / Ti barrier metal 303 can suppress the occurrence of aluminum spikes and prevent the PN junction breakdown of the impurity region 314.

After that, as a polyimide interlayer insulating film 305, a coating flat film, for example, an organic resin film such as a compound of silicon and polyimide is applied to a thickness of about 1.5 μm.
Heat treatment is performed several times at 0 to 400 ° C. to harden the applied flat film.
By this heat treatment, the thickness of the applied flat film becomes about 1.0 μm. Next, the through holes 30 are formed in the interlayer insulating film 305.
6 is opened, and the etching at this time is performed by the interlayer insulating film 3.
Since the film thickness of the layer 05 is as thick as about 1.0 μm, the step coverage of the wiring of the second layer becomes very poor if one hole is opened vertically by one etching. Generally, taper etching combined with etching is performed, and the following method is employed.

First, a plasma silicon nitride film (not shown) serving as a mask material for etching an interlayer insulating film is formed on the interlayer insulating film to a thickness of about 1800 angstroms,
Using the photoresist to which the mask pattern has been transferred, the plasma nitride film on the through-hole portion and the region serving as the concave portion around the bonding pad is removed. Next, the interlayer insulating film is removed by using the plasma nitride film as a mask. At this time, first, an etching apparatus that isotropically advances etching is used, and about half the thickness of the interlayer insulating film (dimension A in FIG. 3). Is etched.

In this method, active radicals formed by dissociation of a reaction gas in a plasma are reacted with a film to be etched and are removed as volatile substances. Since the etching also proceeds, the interlayer insulating film is opened larger than the opening of the plasma nitride film of the mask material, and the cross-sectional shape of the opening becomes a semicircle.

Subsequently, the remaining interlayer insulating film is removed by anisotropic etching using the same plasma nitride film as a mask.

In this method, an electric field is applied to the ionized reaction gas, so that the etching proceeds vertically and there is almost no lateral spread. Therefore, the center portion of the interlayer insulating film which is opened in a semicircular shape by the isotropic etching is vertically opened with substantially the same size as the opening portion of the plasma nitride film (dimension B _{1 in} FIG. 3).

By performing such two-stage etching, the step in the through-hole portion is made gentle, and the step coverage of the second-layer wiring is improved.

At the time of this through hole PR, a portion of the interlayer insulating film 30 where the bonding pad 309 is formed at the same time.
5 is also removed by etching, and a recess 310 is formed so as to expose the insulating film 302. For example, when the bonding pad 309 is formed as a square having a side of 110 μm, the size of the recess is set to a square having a side of about 150 μm in consideration of a variation in bonding position. Avoid damage.

After removing the plasma silicon nitride film as a mask material, a second layer wiring 307 and a bonding pad 309 are formed by anisotropic etching using, for example, a 1.6 μm thick aluminum or the like. Then, the protective insulating film 308 is completed by removing only the bonding pad portion. The reason why the bonding pad is formed only of aluminum, which is the material of the second layer wiring, is that if a barrier metal is provided below the bonding pad like the first layer wiring, the adhesion strength of the lower surface is weakened. The reason why the organic resin interlayer insulating film 305 is removed immediately below the bonding pad is that if such a soft organic resin film exists immediately below the bonding pad, it will be crushed or peeled off during bonding.

[0011]

In the above-described conventional method for manufacturing a semiconductor device, the etching conditions for the through-hole PR are such that the through-hole on the first-layer wiring has an optimum shape and the second-layer wiring has an optimum shape. Step coverage is set to be better. It is preferable that the shape of the through hole 306 shown in FIG. 3 is substantially equal to A, ie, the amount of the interlayer insulating film removed by isotropic etching, and B _1, ie, the amount removed by anisotropic etching.

By the way, since there is no first layer wiring around the bonding pad which is simultaneously etched,
When the interlayer insulating film is formed of a silicon polyimide film or the like having good flatness, the thickness of the first layer wiring is larger than that of the portion where the wiring is provided.

However, the amount A of the interlayer insulating film removed by isotropic etching at the time of the through hole PR is the same as that of the through hole portion. Therefore, the amount B3 to be removed by anisotropic etching increases, and the wall surface of the concave portion 310 of the interlayer insulating film around the bonding pad has a vertically steep shape.
The step becomes very severe.

As a result, when the wiring material (aluminum) of the second layer is sputtered in the next step, the wiring material of the second layer is deposited thickly along the wall surface of the concave portion, and the second layer is formed by anisotropic dry etching. 3 cannot be completely removed at the time of wiring patterning, and becomes a sidewall shape.
The aluminum residue 313 as shown in FIG. If the recess is connected to the recess of the adjacent bonding pad by a scribe line or the like, the bonding pad is electrically short-circuited via the aluminum residue 313, and the function of the semiconductor device is impaired, and the yield is reduced. There was a problem of doing.

For example, when the interlayer insulating film 305 is formed such that the total thickness of the first layer wiring 304 is 0.8 μm and the film thickness on the first layer wiring 304 is 1.0 μm, The film thickness of the interlayer insulating film 305 where the first wiring 304 does not exist is 1.5 μm. Therefore, in FIG. 3, A = 0.5 microns, B ₁ = 0.5 microns, and B ₃ = 1.0 microns.

Here, the film thickness of the second-layer aluminum flat portion (the upper surface of the interlayer insulating film 305) is 1.6 μm, and the film thickness of the aluminum removed even after performing 50% over-etching is as follows. 1.6 microns x 1.5 =
2.4 microns.

The thickness of the aluminum at the step is 1.0
Since micron (dimension B ₃ ) +1.6 μm (film thickness of aluminum at flat portion) = 2.6 μm, 2.6
Micron-2.4 micron = 0.2 micron remaining 313 of aluminum is generated. That is, when the above conditions, the dimension B ₃ aluminum remaining 313 occurs when more than 0.8 microns.

An object of the present invention is to provide a method of manufacturing a semiconductor device having the above-described configuration, in which a bonding pad is formed without generating aluminum residue.

[0019]

A feature of the present invention is that a first element provided on one main surface of a semiconductor substrate on which a semiconductor element is formed is provided.
A method of manufacturing a semiconductor device in which a bonding pad is formed on a first region of an insulating film and a first-layer wiring is formed on a second region, wherein the first region around the first region is formed.
Forming a spacer made of an insulating material at least on the surface of the first insulating film; forming the first layer wiring on the second region of the first insulating film; Forming a second insulating film having high flatness covering the whole including the wiring of the layer and the first region;
By selectively etching away the second insulating film, a through-hole reaching the wiring of the first layer and the first region of the first insulating film are exposed, and a boundary between the through-hole and the upper surface of the spacer is formed. Forming a concave portion located at the same time, and forming a conductive film on the second layer wiring connected to the first layer wiring through the through hole by patterning the conductive film and surrounding the spacer in the concave portion. Simultaneously forming the bonding pads to be attached to the first region of the first insulating film. Here, the second insulating film is preferably made of silicon polyimide. Further, the etching may include a step of removing a predetermined depth from the surface of the second insulating film by isotropic etching and removing the remaining film thickness by anisotropic etching. Further, the whole of the spacer can be constituted by an insulating layer. Alternatively, the spacer may be formed by covering a polycrystalline silicon film with an insulating layer. This insulating layer can be a silicon oxide film formed by a CVD method. Here, as a method of forming a spacer, after performing a plasma treatment on the surface of the insulating layer,
It is preferable to form a trapezoidal cross section by applying a resist mask on the surface and performing wet etching using the resist mask as a mask.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor device shown in the order of manufacturing steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a lower layer of a silicon oxide film having a thickness of, for example, 1.4 μm and a thickness of 1800 Å are formed on a main surface of a semiconductor substrate 101 on which an impurity region 114 of a semiconductor element is formed. A composite insulating film 102 composed of an upper layer of a silicon nitride film is formed. Then, after a contact hole is formed in the portion of the insulating film 102 on the impurity region 114 of the semiconductor element, polycrystalline silicon 111 having a thickness of about 1500 Å is grown.

An impurity such as arsenic is applied to the entire surface of the polycrystalline silicon 111 at an energy of 70 keV and a dose of 1.0 ×.
Ion implantation at about 10 ¹⁶ atoms / cm ² and about 90
By applying a heat treatment at 0 ° C., the impurities are diffused into the polycrystalline silicon. At this time, a polycrystalline silicon resistor (not shown) having an arbitrary resistance value can be formed on the insulating film 102 by controlling the impurity concentration by a dose amount or the like.

Next, as shown in FIG. 1B, unnecessary portions of the polysilicon other than the polysilicon resistor and the diffusion layer electrode are removed by etching. That is, since the impurity region 114 of FIG. 1 does not use polycrystalline silicon as its extraction electrode, the polycrystalline silicon at the location shown in FIG. 1 is entirely removed.

Then, a silicon oxide film 112 having a thickness of about 5000 angstroms is formed by the CVD method.
This CVD oxide film 112 has a polycrystalline silicon resistance and a first resistance.
This is a film for insulating the wiring of the layer, and unnecessary portions are removed. At this time, patterning is performed so that the CVD oxide film 112 remains in a band around the region where the bonding pad is formed.

The patterning method will be described. First, a plasma treatment is performed on the surface of the silicon oxide film formed by the CVD method. This plasma treatment is performed by flowing CF ₄ gas at 25 SCCM, 250 W, 70 ° C., 0.3 To.
Perform for 10 seconds at rr.

The surface of the silicon oxide film subjected to such a plasma treatment becomes porous, and the adhesion to the resist becomes poor. Therefore, using the resist mask as a mask, H
When etching with F to form a pattern of the silicon oxide film 112, HF easily penetrates into the interface between the surface and the resist, and the surface is etched, so that the side surface 112W of the silicon oxide film 112 becomes, for example, as shown in FIG. The acute angle with the bottom surface becomes a taper of 60 degrees, and the silicon oxide film 112 is formed.
Has a trapezoidal cross-sectional shape.

With such a shape, no aluminum residue is generated on the side surface of the silicon oxide film 112 itself as a spacer.

Next, in order to prevent aluminum spikes, the barrier metal 103 is formed of a Ti (lower layer) having a thickness of about 50 Å and a T (thickness) of about 1000 Å.
It is formed in a laminated structure with iN (upper layer), and has a thickness of about 6500, on which a first layer wiring 104 is formed together with a barrier metal.
Angstrom aluminum is patterned by sputtering.

After that, as shown in FIG. 1C, a coating flat film, for example, a silicon polyimide film is applied as an interlayer insulating film 105 to a thickness of about 1.5 μm, and
Heat-treated several times at 0 ° C. and baked to reduce the thickness of the applied flat film to about 1.0 μm. A plasma silicon nitride film may be provided under the silicon polyimide film. Then, a through hole 106 is opened in the interlayer insulating film 105. At this time, a plasma silicon nitride film (not shown) formed at a thickness of about 1800 angstroms as in the conventional example shown in FIG. Perform taper etching by two-step etching using
The step coverage of the second layer wiring is not deteriorated.

At the time of this through hole PR, the portion of the interlayer insulating film 10 where the bonding pad 109 is formed at the same time is formed.
5 is also removed by etching to form a recess 110 so as to expose the insulating film 102. At this time, since a strip-shaped CVD oxide film 112 is formed at the boundary of the interlayer insulating film to be removed by etching, This part is the interlayer insulating film 1
05 is thinner than that of FIG. Therefore, the difference in the amount B ₂ removed by the anisotropic etching with respect to the amount A removed by the isotropic etching of the interlayer insulating film 105 is reduced, and the step of the interlayer insulating film 105 is reduced.

Accordingly, when the second layer wiring 107 and bonding pad 109 are patterned by anisotropic dry etching of, for example, 1.6 μm thick aluminum or the like to improve pattern accuracy, the wall surface of the interlayer insulating film 105 No aluminum residue is generated along the line, and product quality and manufacturing yield can be increased.

Since the CVD silicon oxide film 112 formed as a spacer around the bonding pad is used in other places to insulate the polycrystalline silicon resistor and the first layer wiring, the step of the interlayer insulating film is reduced. Since this is not a new process, the manufacturing period is not extended and the manufacturing cost is not increased.

For example, when the interlayer insulating film 105 is formed such that the total thickness of the first layer wiring 104 is 0.8 μm and the film thickness on the first layer wiring 104 is 1.0 μm. The thickness of the interlayer insulating film 105 on the spacer (silicon oxide film) 112 having a thickness of 0.5 μm is 1.2 μm. By the way, the first layer wiring 104 is also a spacer 11
The film thickness of the interlayer insulating film 105 where no 2 exists is 1.5 μm as in the conventional example.

Therefore, in FIG. 1C, A = 0.
5 microns, B ₁ = 0.5 microns, B ₂ = 0.7 microns.

Here, the thickness of the aluminum flat portion (upper surface of the interlayer insulating film 105) of the second layer is 1.6 μm, and the thickness of aluminum removed when 50% overetching is performed is as follows. 1.6 microns x 1.5 =
2.4 microns.

In this embodiment, the thickness of the aluminum at the step is 0.7 μm (dimension B ₂ ) +1.6 μm (the thickness of the aluminum in the flat portion) = 2.3 μm. Does not occur. That is, in the case of the above conditions, the spacer (CVD silicon oxide film)
If the film thickness of 112 is greater than 0.4 microns, no aluminum residue will be generated.

FIG. 2 is a sectional view showing a second embodiment of the present invention. Note that, in FIG. 2, the same or similar portions as those in FIG.

In FIG. 2, the spacer for preventing the remaining aluminum is made of polycrystalline silicon
It has a cross-sectional shape covered with a VD silicon oxide film 212. This polycrystalline silicon film 211 becomes a polycrystalline silicon resistance at other portions.
Can be formed by patterning. Also CVD
The patterning of the silicon oxide film 212 is performed by using the same method as in the first embodiment shown in FIG.
Has a tapered shape.

In the second embodiment, although the size of the spacer is slightly widened, the step of the interlayer insulating film 105 is further reduced by the thickness of the polycrystalline silicon. This is effective when it is necessary to increase the thickness of the wiring.

[0041]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the thickness of the interlayer insulating film around the bonding pad portion is reduced by using the spacer.
Since the step formed when the interlayer insulating film is etched at the time of the through hole PR can be reduced, aluminum residue can be prevented from being generated along the wall surface of the interlayer insulating film,
This has the effect of improving the quality of the product and increasing the production yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

101, 301 semiconductor substrate 102, 302 insulating film 103, 303 barrier metal 104, 304 first layer wiring 105, 305 interlayer insulating film 106, 306 through hole 107, 307 second layer wiring 108, 308 protective insulating film 109, 309 Bonding pad 110, 310 Concavity 111, 211 Polycrystalline silicon 112, 212 CVD silicon oxide film (spacer) 114, 314 Impurity region 112W, 212W Tapered side surface 313 Aluminum residue A Removed by isotropic etching during through hole PR the amount of that amount B ₁ of the interlayer insulating film, B _2, B ₃ interlayer insulation film to be removed by the through hole PR at anisotropic etching

Claims (7)

(57) [Claims] 1. A bonding pad is formed on a first region of a first insulating film provided on one main surface of a semiconductor substrate on which a semiconductor element is formed, and a wiring of a first layer is formed on a second region. Forming a spacer of at least a surface of an insulating material on the first insulating film around the first region; and forming the second insulating film on the first insulating film around the first region. Forming the first layer wiring on a region, and forming a highly flat second insulating film covering the entire region including the spacer, the first layer wiring and the first region. And selectively removing the second insulating film by etching to reach the first layer wiring.
Simultaneously forming a recess that exposes the through-hole and the first region of the first insulating film and whose boundary is located on the upper surface of the spacer; and applying and patterning a conductive film to form the through-hole. A second-layer interconnect connected to the first-layer interconnect through a hole and the bonding pad, which is surrounded by the spacer in the recess and adheres to the first region of the first insulating film, are simultaneously formed. And a method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein said second insulating film is made of silicon polyimide. 3. The method according to claim 1, wherein the etching includes a step of removing a predetermined depth from the surface of the second insulating film by isotropic etching and removing the remaining film thickness by anisotropic etching. Item 2. A method for manufacturing a semiconductor device according to Item 1. 4. The method according to claim 1, wherein the entire spacer is formed of an insulating layer. 5. The spacer according to claim 1, wherein the spacer is formed by covering a polycrystalline silicon film with an insulating layer.
The manufacturing method of the semiconductor device described in the above. 6. The method according to claim 4, wherein the insulating layer is a silicon oxide film formed by a CVD method. 7. After performing a plasma treatment on the surface of the insulating layer, a resist mask is applied to the surface, and the spacer is formed in a trapezoidal cross-sectional shape by performing wet etching using the resist mask as a mask. 6. The method for manufacturing a semiconductor device according to claim 4, wherein