JP2782761B2 - Pulse width output device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pulse width output device for outputting a pulse width signal from a microprocessor and obtaining an analog signal corresponding to the pulse width. TECHNICAL FIELD The present invention relates to a pulse width output device having improved output resolution in a D / A conversion circuit using a microprocessor internally having a plurality of pulse width signal output functions.

<Prior Art> Recently, a microprocessor having a plurality of pulse width signal output units (functions) has appeared (for example, NEC 783).
12), and is being used in various devices that handle analog signals.

Such a microprocessor is configured to select one of several pulse width modulation periods obtained by dividing the reference clock, and the plurality of pulse width signal output units all operate at the same selected period. It is supposed to work.

Here, the resolution of the output pulse width can be increased by selecting the period of the pulse width modulation to be large.

<Problem to be Solved by the Invention> By the way, in such a microprocessor having a plurality of pulse width signal output units therein, since all of the plurality of pulse width signal output units operate at the same cycle, When these are used at the same time, for example, the first pulse width signal output means needs a conversion speed of the period T0, while the second pulse width signal output means has a high output even if the period is sacrificed. A problem arises in that different purposes cannot be used such that resolution is required.

The present invention has been made in view of such circumstances, and an object of the present invention is to simultaneously use a plurality of pulse width signal output means in a microprocessor at the same cycle while using one of a high-speed pulse width signal. The other purpose is to realize a pulse width output device capable of outputting a pulse width signal with high resolution.

<Means for Solving the Problems> According to the present invention for solving the above-described problems, first and second units for outputting a pulse width signal having a pulse width corresponding to set data are provided.
Pulse width signal output means, and first and second integration means for integrating a reference signal for a time corresponding to the pulse width of the pulse width signal output from each of these pulse width signal output means, The second pulse width signal output means operates at a common pulse width modulation period (T0).

The first pulse width signal output means outputs a high-speed pulse width signal corresponding to data set within one cycle of the cycle, and the second pulse width signal output means
It is characterized in that a high-resolution pulse width signal corresponding to data set using a plurality of the cycles is output.

<Operation> The first pulse width signal output means outputs one of the pulse width modulation periods.
A pulse width signal having a pulse width corresponding to the data set within the cycle is output, and the first integrating means integrates the reference signal for a time corresponding to the pulse width, and an analog signal corresponding to the set data. At a high speed in one cycle.

The second pulse width signal output means outputs a pulse width signal of a pulse width corresponding to the data set using a plurality of pulse width modulation cycles, and the second integration means converts the pulse width into a pulse width for each cycle. Since the reference signal is sequentially integrated for a corresponding time and an analog voltage corresponding to the set data is obtained over a plurality of cycles, a highly accurate analog signal can be obtained.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration block diagram showing one embodiment of the present invention. In the figure, MP is a microprocessor, and 1 and 2 are first and second provided inside the microprocessor.
The pulse width signal output means is realized by firmware. These pulse width signal output means
All operate at the same pulse width modulation cycle.

3 is a first pulse width / analog signal conversion circuit for inputting a pulse width signal from the first pulse width signal generating means 1,
4 is a second pulse width / analog signal conversion circuit for inputting a pulse width signal from the second pulse width signal generating means 2,
Each of these circuits has the same circuit configuration.

In the pulse width / analog signal conversion circuits 3 and 4, I
NT1 and INT2 are integrators that integrate the reference voltage Es, and SH1 and SH2 are sample and hold circuits that sample and hold the output of the integrator INT.

The integrators INT1 and INT2 are provided with a switch SW1 which is turned on for a time corresponding to the pulse width by a pulse width signal output from each pulse width signal generating means 1 and 2 in the microprocessor MP, and an integration resistor R, Capacitor C, reset switch SW2 short-circuiting both ends of this capacitor C, reference voltage Es
Is input via a switch SW1 and an integrating resistor R, and a capacitor C is constituted by an amplifier A connected between input and output terminals.

 The operation of the device configured as described above will be described below.

FIG. 2 is a time chart showing an example of the operation.
In this example, while the analog signal OUT1 is obtained at high speed with one pulse width signal output from the first pulse width signal output means 1, the second pulse width signal output means 2 outputs the analog signal OUT1 at high speed.
High resolution analog signal by outputting pulse width signal twice
It is assumed that OUT2 is obtained.

(A) is a waveform showing the pulse width modulation cycle selected by each pulse width signal output means 1 and 2 in the microprocessor MP, and (b1) and (b2) are the first and second pulse width /
The timing at which the switch SW2 is turned on in the analog signal conversion circuits 3 and 4 is shown. When the switch SW2 is turned on, both ends of the capacitor C are short-circuited, and the integrator IN
T1 and INT2 are initialized.

(C1) and (c2) are first and second pulse width signal output means 1,
2 indicates the pulse width signal, and at the rising edge of the periodic waveform shown in (a), data D1 and D21 designating the pulse width to be output to each pulse width signal output means are set. A pulse width signal having a time width corresponding to each of the data D1 and D21 set earlier is output.

Here, as shown in (c1), the first pulse width signal output means 1 outputs one pulse T0 within one pulse width modulation period.
A pulse width signal having a pulse width t11 corresponding to the set data D1 is output.

On the other hand, the second pulse width signal output means 2
As shown in (c2), the data D21 and D22 are set in two periods of the pulse width modulation period T0, and these data D21 and D2 are set.
The pulse width corresponding to 2 is divided into two pulse widths t1 and t2, and output over two cycles. That is, if the output is to be performed within one cycle, D21 + D22 is the data to be set originally, and t1 + t2 is the pulse width of the pulse width signal to be output originally.

The switch SW1 of the first integrator INT1 is turned on by the pulse width signal from the first pulse width signal output means 1 for a time t11 corresponding to the pulse width.

When the switch SW1 is turned on, the reference voltage Es is integrated via the switch SW1 and the integration resistor R1, and as shown in (d1) from the output terminal of the integrator INT1, the inclination angle θ1 is turned on after the switch SW1 is turned on. , And gradually rises to the voltage E01 shown by the equation (1).

E01 = (Es / R1) × (t11 / C) (1) The output voltage E01 of the first integrator INT1 is obtained when one pulse width modulation period T0 elapses and after a while,
The sampling is performed as shown in (d1), and the analog output signal OUT1 is obtained through the sample and hold circuit SH1.

This output signal OUT1 can be obtained at high speed because it uses one pulse width modulation period and uses the integrator INT1 having a relatively short integration time.

The switch SW1 of the second integrator INT2 is turned on by the pulse width signal from the second pulse width signal output means 2 for the time t1 in the first pulse width modulation cycle, and is turned on for the time t2 in the next pulse width modulation cycle. Only turns on.

When the switch SW1 is turned on, the reference voltage Es is integrated via the switch SW1 and the integrating resistor R2, and as shown in (d2) from the output terminal of the integrator INT2, the inclination angle θ2 is turned on after the switch SW1 is turned on. (This inclination angle is gentler than θ1), and gradually increases, and at the time when the first pulse width modulation cycle ends, the voltage becomes E021 represented by Expression (2).

E021 = (Es / R2) × (t1 / C) (2) When the next pulse width modulation cycle ends,
The voltage becomes the voltage E022 shown by the equation (3).

E022 = E021 + (Es / R2) × (t2 / C) = (Es / R2) × {(t1 + t2) / C} (3) After the two pulse width modulation periods are completed, the second integrator
After a lapse of two pulse width modulation periods, the output voltage E022 of INT2 is sampled as shown in (d2), passes through the sample and hold circuit SH2, and becomes an analog output signal OUT2.

Since the analog output signal OUT2 is obtained by the pulse widths t1 and t2 output in two pulse width modulation periods using the second integrator INT2 having a long integration time, the analog output signal OUT2 has a high resolution. Becomes

In the above embodiment, the first and second integrators INT1, INT
Although the integration time is changed by changing the values of the integration resistors R1 and R2 in FIG. 2, the value of the capacitor or the magnitude of the reference voltage Es may be changed.

Further, in order to obtain a high-resolution analog signal, two or more pulse width modulation periods may be used. Further, the microprocessor may have two or more pulse width signal output means.

<Effects of the Invention> As described in detail above, according to the present invention, while simultaneously using a plurality of pulse width signal output means in a microprocessor at the same cycle, one outputs a high-speed pulse width signal. On the other hand, a pulse width output device capable of outputting a high resolution pulse width signal can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing an example of the operation. MP: microprocessor, 1,2: pulse width signal output means, 3, 4: pulse width / analog signal conversion circuit, INT1, INT2 ... integrator, SH1, SH2 ... sample hold circuit

Claims (1)

(57) [Claims] A first pulse width signal output means for outputting a pulse width signal having a pulse width corresponding to set data; and a pulse width signal output from each of these pulse width signal output means. First and second integration means for integrating the reference signal for a time corresponding to the pulse width, wherein the first and second pulse width signal output means operate at a common pulse width modulation period (T0). The first pulse width signal output means outputs a high-speed pulse width signal corresponding to data set within one cycle of the cycle, and the second pulse width signal output means outputs a plurality of pulses of the cycle. A pulse width output device for outputting a high-resolution pulse width signal corresponding to data set using a cycle.