JPS6022682Y2 - Digital to analog converter - Google Patents

Description

[Detailed Description of the Invention] The present invention is a digital-to-analog converter (hereinafter referred to as rDADA converter) suitable for use in measuring instruments, automatic control devices, etc.

) regarding. DA converters that convert a digital signal input into a pulse width signal using a timing circuit and integrate the signal to obtain an analog signal output are widely known.

In general, when performing high-precision conversion in such an A converter, the number of digits of the input digital signal is large, and the response speed is slow.

On the other hand, when performing high-speed conversion, it is inevitable that the accuracy will decrease.

For example, when adjusting a device using a measuring instrument that uses an A converter, it is necessary to operate with a fast response speed even if the accuracy is low in the initial stage of the adjustment, and in the final stage of the adjustment, Even if the response speed is slow, highly accurate operation is required.

In order to cope with this, conventional devices are equipped with several DA converters with different precisions and speeds, and are configured to switch between them.

This has the disadvantage that the device becomes expensive and also large in size.

The present invention is an improvement on this, and is inexpensive and allows a single DA converter to select and switch multiple clock signals with different periods and the time constants of the corresponding integration circuits in conjunction with each other. The purpose is to provide a small DA converter.

The present invention uses this as a section averaging circuit (SectionalAv).
One of its characteristics is that it is applied in two ways.

The interval averaging circuit is an integrating circuit that is configured to be reset accurately within one sampling period and not to include information from at least two sampling periods before in its output.

Regarding this, Nikkei Electronics 197
Although it is described in detail on pages 85 to 104 of the September 24 issue, it will also be explained here in the description of the embodiments.

The present invention uses a digital input terminal and digital input information given to this digital input terminal as parallel inputs,
A clock signal is input, and one cycle is set every time a predetermined number of clock signals are input, and a pulse time width signal with a time width corresponding to the digital input information is sent out for each cycle. and an integration circuit that integrates a constant reference voltage for the duration of this pulse time width signal, and repeats the integration immediately after the elapse of this duration so that the output becomes the starting point potential at the end of the above cycle. A digital-to-analog converter using an interval averaging circuit, comprising: a plurality of input terminals into which a plurality of clock signals having different frequencies are inputted as the clock signal;
a selection means for selecting one of the input terminals and applying it to the clock signal input of the timing circuit; and a switching means for switching the time constant of the integrating circuit in conjunction with the selection switching of the selection means; The switching means for switching and the selection means are characterized in that they select a smaller time constant as the frequency of the clock signal selected by the selection means becomes higher.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In Figure 1, 1 is a digital input terminal, 2 is a timing circuit, 3 and 4 are clock signal generation circuits, 5 and 6 are selection switching input terminals, 7 is a start input terminal, 8 is a busy output terminal, and 9 is an RS flip-flop. 10.11 is an AND circuit, 12 is an inverter, 3.14 is an operational amplifier, and 15 is an analog output terminal.

Also, 1, -Es is a reference power supply, R is a resistor, C1, C2,
C3 indicates a capacitor.

SW, to SW4 are switches (FETs are used).

At the digital input terminal 1 there is an input digital signal, which is arranged to be input in parallel to the timing circuit 2 .

Two clock signals with different periods are guided to the timing circuit 2 from clock signal generation circuits 3 and 4 via AND circuits 10 and 11, respectively.

Selection signals are coupled to the AND circuits 10 and 11 from selection switching input terminals 5 and 6, respectively, and one of the AND circuits is configured to open in response to the selection signal.

Further, the output Q of the RSS flip-flop circuit 9 is led to the timing circuit 2 as a strobe signal input.

The end signal generated by the timing circuit 2 is guided to the reset manual R of the RSS flip-flop circuit 9.

The signal from the start input terminal 7 is fed to the set input signal S of the RSS flip-flop circuit 9, and the inverted output Q is fed to the busy output terminal 8 via the inverter 12.

The output P2 of the timing circuit 2 is a pulse time width signal corresponding to the set magnitude of the input digital signal,
It may be configured to control switch SW0 and switch SW2.

The switch SW1 is a changeover switch, the - contact a is led to the input of the operational amplifier 13 via the resistor R, the contact A is connected to the reference voltage -Es, and the contact C is connected to the potential point of the output terminal 15. There is.

Switch SW2 is an open/close switch.

When there is a signal at output P2, switch SW1 is at contact ab
When there is no signal at the output P2, the switch SW1 is connected between the contacts ac, and the switch SW2 is closed.
Switch SW2 is controlled to open.

The output of operational amplifier 13 is connected to switch SW3 and capacitor C.
1 series circuit, switch SW, and capacitor C2
is fed back to the input by a series circuit.

Switches SW3 and SW4 are controlled by signals at selection switching input terminals 5 and 6, respectively.

That is, when the clock signal generation circuit 3 is selected, the switch SW3 is closed, and when the clock signal generation circuit 4 is selected, the switch SW is closed, so that they are controlled in conjunction with each other.

The operational amplifier 13 uses these switches to connect the capacitor C1.
Alternatively, C2 is coupled to form an integrating circuit.

The output of operational amplifier 13 is applied to capacitor C3 and the input of operational amplifier 14 via switch SW2.

The capacitor C3 constitutes a holding circuit, and the operational amplifier 14 constitutes a buffer amplifier circuit with a gain of 1 that outputs the potential of the capacitor C3.

The output of this operational amplifier 14 is coupled to an output terminal 15.

Here, the clock signal generation circuit 3 generates a high frequency clock signal, and the clock signal generation circuit 4 generates a low frequency clock signal.

Further, the capacitor C1 has a small capacitance, and the capacitor C2 has a large capacitance.

The timing circuit 2 is set so that one period occurs every time a predetermined number of clock signals are input, and for each period, the timing circuit 2 generates one period according to the value of the digital signal applied to the parallel input of that period. It sends out a pulse width signal with a specified length.

Therefore, when the frequency of the applied clock signal is high, the period is automatically shortened because the time for each pulse of the clock signal to be inputted is short, and when the frequency of the clock signal is low, the period is lengthened.

Since the time discrimination accuracy of the output pulse width signal of the timing circuit 2 is constant, when the period is long, the accuracy of the information contained in the output pulse width signal can be improved.

Therefore, the large number of digits of the digital signals applied to the parallel inputs can be effectively utilized.

However, when the period is short, the accuracy of the information contained in the pulse width signal deteriorates, so that only the upper digits of the digital signal are effectively used, and there is no point in using the lower digits for measurement.

Therefore, this embodiment circuit is configured to take in only the upper m digits of the parallel input digital signals when the clock signal frequency is high.

The operation of the device configured in this way is shown in Figures 2 and 3.
This will be explained using the timing chart shown in the figure.

FIG. 2 is a timing chart when high speed, low precision is selected, and FIG. 3 is a timing chart when low speed, high precision is selected.

In the case of high speed and low precision shown in FIG. 2, the signal F1 is applied to the selection switching input terminal 5.

This opens the AND circuit 10, selects the clock signal generation circuit 3, and at the same time closes the switch SW3.

On the other hand, an input digital signal is applied to a timing circuit 2 from a digital input terminal 1 .

At this time, even if there is a (m+n) digit digital signal at the input terminal 1, only the first m digits will be taken in if the precision is low.

The timing circuit 2 receives the strobe signal F3 from the signal P1 at the start input terminal 7, converts it into a pulse time width signal according to the input clock signal, and sends it to the output P2.

As for the configuration of the timing circuit 2, a preset counter is used, for example, but since it is widely known, a description thereof will be omitted here (it is also detailed in the above-mentioned Nikkei Electronics article).

While the timing circuit 2 is operating, a busy signal P is applied to the terminal 8.
.

is sent out and is used to prohibit data capture in the previous or subsequent stages.

Switch SW1 outputs ab only during the time when there is a signal at output P2.
conduction between the two.

As a result, the integration circuit formed by the operational amplifier 13 integrates the reference voltage -Es.

This output voltage E1 is held in capacitor C3 via switch SW2, and appears at output terminal 15 as output voltage E2.

After time t1 has elapsed, switch SW1 is switched so that a and C are electrically connected, and switch SW2 is opened.

Thereby, the integrating circuit integrates this voltage E2 by folding back.

After a certain period of time, the output voltage E of the operational amplifier 13
1 returns to zero.

This timing circuit 2, an integration circuit made up of the operational amplifier 13, a circuit made up of the capacitor C3 and the operational amplifier 14 are as follows:
This is an interval averaging circuit.

In other words, the integration circuit operates over a period of time t1 corresponding to the amount of information.
, a constant reference voltage Es is integrated.

After time t1 has elapsed, the output potential of the integrating circuit is proportional to the length of time t□.

The output potential at this time is held in a holding circuit, and the held potential is folded back and integrated after a certain period of time.

In this way, the output of the integrating circuit will change over time (t1+t2
), it will return to the initial value.

If the timing circuit sends out a signal such that time (11+t2) corresponds to one sampling period, the output will be reset every period and will not always contain information from two periods earlier.

However, depending on the capacitance of the capacitor C3 in the holding circuit, the output voltage may not be stable at the initial rise.

The timing chart in Figure 2 (and Figure 3) shows E.
The gradual stabilization of the potential at point 2 is depicted in a slightly exaggerated manner.

In the circuit shown in Fig. 1, the end signal P3 is output from the timing circuit 2.
One reason why the RS flip-flop 9 is configured to be reset is to eliminate instability of the output voltage at the time of initial rise.

That is, the busy signal P is sent from the terminal 8, and while the busy signal P4 is present in the subsequent circuit, the output terminal 1 is sent.
5 is prohibited.

The constant of the timing circuit 2 may be determined so that the end signal P3 is generated after two to four cycles have elapsed depending on the instability of the rise.

Next, in the case of FIG. 3, the case of high precision and low speed will be described. In this case, the signal F2 is present at the selection switching input terminal 6, and the clock signal generation circuit 4 is selected.

At the same time, switch SW3 is opened and SW4 is closed.

This increases the period of the clock signal and correspondingly increases the time constant of the integrating circuit.

The number of digits of the digital signal input to the timing circuit 2 increases, and all (m+n) digits displayed at the input terminal 1 are taken in.

All other operations are the same.

The time length of the pulse time width signal sent to output P2 is set to 1.
7. , the timing circuit operates so that the l sampling period becomes (t't+t'2), assuming that the constant time required for fold-back integration is t'2.

Here, after the interval averaging circuit integrates the reference voltage Es as described above, it immediately performs fold-back integration and in order to respond at l sampling periods, the following relationship is established between the constants.

(However, the gain of the amplifier 13) That is, each circuit that is provided to operate by being selectively switched substantially satisfies the conditions as an interval average circuit.

Although the above example shows the case where two selections are switched, if the configuration is such that three or more selections are switched, more detailed selections can be made.

In this case as well, if each circuit satisfies the conditions for an interval average circuit, the same configuration can be achieved.

As described above, according to the DA converter of the present invention, a high-speed, low-accuracy mode and a low-speed, but high-accuracy mode can be arbitrarily switched and created using one device. This has the effect of providing a device that is inexpensive, compact, and has a wide range of applications.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention. FIG. 2 is an operation time chart of the above embodiment (when low precision and high speed is selected). FIG. 3 is an operation time chart of the above embodiment (when high precision low speed is selected). 1... Digital input terminal, 2... Timing circuit, 3, 4... Clock signal generation circuit, 5, 6... Selection switching input terminal, 7・・・・・・
...Start input terminal, 8...Busy output terminal, 9...RS flip-flop, 10, 11...
...AND circuit, 12...Inverter,
13, 14... operational amplifier, 15...
Analog output terminal, -Es...Reference voltage, R.
...Resistor, C1, C2, C3...Capacitor, SW engineering ~ SW, ...Switch.

Claims (1)

[Claims for Utility Model Registration] A digital input terminal and the digital input information given to this digital input terminal are input in parallel, and a clock signal is input, and one cycle is generated every time a predetermined number of clock signals are input. is set, and a timing circuit that sends out a pulse time width signal with a time width corresponding to the digital input information in each cycle, and a timing circuit that integrates a constant reference voltage for the duration of this pulse time width signal. In a digital-to-analog converter using an interval averaging circuit including an integrating circuit that performs fold-back integration so that its output becomes the starting point potential immediately after the elapse of this duration time and at the end of the above-mentioned cycle, a plurality of clock signals having different frequencies are used as the clock signal. a plurality of input terminals into which clock signals are input; a selection means for selecting one of the input terminals and applying it to the clock signal input of the timing circuit; switching means for switching a time constant; the switching means and the selection means are configured such that as the frequency of the clock signal selected by the selection means becomes higher, the switching means selects a smaller time constant; A digital-to-analog converter characterized by: