JP2739800B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2739800B2 JP2739800B2 JP4207684A JP20768492A JP2739800B2 JP 2739800 B2 JP2739800 B2 JP 2739800B2 JP 4207684 A JP4207684 A JP 4207684A JP 20768492 A JP20768492 A JP 20768492A JP 2739800 B2 JP2739800 B2 JP 2739800B2
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- insulated gate
- gate field
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 230000005669 field effect Effects 0.000 claims description 33
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 11
- BMZIBHZDQPLVIS-UHFFFAOYSA-N 4-[2-(2-morpholin-4-ylethylselanyl)ethyl]morpholine Chemical compound C1COCCN1CC[Se]CCN1CCOCC1 BMZIBHZDQPLVIS-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特にピークホールド回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a peak hold circuit.
【0002】[0002]
【従来の技術】従来ピークホールド回路の一例として図
4に示す回路がある。この回路は、ドレインを電源電位
VDDにゲートを入力端子Vinにソースを出力端子Vo
utに接続したNチャネル型絶縁ゲート電界効果トラン
ジスタ(以下、N型MOSFETと称す)Q1 と、出力
端子Voutと接地電位GNDの間に接続した容量素子
Cと、出力端子Voutと接地電位GNDの間に接続し
た抵抗素子Rによって構成されている。次にこの回路の
動作波形図を図5に示す。N型MOSFETQ1 のスレ
ッショルド電圧VT を0Vとすると、N型MOSFET
Q1 のソース電位Voutよりゲート電位Vinが大き
くなるとVout=VinとなるまでN型MOSFET
Q1 は導通状態となって容量素子Cを充電し、またN型
MOSFETQ1 のソース電位Voutよりゲート電位
Vinが小さいとN形MOSFETQ1 は非導通状態と
なって容量素子Cの電荷を抵抗素子Rを通して放電す
る。2. Description of the Related Art FIG. 4 shows an example of a conventional peak hold circuit. In this circuit, the drain is connected to the power supply potential VDD , the gate is connected to the input terminal Vin, and the source is connected to the output terminal Vo.
N, an N-channel insulated gate field effect transistor (hereinafter referred to as an N-type MOSFET) Q 1 connected to the output terminal Vout, a capacitor C connected between the output terminal Vout and the ground potential GND, and an output terminal Vout and the ground potential GND. It is constituted by a resistance element R connected therebetween. Next, an operation waveform diagram of this circuit is shown in FIG. When the threshold voltage V T of the N-type MOSFET Q 1 and 0V, the N-type MOSFET
N-type MOSFET than the source potential Vout for Q 1 until the gate potential Vin becomes larger when Vout = Vin
Q 1 is to charge the capacitor C in a conductive state and N-type MOSFET Q 1 of N-type MOSFET Q 1 and the gate potential Vin is lower than the source potential Vout is resistance element a charge of the capacitor C in a non-conductive state Discharge through R.
【0003】図5に示す実線の入力波形図Vinに対し
て、この回路の出力波形Voutは点線で示した様にな
り、ピークの波形を保持することが出来る。[0005] With respect to a solid line input waveform diagram Vin shown in FIG. 5, an output waveform Vout of this circuit becomes as shown by a dotted line, and a peak waveform can be held.
【0004】[0004]
【発明が解決しようとする課題】従来のピークホールド
回路では、図6に示すように信号の間隔(周波数)が一
定でない入力波形の場合、または入力信号の間隔がせま
い場合は信号のピークを検出できず、入力信号の間隔が
広くなるとピークを保持できないという欠点があった。In a conventional peak hold circuit, a signal peak is detected in the case of an input waveform in which the signal interval (frequency) is not constant as shown in FIG. 6 or when the input signal interval is narrow. However, there is a disadvantage that the peak cannot be held if the interval between the input signals is widened.
【0005】本発明の目的は、前述の欠点を除去するこ
とにより、入力信号の間隔(周波数)が変動しても、ピ
ークホールド回路の出力はピーク値を所定のレベル範囲
内に保持する手段を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and provide a means for holding the peak value of the output of the peak hold circuit within a predetermined level range even if the interval (frequency) of the input signal fluctuates. To provide.
【0006】[0006]
【課題を解決するための手段】本発明の特徴は、ドレイ
ンを第1の電位にゲートを入力端子にソースを出力端子
に接続した一導電型の第1の絶縁ゲート電界効果トラン
ジスタと、ドレインを前記第1の電位にゲートを前記入
力端子に接続した前記第1の絶縁ゲート電界効果トラン
ジスタと同一導電型の第2の絶縁ゲート電界効果トラン
ジスタと、ドレインとゲートを前記第1の絶縁ゲート電
界効果トランジスタのソースに、ソースを第2の電位に
接続した前記第1の絶縁ゲート電界効果トランジスタと
同一導電型の第3の絶縁ゲート電界効果トランジスタ
と、ドレインを前記出力端子にゲートを前記第1の絶縁
ゲート電界効果トランジスタのソースに、ソースを前記
第2の電位に接続した前記第1の絶縁ゲート電界効果ト
ランジスタと同一導電型の第4の絶縁ゲート電界効果ト
ランジスタと、前記出力端子と前記第2の電位に接続し
た容量素子とを含んで構成されたことにある。SUMMARY OF THE INVENTION A feature of the present invention is that a first conductive insulated gate field effect transistor having a drain connected to a first potential, a gate connected to an input terminal, a source connected to an output terminal, and a drain connected to the drain. A second insulated gate field effect transistor of the same conductivity type as the first insulated gate field effect transistor having a gate connected to the input terminal at the first potential, and a drain and a gate connected to the first insulated gate field effect transistor A third insulated gate field effect transistor having the same conductivity type as the first insulated gate field effect transistor having a source connected to a second potential, a drain connected to the output terminal and a gate connected to the first terminal; The source of the insulated gate field effect transistor has the same conductivity as the first insulated gate field effect transistor whose source is connected to the second potential. A fourth insulated gate field effect transistor of the type, in that it has been configured to include a capacitive element connected to the said output terminal and the second potential.
【0007】また、前記第1,第2,第3及び第4の絶
縁ゲート電界効果トランジスタのスレッショルド電圧を
それぞれ0ボルトに設定するとともに、前記第1の絶縁
ゲート電界効果トランジスタよりも前記第2の絶縁ゲー
ト電界効果トランジスタの相互コンダクタンスを大きく
設定し、且つ前記第3の絶縁ゲート電界効果トランジス
タと前記第4の絶縁ゲート電界効果トランジスタの相互
コンダクタンスを等しくなるように設定することができ
る。The threshold voltage of each of the first, second, third and fourth insulated gate field effect transistors is set to 0 volt, and the threshold voltage of the second insulated gate field effect transistor is set to be higher than that of the first insulated gate field effect transistor. The transconductance of the insulated gate field effect transistor can be set to be large, and the transconductance of the third insulated gate field effect transistor and the fourth insulated gate field effect transistor can be set to be equal.
【0008】さらに、前記第2の絶縁ゲート電界効果ト
ランジスタのスレッショルド電圧を0ボルト以上の所定
の電圧に設定することもできる。Further, the threshold voltage of the second insulated gate field effect transistor may be set to a predetermined voltage of 0 volt or more.
【0009】[0009]
【実施例】次に本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0010】図1は本発明の第1の実施例の回路図であ
り、この回路は、ドレインを電源電位(第1の電位)V
DDにゲートを入力端子Vinにソースを出力端子Vou
tに接続した(第1の)N型MOSFETQ1 と、ドレ
インを電源電位VDDに、ゲートを入力端子Vinに、ソ
ースを接続点Aにそれぞれ接続した(第2の)N型MO
SFETQ2 と、ドレインとゲートとを接続点Aに、ソ
ースを接地電位(第2の電位)GNDに接続した(第3
の)N型MOSFETQ3 と、ドレインを出力端子Vo
utに、ゲートを接続点Aに、ソースを接地電位GND
にそれぞれ接続した(第4の)N型MOSFETQ
4 と、出力端子Voutと接地電位GNDの間に接続し
た容量素子Cとによって構成されている。FIG. 1 is a circuit diagram of a first embodiment of the present invention. In this circuit, the drain is connected to a power supply potential (first potential) V
Gate to DD Input terminal Vin to Source Output terminal Vou
The (second) N-type MOSFET Q 1 connected to the N-type MOSFET, the drain is connected to the power supply potential V DD , the gate is connected to the input terminal Vin, and the source is connected to the connection point A.
The SFET Q 2 , the drain and the gate were connected to the connection point A, and the source was connected to the ground potential (second potential) GND (third potential).
) N-type MOSFET Q 3 and drain to output terminal Vo
ut, the gate to the connection point A, the source to the ground potential GND
(Fourth) N-type MOSFET Q connected to
4 and a capacitive element C connected between the output terminal Vout and the ground potential GND.
【0011】この回路の動作波形図を図2に示す。N型
MOSFETのスレッショルド電圧VT を0Vとし、N
型MOSFETQ1 〜Q4 の相互コンダクタンスgm を
それぞれgm1,gm2,gm3,gm4としたとき、gm3=g
m4 gm1がgm2よりもはるかに大きいものとする。FIG. 2 shows an operation waveform diagram of this circuit. The threshold voltage V T of the N-type MOSFET and 0V, N
When the mutual conductances g m of the MOSFETs Q 1 to Q 4 are g m1 , g m2 , g m3, and g m4 , respectively, g m3 = g
Let m4 g m1 be much larger than g m2 .
【0012】入力電圧Vinが出力電圧Voutより大
きいとき、N型MOSFETQ1 は導通状態となって電
流I1 が流れる。また、N型MOSFETQ2 は導通状
態となって電流I2 が流れ、N型MOSFETQ3 ,Q
4 はgm が等しくゲート電圧も等しいためN型MOSE
FETQ4 にも電流I2 が流れる。ここでgm1がgm2よ
りはるかに大きいからI1 も当然I2 より大きな電流と
なり出力電圧VoutはVinまで上昇する。[0012] When the input voltage Vin is higher than the output voltage Vout, N-type MOSFET Q 1 flows a current I 1 becomes conductive. Further, the N-type MOSFET Q 2 becomes conductive and the current I 2 flows, and the N-type MOSFETs Q 3 and Q 3
4 N-type because g m is equal equally gate voltage MOSE
Also current I 2 flows through the FETs Q 4. Here, since g m1 is much larger than g m2, I 1 naturally becomes a current larger than I 2 , and the output voltage Vout rises to Vin.
【0013】次に入力電圧Vinが出力電圧Voutよ
り小さいとき、N型MOSFETQ1 は非導通状態とな
っており、N型MOSFETQ2 は導通状態となって電
流I2 が流れ、N型MOSFETQ4 にも電流I2 が流
れるため容量素子Cの電荷は放電されて出力電圧Vou
tは下がり、Vin=Voutとなると、N型MOSF
ETQ1 が導通状態となってVin=Voutの状態で
安定する。Next, when the input voltage Vin is lower than the output voltage Vout, the N-type MOSFET Q 1 is in a non-conductive state, the N-type MOSFET Q 2 is in a conductive state, and a current I 2 flows, and the N-type MOSFET Q 4 charge of the capacitor C since the current flows I 2 is discharged the output voltage Vou
t decreases and when Vin = Vout, the N-type MOSF
ETQ 1 becomes conductive, and stabilizes in the state of Vin = Vout.
【0014】これにより、どのような入力波形が本実施
例に示すピークホールド回路に入ってきても、ピークホ
ールドを確実に行なうことが出来る。Thus, no matter what input waveform enters the peak hold circuit shown in this embodiment, the peak hold can be reliably performed.
【0015】次に第2の実施例について説明する。Next, a second embodiment will be described.
【0016】第1の実施例と異なるところは、図1に示
した第1の実施例において、N型MOSFETQ2 のス
レッショルド電圧VT を0Vより高く設定することであ
る。[0016] The difference from the first embodiment, in the first embodiment shown in FIG. 1, is to the threshold voltage V T of the N-type MOSFET Q 2 is set higher than 0V.
【0017】通常入力信号Vinにノイズが重畳されて
いた場合、このノイズに対してN型MOSFETQ2 が
応答してしまい、図3に示す波形図のように出力電圧が
変動してしまうが、N型MOSFETQ2 のスレッショ
ルド電圧VT を0Vよりも高い所定の電圧に設定するこ
とで、入力信号Vinにノイズが重畳されていてもノイ
ズの振幅がN型MOSFETQ2 のスレッショルド電圧
VT 以下ならばN型MOSFETQ2 は導通せず、従っ
てN型MOSFETQ4 には電流が流れないため、ノイ
ズによって出力電位が変動することがなくなり、かつ第
1の実施例と同様の効果を得ることが出来る。[0017] When the normal input signal Vin to the noise has been superimposed, will in response have N-type MOSFET Q 2 for this noise, the output voltage as a waveform diagram shown in FIG. 3 fluctuates, N type MOSFET Q 2 of the threshold voltage V T by setting the predetermined voltage higher than 0V, if the amplitude of the noise be superimposed noise on the input signal Vin is N-type MOSFET Q 2 below the threshold voltage V T N type MOSFET Q 2 does not conduct, therefore no current flows in the N-type MOSFET Q 4, it is not possible to vary the output voltage due to noise, and can obtain the same effect as the first embodiment.
【0018】[0018]
【発明の効果】以上説明したように本発明は、ドレイン
を電源電位にゲートを入力端子に接続したN型MOSF
ETQ1 と、ドレインを電源電位にゲートを入力端子に
接続したN型MOSFETQ2 と、ドレインとゲートを
N型MOSFETQ2 のソースにソースを接地電位に接
続したN型MOSFETQ3 と、ドレインを出力端子に
ゲートをN型MOSFETQ3 のゲートとドレインにそ
れぞれ接続し、且つソースを接地電位に接続したN型M
OSFETQ4 と、出力端子と接地電位の間に接続した
容量素子とによって構成するので、入力信号の周波数が
変動してもピークホールド回路の出力信号のピーク値を
保持することが出来るという効果を有する。As described above, the present invention relates to an N-type MOSFET having a drain connected to a power supply potential and a gate connected to an input terminal.
And ETQ 1, the N-type MOSFET Q 2 that a gate connected to the input terminal of the drain to the power supply potential, and the N-type MOSFET Q 3 to the source drain and gate to the source of the N-type MOSFET Q 2 is connected to the ground potential, the output terminal a drain respectively connecting the gate to the gate and drain of the N-type MOSFET Q 3 to and a source connected to a ground potential N-type M
And OSFETQ 4, so constituting the output terminal and a capacitor element connected between the ground potential, an effect that the frequency of the input signal can be held peak value of the output signal of the peak hold circuit be varied .
【図1】本発明の第1の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
【図2】図1に示した第1の実施例の入出力波形図であ
る。FIG. 2 is an input / output waveform diagram of the first embodiment shown in FIG.
【図3】第2の実施例を説明するための入出力波形図で
ある。FIG. 3 is an input / output waveform diagram for explaining a second embodiment.
【図4】従来例の回路図である。FIG. 4 is a circuit diagram of a conventional example.
【図5】図4に示した従来例の入出力波形図である。FIG. 5 is an input / output waveform diagram of the conventional example shown in FIG.
【図6】図4に示した従来例の他の入出力波形図であ
る。FIG. 6 is another input / output waveform diagram of the conventional example shown in FIG.
Q1 〜Q4 N型MOSFET C 容量素子 R 抵抗素子 VDD 電源電位 GND 接地電位 Vin 入力端子 Vout 出力端子Q 1 to Q 4 N-type MOSFET C Capacitance element R Resistance element VDD Power supply potential GND Ground potential Vin Input terminal Vout Output terminal
Claims (3)
子にソースを出力端子し接続した一導電型の第1の絶縁
ゲート電界効果トランジスタと、ドレインを前記第1の
電位にゲートを前記入力端子に接続した前記第1の絶縁
ゲート電界効果トランジスタと同一導電型の第2の絶縁
ゲート電界効果トランジスタと、ドレインとゲートを前
記第1の絶縁ゲート電界効果トランジスタのソースに、
ソースを第2の電位に接続した前記第1の絶縁ゲート電
界効果トランジスタと同一導電型の第3の絶縁ゲート電
界効果トランジスタと、ドレインを前記出力端子にゲー
トを前記第1の絶縁ゲート電界効果トランジスタのソー
スに、ソースを前記第2の電位に接続した前記第1の絶
縁ゲート電界効果トランジスタと同一導電型の第4の絶
縁ゲート電界効果トランジスタと、前記出力端子と前記
第2の電位に接続した容量素子とを含んで構成したこと
を特徴とする半導体集積回路。A first insulated gate field effect transistor having a drain connected to a first potential, a gate connected to an input terminal, a source connected to an output terminal, and a drain connected to the first potential; A second insulated gate field effect transistor of the same conductivity type as the first insulated gate field effect transistor connected to the terminal, and a drain and a gate connected to a source of the first insulated gate field effect transistor;
A third insulated gate field effect transistor of the same conductivity type as the first insulated gate field effect transistor having a source connected to a second potential, and a first insulated gate field effect transistor having a drain at the output terminal and a gate at the output terminal A fourth insulated gate field effect transistor of the same conductivity type as the first insulated gate field effect transistor having a source connected to the second potential, and the output terminal connected to the second potential A semiconductor integrated circuit comprising a capacitor.
ート電界効果トランジスタのスレッショルド電圧をそれ
ぞれ0ボルトに設定するとともに、前記第1の絶縁ゲー
ト電界効果トランジスタよりも前記第2の絶縁ゲート電
界効果トランジスタの相互コンダクタンスを大きく設定
し、且つ前記第3の絶縁ゲート電界効果トランジスタと
前記第4の絶縁ゲート電界効果トランジスタの相互コン
ダクタンスを等しくなるように設定したことを特徴とす
る請求項1に記載の半導体集積回路。2. The threshold voltage of each of the first, second, third, and fourth insulated gate field effect transistors is set to 0 volt, and the second insulated gate field effect transistor is set to a second voltage higher than that of the first insulated gate field effect transistor. The transconductance of the insulated gate field effect transistor is set to be large, and the transconductance of the third insulated gate field effect transistor and the fourth insulated gate field effect transistor are set to be equal. 2. The semiconductor integrated circuit according to 1.
スタのスレッショルド電圧を0ボルト以上の所定の電圧
に設定したことを特徴とする請求項1に記載の半導体集
積回路。3. The semiconductor integrated circuit according to claim 1, wherein a threshold voltage of said second insulated gate field effect transistor is set to a predetermined voltage of 0 volt or more.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4207684A JP2739800B2 (en) | 1992-08-04 | 1992-08-04 | Semiconductor integrated circuit |
EP93112496A EP0582289B1 (en) | 1992-08-04 | 1993-08-04 | Transistor circuit for holding peak/bottom level of signal |
US08/101,731 US5469090A (en) | 1992-08-04 | 1993-08-04 | Transistor circuit for holding peak/bottom level of signal |
DE69306494T DE69306494T2 (en) | 1992-08-04 | 1993-08-04 | Transistor circuit for holding the maximum / minimum value of a signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4207684A JP2739800B2 (en) | 1992-08-04 | 1992-08-04 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0660686A JPH0660686A (en) | 1994-03-04 |
JP2739800B2 true JP2739800B2 (en) | 1998-04-15 |
Family
ID=16543868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4207684A Expired - Fee Related JP2739800B2 (en) | 1992-08-04 | 1992-08-04 | Semiconductor integrated circuit |
Country Status (4)
Country | Link |
---|---|
US (1) | US5469090A (en) |
EP (1) | EP0582289B1 (en) |
JP (1) | JP2739800B2 (en) |
DE (1) | DE69306494T2 (en) |
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FR2728744B1 (en) * | 1994-12-21 | 1997-03-14 | Sgs Thomson Microelectronics | EXTREMUM VOLTAGE SUPPLY CIRCUIT |
TW427051B (en) * | 1998-01-15 | 2001-03-21 | Koninkl Philips Electronics Nv | Peak detection apparatus |
US6140993A (en) * | 1998-06-16 | 2000-10-31 | Atmel Corporation | Circuit for transferring high voltage video signal without signal loss |
US6191621B1 (en) * | 1999-06-15 | 2001-02-20 | Lucent Technologies Inc. | Peak detector |
US7362094B2 (en) * | 2006-01-17 | 2008-04-22 | Allegro Microsystems, Inc. | Methods and apparatus for magnetic article detection |
US8310277B2 (en) * | 2009-08-27 | 2012-11-13 | Qualcomm, Incorporated | High linear fast peak detector |
JP5545751B2 (en) * | 2010-11-25 | 2014-07-09 | 三菱電機株式会社 | Peak hold circuit and bottom hold circuit |
US9520871B2 (en) | 2012-01-05 | 2016-12-13 | Allegro Microsystems, Llc | Methods and apparatus for supply voltage transient protection for maintaining a state of a sensor output signal |
CN103630735B (en) * | 2012-08-27 | 2016-04-13 | 上海占空比电子科技有限公司 | A kind of voltage slope change detection circuit and method |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3694748A (en) * | 1971-07-19 | 1972-09-26 | Hekimian Laboratories Inc | Peak-to-peak detector |
JPH071286B2 (en) * | 1983-12-09 | 1995-01-11 | 日本電信電話株式会社 | Peak value detection circuit |
JPH0787300B2 (en) * | 1985-12-26 | 1995-09-20 | ソニー株式会社 | Peak detection circuit |
IT1232927B (en) * | 1987-10-26 | 1992-03-10 | Sgs Microelettronica Spa | FULL WAVE PEAK DETECTOR DEVICE. |
JP2763778B2 (en) * | 1988-06-20 | 1998-06-11 | 株式会社ユニシアジェックス | Peak value detection circuit |
JP2503598B2 (en) * | 1988-08-08 | 1996-06-05 | 日本電気株式会社 | Peak voltage holding circuit |
JP2856744B2 (en) * | 1988-12-02 | 1999-02-10 | 株式会社東芝 | Peak detection circuit |
JPH02173575A (en) * | 1988-12-27 | 1990-07-05 | Fujitsu Ltd | Peak value holding circuit |
JPH0769355B2 (en) * | 1989-07-17 | 1995-07-26 | 三洋電機株式会社 | Peak detection circuit |
JPH07104370B2 (en) * | 1990-04-13 | 1995-11-13 | ローム株式会社 | Audio signal peak hold circuit |
US5120995A (en) * | 1991-05-29 | 1992-06-09 | Motorola, Inc. | Switched peak detector |
US5254881A (en) * | 1991-09-16 | 1993-10-19 | At&T Bell Laboratories | Master-slave peak detector |
US5315168A (en) * | 1993-04-28 | 1994-05-24 | Fujitsu Limited | Peak hold circuit with improved linearity |
-
1992
- 1992-08-04 JP JP4207684A patent/JP2739800B2/en not_active Expired - Fee Related
-
1993
- 1993-08-04 DE DE69306494T patent/DE69306494T2/en not_active Expired - Fee Related
- 1993-08-04 US US08/101,731 patent/US5469090A/en not_active Expired - Fee Related
- 1993-08-04 EP EP93112496A patent/EP0582289B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69306494T2 (en) | 1997-07-10 |
EP0582289A1 (en) | 1994-02-09 |
JPH0660686A (en) | 1994-03-04 |
DE69306494D1 (en) | 1997-01-23 |
EP0582289B1 (en) | 1996-12-11 |
US5469090A (en) | 1995-11-21 |
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A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19971224 |
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LAPS | Cancellation because of no payment of annual fees |