JPH071286B2 - Peak value detection circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit for detecting a peak value of a digital code, and more particularly to a peak value detection circuit suppressing a detection output fluctuation due to a code pattern density (mark ratio) fluctuation. Is.

Conventional Technology and Problems Conventionally, as a peak value detection circuit, an example of which is shown in FIG. 1 is provided between an input side and an output side emitter follower circuit according to input levels “H” and “L”. An emitter follower type peak value detection circuit that charges a capacity and has a sufficiently long discharge time constant is used.

In Fig. 1, Q ₁ , Q ₂ , and Q ₃ are NPN transistors and R ₁ and R, respectively.
₂ is a resistor, C is a capacitor, V _CC and V _EE are power supplies, and I1 and O1 are input and output terminals, respectively. In FIG. 1, the transistors Q ₁ and Q ₃ each operate as an emitter follower. The transistor Q ₂ is driven by the emitter output of the transistor Q ₁ , but since the capacitor C is added between the emitter of the transistor Q ₂ and the ground terminal, the input signal applied to the input terminal I 1 becomes “H”. , The capacitor C is charged via the transistor Q ₂ .

On the other hand, the supply is stopped for the input signal changes from "H" to "L" charge from the transistor Q _2, the electric charge of the capacitor C is discharged as a base current of the transistor Q _3. However the input impedance of the transistor Q ₃ are large discharge time constant so very high, slave connexion transistor Q ₃
Since the base potential of is gradually decreased, the output terminal O1 holds the output level when the "H" level is applied to the input,
With this, the peak value can be detected.

However, in this circuit, since only the capacitor C and the base of the transistor Q ₃ are connected to the emitter of the transistor Q ₂ , in the steady state, the transistor Q ₂ has a very small emitter current (Ie) of about several microamperes. Only flowing. In accordance connexion input signal is "H" several hundred mV also its level reaches the level amplitude, the transistor Q ₂ is a very low ability to charge this by driving a capacitance C. Especially when the mark ratio of the input signal is low, the discharge time is relatively longer than the charge time for the capacitor C, so that the terminal voltage of the capacitor C decreases, and therefore the detection output level at the output terminal O1 decreases. .

As described above, the conventional peak value detection circuit has a drawback that the detection output level fluctuates greatly due to the fluctuation of the mark ratio of the input signal.

OBJECT OF THE INVENTION The present invention is intended to solve such a problem of the prior art, and its object is to prevent the detection output level from varying due to the variation of the mark ratio of the input signal. It is to provide a detection circuit.

The peak value detection circuit of the present invention controls the current of the driving transistor according to the level of the input signal in order to increase the driving capability of the driving transistor that charges the capacitor for holding the peak value of the digital code. The current switching circuit is added to the driving transistor.

Embodiment of the Invention FIG. 2 shows the configuration of an embodiment of the peak value detection circuit of the present invention. In the figure, the same parts as in FIG. 1 are indicated by the same numbers, and Q ₄ and Q ₅ are NPN transistors and D
₁ , D ₂ is a diode, R ₃ is a resistor, _IE is a constant current circuit, and V _B is a reference power source.

In Fig. 2, transistors Q ₄ , Q ₅ and constant current circuit _IE
Constitutes a current switching circuit, and depending on which of the base potentials of transistors Q ₄ and Q ₅ is higher, transistor Q ₄ or
Supplies a constant current by connexion determined to the constant current circuit I _E to Q _5. On the other hand, a constant voltage circuit constituted by the diodes D ₁ and D ₂ is connected between the emitter of the transistor Q ₁ and the base of the transistor Q ₄ , and the level of the input terminal I1 is “H” or According to being "L", the transistor Q ₄
Compared to base reference power supply V _B of such a high potential or a low potential, the reference power source V _B and the constant voltage circuit D _1, D ₂ is selected.

Therefore, when the input signal is "H" level, the transistor
Q ₄ becomes non-conductive and Q ₄ becomes conductive.
In this way, the difference between the current flowing through the transistor Q ₂ when charging the capacitor C and the conventional example shown in FIG. 1 will be described. In the conventional example of FIG. 1, only the input signal path (a) to the base of the transistor Q ₃ and the path (b) to the capacitor C are connected to the emitter of the transistor Q ₂ . On the other hand, in FIG. 2 which is one embodiment of the present invention, since the transistor Q ₄ becomes conductive, the current path is further parallel to the paths (a) and (b) through the transistor Q ₄ . The emission current Ie can be increased because the emission current Ie is increased. Furthermore, the transistor Q ₄ is
I connexion determined current flows to the constant current source I _E, Yotsute the value of the constant current source I _E, may be greater than the emitter current of the transistor Q ₂ in readily conventional configuration of FIG. 1.
On the other hand, as is well known as the basic characteristic of the transistor, the emitter resistance r _e of the transistor Q ₂ is qualitatively shown by the following equation.

Here, k is the Boltzmann constant, T is the absolute temperature, q is the electron charge, and I _e is the emitter current. From this relationship, the emitter resistance r _e of the transistor Q ₂ decreases as the emitter current I _e increases. Yotsute thereto, the charging of the capacitor C can be regarded as the time constant of the integrating circuit to a time constant r _e × C.

Therefore, the time constant can be made smaller than that in FIG. 1 of the conventional example, so that the rise of charging becomes faster, and a remarkable effect that speeding up can be achieved.

On the other hand, Q ₄ together with the transistor Q ₅ when the input signal changes from "H" to "L" becomes conductive becomes nonconductive. Therefore, the discharge path of the charge in the capacitor C is only through the base of the transistor Q ₃ , and the discharge time constant is not different from that in the conventional circuit shown in FIG.

As described above, in the peak value detection circuit shown in FIG. 2, the rising speed at the time of charging becomes faster, so that the capacitor C is sufficiently charged, the peak value detection level becomes more accurate, and the mark ratio of the input signal becomes higher. The fluctuation of the detection level when the value is decreased is suppressed.

FIG. 3 shows an example of a result obtained by the computer simulation for the peak value detection level when the mark ratio is changed in the circuits of FIGS. 1 and 2. In the figure, the peak value detection level fluctuation when the mark rate changes is based on the detection level when the mark rate is 1/2, and the peak value detection level variation is shown in FIG. 1 (1) and FIG. 2 (2). shows the preparative, circuit parameters used in Shimiyureshiyon in this _{case, V CC = 6V, V EE} = 0, V B = 3.1V, I E = 1mA, C = 100PF, R 1 = 4.7KΩ, R ₂ = 20K Ohms, a R ₃ = 3KΩ, are the current amplification factor h _FE = 100 for each transistor. The input signal is 5.5 ± 0.15V.

From the results of FIG. 3 as well, it is clear that the peak value detection circuit of the present invention has a great effect of suppressing the fluctuation of the detection level, especially when the mark ratio is lowered.

EFFECTS OF THE INVENTION As described above, according to the present invention, by increasing the current of the drive transistor of the peak value holding capacitor when the input signal is at the “H” level, it is possible to have a remarkably higher detection capability than the conventional circuit. Since it is possible, there is an effect of suppressing the fluctuation of the detection level with respect to the fluctuation of the mark rate in the digital transmission. Specifically, it can be applied to an equalizing and amplifying circuit of a digital transmission type repeater.

[Brief description of drawings]

FIG. 1 is a conventional emitter-follower type peak value detection circuit, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG.
It is a figure which shows an example of the mark rate dependence of the peak value detection level variation in the conventional circuit and the circuit of the Example of this invention. Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ …… NPN transistor, D ₁ , D ₂ ……
_{Diodes, R 1, R 2, R} 3 ...... resistance, C ...... capacitor,
I _E …… Constant current circuit, V _CC , V _EE …… Power supply, V _B …… Reference voltage, I1 …… Input terminal, 1 …… Output terminal, 1 …… Conventional circuit peak value detection level, 2 …… The peak value detection level of the circuit of one embodiment of the present invention.

Claims (1)

[Claims] 1. A first transistor circuit forming an emitter follower connected between a first power supply and a second power supply, and an emitter of the first emitter follower circuit having a collector connected to the first power supply. The output is used as a base input, and the emitter output of the second transistor circuit connected between the first power supply and the second power supply and the second transistor circuit connected between the grounded emitter and the capacitor is used as the input. In a peak value detection circuit including a second emitter follower circuit, a constant voltage level shift circuit for level-shifting an emitter voltage by a predetermined amount between the emitter and the emitter load of the first emitter follower circuit and applying the voltage to the emitter load. And a collector connected to the emitter of the second transistor circuit, and the collector of the first emitter follower circuit is connected. Of the fourth transistor whose base input is the output of the load and the collector of which is connected to the first power supply and the emitter of the fifth transistor whose base input is the reference voltage are connected to form a second constant current circuit. A peak value detection circuit, which is provided with a current switching circuit connected to the power source.