JP2739798B2 - Program loading device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program loading device and, more particularly, to a program loading device having a plurality of types of programs to be loaded.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional program loading apparatus comprises an upper panel 3 and a plurality of lower panels 4a.
To 4c. Lower panels 4b and 4c
Has the same internal configuration as that of the lower panel 4a, and is not shown.

The upper panel 3 includes a monitoring CPU 31 for monitoring the entire apparatus and a memory 32 accessed by the monitoring CPU 31. The lower panel 4a includes a CP.
U43 and the memory 42 accessed by the CPU 43
And a dual port memory 41 accessed by the CPU 43.

The monitoring CPU 31 of the upper panel 3 accesses the dual-port memory 41 of the lower panels 4a to 4c via a bus, and the monitoring CPU 31 and the CPU 43 communicate with each other via the dual-port memory 41. Lower-level panel 4a
4c was loaded into the memory 42.

[0005]

In this conventional program loading device, the monitoring CPU accessing the load source memory in the upper panel communicates directly with the CPU accessing the load destination memory in the lower panel. When there are two types of programs to be loaded, it is necessary for the monitoring CPU to select the program to be loaded and then to select the loading destination CPU, which complicates the operation of the monitoring CPU on the upper panel. There was a point.

Further, since it is necessary to allocate the memory space of the CPU to the memory space of the monitoring CPU, there is a problem that the memory space of the monitoring CPU of the upper panel is increased.

[0007]

According to the present invention, there is provided a program loading apparatus comprising: a high-level panel having a monitoring CPU for monitoring the entire apparatus, a first memory accessed by the monitoring CPU and holding a plurality of programs; A first dual-port memory into which first and second programs read out by the monitoring CPU from among the plurality of programs held in the first memory are written, and via the first dual-port memory, A first CPU that communicates with a monitoring CPU, a second memory that is accessed by the first CPU and into which one of the first and second programs is written, and a first CPU
A second dual-port memory accessed by the second CPU, a second CPU communicating with the first CPU via the second dual-port memory, and the first and second memories accessed by the second CPU. And a third memory having a third memory in which a program not written in the second memory is written.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, the program for the MAIN-CPU 23 is referred to as a program 5, and the program for the SUB-CPU 26 is referred to as a program 6. In this embodiment, the program 5 is loaded from the memory 12 to the memory 22,
The operation when the program 6 is loaded from the memory 21 to the memory 25 will be described.

The program loading device comprises an upper panel 1 and a plurality of lower panels 2a to 2c. The internal configuration of the lower panels 2b and 2c is the same as that of the lower panel 2a, so that the illustration is omitted.

In the upper panel 1, there are a monitoring CPU 11 for monitoring the entire apparatus and a load source memory 12 accessed by the monitoring CPU 11, and a program 5 and a program 6 are held in the memory 12. . Monitoring C
The PU 11 stores the program 5 and the program 6 in the memory 12
And writes to the dual port memory 21 in the lower panel 2a via the bus.

The lower panel 2a includes a dual port memory 21, a MAIN-CPU 23 communicating with the monitoring CPU 11 via the dual port memory 21, a memory 22 accessed by the MAIN-CPU 23,
Similarly, a dual port memory 24 accessed by the MAIN-CPU 23 and a SUB-CPU 26 communicating with the MAIN-CPU 23 via the dual port memory 24
And the memory 25 accessed by the SUB-CPU 26
There is.

The MAIN-CPU 23 reads the program 5 and the program 6 from the dual port memory 21, writes the program 5 into the memory 22,
Is written to the dual port memory 24, and the SUB-CP
U 26 reads program 6 from dual port memory 24 and writes program 6 to memory 25.

[0014]

As described above, according to the present invention, when there are two types of programs to be loaded, the loading between the monitoring CPU of the upper panel and the first CPU of the lower panel is performed via the first dual port memory. Two kinds of programs are simultaneously executed, and one of the two kinds of programs is loaded between the first CPU and the second CPU in the lower panel via the second dual port memory. Therefore, the operation of the monitor CPU of the upper panel is simplified, and the memory space of the monitor CPU of the upper panel can be reduced because the memory space of the second CPU does not need to be allocated to the memory space of the monitor CPU. Have.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional program loading device.

[Explanation of symbols]

 1 Upper Panel 2 Lower Panel 11 Monitoring CPU 12, 22, 25 Memory 21, 24 Dual Port Memory 23 MAIN-CPU 26 SUB-CPU

Claims (1)

(57) [Claims] An upper panel including a monitoring CPU for monitoring the entire apparatus, a first memory accessed by the monitoring CPU and holding a plurality of programs, and an upper panel including a plurality of programs held in the first memory. A first dual-port memory into which the first and second programs read out by the monitor CPU are written, and the monitor C through the first dual-port memory.
A first CPU that communicates with a PU, a second memory accessed by the first CPU and in which one of the first and second programs is written,
A second CPU connected to the second CPU, a second CPU communicating with the first CPU via the second dual port memory, and a second CPU
A plurality of lower panels including a third memory accessed by a PU and into which a program of the first and second programs not written to the second memory is written. Program loading equipment.