JP2733620B2 - Inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to an inspection apparatus for testing, for example, a semiconductor wafer, and more particularly to a communication method between a plurality of computers mounted on the inspection apparatus.

[Prior art]

A wafer prober for testing a semiconductor wafer, which is an inspection apparatus of this type, includes a measurement stage, a loader, an unloader, a handling arm, and the like, and includes a plurality of computers for controlling each unit. Then, one of the computers is used as a master and the other is used as a slave to communicate with each other to perform desired processing and control. As described above, when a plurality of slaves are provided for one master, when a predetermined signal is transmitted from the plurality of slaves to the master, it is determined from which slave the predetermined signal is transmitted. Conventionally, it is common to connect each of a master and each of a plurality of slaves with a separate communication line so that the information can be easily known. For example, when a plurality of slaves send an interrupt request signal to a master having a computer that executes a predetermined program to execute interrupt processing corresponding to the interrupted slave, generally, an interrupt line is generally It is provided between each slave and the master. When an interrupt request signal is sent from any slave to the master, it is not known as to which slave sent the interrupt request signal as it is, so the master returns a response signal to the slave, etc.
A predetermined signal is exchanged with the slave to know from which slave the interrupt request comes.

[Problems to be solved by the invention]

However, when the master and the slave are connected by individual communication lines as described above, the number of signal lines increases as the number of slaves increases, which is not preferable in terms of wiring space and the like. As described above, for example, when an interrupt is performed,
Conventionally, in order to know which one of a plurality of slaves is the interrupt from the above-mentioned interrupt sequence, it was necessary to exchange signals such as sending a response signal from the master to the slave. However, there is a disadvantage that it cannot be performed at high speed. In view of the above points, the present invention provides an inspection apparatus that employs a communication method that allows a communication signal line such as an interrupt line to be shared by a plurality of slaves to reduce the number of signal lines and that can omit an interrupt sequence compared to the related art. The purpose is to do.

[Means for Solving the Problems]

An inspection apparatus according to the present invention includes: a first master unit for managing an operation of a first stage for inspection on which an object to be inspected is mounted; and a second master unit for inspection on which the object to be inspected is mounted. A second master unit for managing the operation of the stage, a third master unit for managing the loading and unloading operations of the test object, and a fourth master unit for managing the entire apparatus A first X, Y-direction slave unit for controlling the movement of the first stage in the two-dimensional plane for positioning the object to be inspected in the two-dimensional plane; A first rotation direction slave unit that controls the rotation of the first stage for alignment of the inspection object in the rotation direction, and an alignment of the inspection object in the two-dimensional plane, Controlling movement of the second stage in the two-dimensional plane. A second X- and Y-direction slave unit to be controlled, a second rotation-direction slave unit that controls rotation of the second stage for alignment of the inspection object in the rotation direction, A loading slave unit for controlling a loading operation of the inspection object; an unloading slave unit for controlling an unloading operation of the inspection object; and controlling an operation of a handling arm used when loading and unloading the inspection object. A handling arm slave unit, a bus for connecting the first to fourth master units, the first master unit, the first X, Y direction slave unit, and a first rotation unit. A first local bus connecting between the direction slave unit and at least one common signal communication line and one common clock line; At least one common signal communication line and one common signal line connecting between the second master unit and the second X, Y direction slave unit and the second rotational direction slave unit. A second local bus composed of a clock line, a third master unit, and a connection between the loading slave unit, the unloading slave unit, and the handling arm slave unit. And a third local bus consisting of one signal communication line and one common clock line, wherein each of the slave units is driven by a clock through the clock line and connected to each local bus. Timing forming means for forming different communication timings in the slave section, and the signal communication is performed by the timing from the timing forming means. Communication control means for transmitting a predetermined signal to the master unit side via the signal communication line when the first master unit is empty, wherein each of the first to third master units includes a clock through the clock line. Means for detecting the communication timing of each of the plurality of slave units respectively connected to the first to third local buses, and receiving a signal transmitted through the signal communication line to perform predetermined processing. Receiving means for performing the following.

[Action]

Communication (eg, interrupt) timing is made different between a plurality of slave units connected to a common local bus. Therefore, even if a single communication signal line is used, communication signals (such as interrupts) are transmitted from the plurality of slave units. For example, an interrupt request signal) is not transmitted at a timing overlapping the common signal line. Further, since the communication timing of each of the plurality of slave units connected to the common local bus can be detected by the detection unit of the master unit, the master unit can immediately know which slave unit has transmitted the signal. it can. Therefore, quick interrupt processing can be performed. Thereby, the plurality of stages of the inspection device operate efficiently and smoothly.

【Example】

Hereinafter, a case where an embodiment of the present invention is applied to a wafer prober will be described as an example. FIG. 2 shows an overall configuration diagram of a control circuit system of the wafer prober. In this example, a first stage and a second stage are provided so that two wafers can be processed simultaneously. 10 is a master CPU for managing the entire system, 20 is a master CPU for managing the operation in the first stage, 30 is a master CPU for managing the loading operation, and 40 is an operation for managing the operation in the second stage. Master CPU for The master CPUs 10, 20, 30, and 40 are connected in a general multi-bus format in this example. Local buses 21, 3 for master CPUs 20, 30, 40
1 and 41 are connected, and C is connected to each of these local buses 21, 31, and 41.
A plurality of slaves such as PUs are connected. The local buses 21, 31, and 41 include a data bus, a clock line common to a plurality of slaves connected thereto, a common interrupt line, and a reset line, as shown in FIG. In. As slaves, the local buses 21 and 41 of the first stage and the second stage are, for example, the CPU 22 for the X-direction and Y-direction drive motors for wafer alignment, respectively.
The tester interfaces 24 and 44 provided between the CPU 42 and the drive motor CPUs 23 and 43 in the Z and θ directions (wafer rotation direction) and an external tester are connected. GPIB interfaces 25 and 45 and RS-232-C interfaces 26 and 46 for performing communication with the PC are connected. Further, motor CPUs 32 and 33 for loading and unloading wafers and a CPU 34 for a handling arm drive motor are connected as slaves to the local bus 31 of the loader. For example, the operation between the master and the slave will be described by taking as an example the case where wafer positioning is performed in the first stage. First, X, Y,
The data for each direction of Z and θ is transferred to each slave CPU2.
Send to 2 and 23. Next, a start command is sent to the slave CPUs 22 and 23 via, for example, a common command line (data line). When each of the slave CPUs 22 and 23 receives the start command, the slave CPUs 22 and 23 send a signal for driving the motor to the motor by an amount corresponding to each direction transfer amount data transmitted in advance. When the movement for the given amount of data is completed in each direction, the slave CPUs 22 and 23
An interrupt request is sent to 20. On the other hand, at the first movement completion position, the positioning error data has been sent to the master CPU 20, and upon receiving the interrupt request, the master CPU 20 then determines the direction of the interrupt request based on the difference data. Of the second transfer amount data is executed.
Then, the result is sent to the slave CPU that has issued the interrupt via the data bus. In this way, the master CPU detects the interrupt request from each slave CPU as the end of the transfer in that direction, executes an interrupt program for calculating the required transfer amount, and repeats this several times to reach the target position. Try to align the wafer. In this case, since only one common interrupt line is used between the plurality of slaves and the master, the present invention is devised so that the interrupt request timings from the plurality of slaves do not overlap. That is, FIG. 1 shows an example of a circuit on the master side and a slave side for performing this interrupt timing control. An interrupt line 71 for communication of an interrupt request signal is provided between the master 50 and a plurality of slaves 60. And the clock line 72,
The reset line 73 is connected. The interrupt line 71, clock line 72, and reset center 73 are common to a plurality of slaves. In this example, each slave 60 is provided with a hexadecimal counter 61 in order to determine the output timing of the interrupt request signal of the slave. The initial value (load value) of the counter 61 is set to be different for each slave. The load value is set by the dip switch 62, and the set load value is stored in the ID register 63. This load value becomes the ID (identification signal) of each slave. Therefore, in this example, 16 slaves can be connected to one master. The recorded value of the ID register 63 is sent to the interrupt sequence controller 64. The clock CK is supplied to the hexadecimal counter 61 of each slave 60 from the master 50 through the clock line 72. Also,
A counter reset signal RS is supplied from the master side to the reset terminal of the counter 61 and to the ID register 63 via the reset line 73. When the counter reset signal RS is supplied to the counter 61, the stored value of the ID register 63 is loaded into the counter 61 via the interrupt sequence controller 64, and the counter 61
Starts counting hexadecimal numbers from the load value at the time of reset. The interrupt sequence controller 64 is a hexadecimal counter
It recognizes that the time when the count value of 61 becomes “0” is the interrupt request signal output timing. Then, when an interrupt request such as when the movement of the motor is completed is input to the controller 64, an interrupt request signal is output to the interrupt line 71 at the timing when the count value of the counter 61 is "0". In this case, the output of the interrupt request signal from the slave is performed by lowering the high-level interrupt line 71 to a low level. On the other hand, on the master 50 side, a hexadecimal counter 51 is provided as a means for detecting the interrupt request signal output timing of each slave, and a clock CK sent via the clock line 72 is supplied to this counter 51. Therefore, the counter 51 increments the count value in synchronization with the counter 61 of each slave 60. The counter 51 of the master 50 is controlled by the counter reset signal RS transmitted through the reset
It is reset in synchronization with the counter 61 of 60. Therefore, each of the count values of the counter 51 of the master 50 is
It corresponds to each interrupt request signal output timing of the plurality of slaves 60, and by referring to the count value of the counter 51 when the interrupt request signal arrives, it is possible to determine from which slave the interrupt request signal is issued. The master 50 can immediately detect it. Therefore, the count value of the counter 51 is sent to the master CPU via the data bus. An interrupt controller provided on the master 50 side
52 (may be the master CPU itself)
When an interrupt request is made low, the interrupt line 71 is held low and the master CP
U detects from the count value of the counter 51 which slave the interrupt is from, and sends an interrupt program corresponding to the detected slave to the master CPU.
Run with When the interrupt program ends, the master CPU returns to the original processing program, sets the interrupt line 71 to high level by the interrupt controller 52, and sets the interrupt ready state (READY). FIG. 3 shows an example of an interrupt request signal output timing from the slave. In this example, the clock CK supplied to the slave via the clock line 72 is as shown in FIG.
For example, its frequency is 5 MHz. Then, at the timing of the counter reset signal RS shown in FIG. B, the count value of the counter 61 of a certain slave is loaded to “6” as shown in FIG. Therefore, this counter 61
Is the clock CK from the count value “6” from the time of reset.
Is incremented, and the 4-bit count value output QA, Q
B, QC, and QD are as shown in FIGS. Now, as shown in FIG. 3J, it is assumed that when the interrupt line 71 is at the low level, an interrupt request arrives at the interrupt sequence controller 64 at the slave having the timing shown in FIG. 3H. Interrupt line 71
Is low when the master is performing interrupt processing for another slave, the interrupt sequence controller 64 uses the interrupt output enable signal (FIG. 3I) to count the counter 61 (FIG. 3). Even if C) becomes "0", the interrupt request signal is not output and is postponed. Then, when the interrupt program by the interrupt of the other slave in the master 50 ends, the interrupt line 71 is set to the high level by the interrupt controller 52 as shown in FIG. 3J. Then, in the interrupt sequence controller 64 of the slave 60, the interrupt output enable signal (FIG. 3I) becomes low level, and the interrupt output is enabled. When the count value of the slave 61 becomes “0” in this state, an interrupt request signal is output to the interrupt sequence controller 64. Upon receiving this interrupt request, the interrupt controller 52 of the master 50
From this point, and the master CPU
The slave which interrupted is detected by referring to the count value data of the counter 51, and an interrupt processing program corresponding to the slave is executed. When the interrupt processing program ends, the master CPU returns to the original program processing, and the interrupt controller 52 sets the interrupt line 71 to a high level state. As described above, since the plurality of slaves have different interrupt request signal output timings, even if the interrupt line 71 is common, the interrupt request signals from the plurality of slaves 60 are simultaneously transmitted to the master 50. No duplicates are sent. Moreover, since the master 50 is provided with means for detecting each interrupt output timing of each slave 60, when an interrupt request signal is actually sent from any slave to the master, the interrupt means is detected by the detecting means. Only by detecting the timing, it is possible to detect which slave has issued the interrupt request. For this reason, it is possible to omit the exchange of signals at the time of interruption, such as returning a response signal from the master, in response to an interruption request from the slave as in the related art, and to perform a quick interruption. In the above example, a CPU may be provided on the slave side, or the CPU may not be provided and the completion of a predetermined operation may be supplied to the interrupt sequence controller 64 as an interrupt request. . In the above description, the interrupt request signal is taken as an example of the communication signal. Therefore, although the CPU is provided on the master side, the present invention can be applied to other than the communication of the interrupt request signal. Of course, in this case, it is not necessary to provide CPUs on both the master side and the slave side.

【The invention's effect】

As is apparent from the above description, according to the present invention,
Since a plurality of slaves have different communication output timings from each other, even when a communication line is common between the master and the plurality of slaves, a situation in which transmission signals are simultaneously transmitted from the plurality of slaves to the master is impossible. Does not occur. Therefore, a large number of slaves can be connected to one master with a small number of lines, and communication can be performed between them. In addition, since the master side is provided with a means for detecting each communication timing of each slave, when a transmission signal is actually sent from any slave to the master, the detection means detects the transmission timing. It is possible to detect from which slave the signal is transmitted. For this reason, exchange of signals at the time of interruption, such as returning a response signal from the master in response to an interrupt request from the slave as in the related art, can be omitted, and quick interruption can be performed. Therefore, according to the inspection apparatus of the present invention, the plurality of stages can be operated efficiently and smoothly, and the inspection speed and inspection efficiency can be increased. Further, according to the present invention, since the communication signal line is not provided for the master for each slave but is common,
There is also an advantage that when a communication interface such as RS-232-C or the like is later connected to the master as a slave, the connection can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, and FIG.
FIG. 3 is a block diagram showing an example of the configuration of a control system of a wafer prober to which the present invention is applied, and FIG. 3 is a timing chart for explaining the operation of the example of FIG. 50; Master 60; Slave 51, 61; Counter 52; Interrupt controller 64; Interrupt sequence controller 71; Interrupt line 72; Clock line 73; Reset line

Claims (1)

(57) [Claims] 1. A first master unit for managing an operation of a first stage for inspection on which an object to be inspected is mounted, and a second stage for inspection on which the object to be inspected is mounted. A second master unit for managing the operation of the device, a third master unit for managing the loading and unloading operations of the device under test, a fourth master unit for managing the entire apparatus, For alignment of the test object in a two-dimensional plane,
A first X- and Y-direction slave unit for controlling the movement of the first stage in the two-dimensional plane; and a rotation of the first stage for positioning the object to be inspected in a rotational direction. A first rotation direction slave unit that controls the movement of the object to be inspected in the two-dimensional plane; A slave unit for the X and Y directions, a second slave unit for the rotation direction for controlling rotation of the second stage for positioning in the rotation direction of the test object, and loading of the test object. A loading slave unit for controlling an operation; an unloading slave unit for controlling an unloading operation of the device under test; and a movement of a handling arm used during loading and unloading of the device under test. A slave unit for controlling a handling arm, a bus for connecting the first to fourth master units, the first master unit, the first X and Y direction slave units and the first A first local bus connecting at least one common signal communication line and one common clock line, connecting the second master unit; A second local bus connecting at least two X and Y direction slave units and a second rotation direction slave unit and including at least one common signal communication line and one common clock line. And at least one common signal communication line and common connection for connecting the third master unit with the loading slave unit, the unloading slave unit and the handling arm slave unit. A third local bus comprising one clock line, wherein each of the slave units is driven by a clock through the clock line and communicates differently with the plurality of slave units connected to each local bus. Timing forming means for forming timing, and communication control means for transmitting a predetermined signal to the master unit side via the signal communication line when the signal communication line is vacant with the timing from the timing forming means. Wherein each of the first to third master units is driven by a clock through the clock line, and
A means for detecting the communication timing of each of the plurality of slave units connected to the third local bus, and a receiving means for performing a predetermined process in response to a signal sent through the signal communication line. An inspection device characterized by the above-mentioned.