JPH0229844A - Interruption control system for input/output device - Google Patents

Interruption control system for input/output device

Info

Publication number
JPH0229844A
JPH0229844A JP18223888A JP18223888A JPH0229844A JP H0229844 A JPH0229844 A JP H0229844A JP 18223888 A JP18223888 A JP 18223888A JP 18223888 A JP18223888 A JP 18223888A JP H0229844 A JPH0229844 A JP H0229844A
Authority
JP
Japan
Prior art keywords
input
output device
interrupt
control
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18223888A
Other languages
Japanese (ja)
Inventor
Makoto Kikuchi
誠 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HOKKAIDO NIPPON DENKI SOFTWARE KK
NEC Solution Innovators Ltd
Original Assignee
HOKKAIDO NIPPON DENKI SOFTWARE KK
NEC Software Hokkaido Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HOKKAIDO NIPPON DENKI SOFTWARE KK, NEC Software Hokkaido Ltd filed Critical HOKKAIDO NIPPON DENKI SOFTWARE KK
Priority to JP18223888A priority Critical patent/JPH0229844A/en
Publication of JPH0229844A publication Critical patent/JPH0229844A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE:To prevent the number of I/O devices to be connected to a CPU from being restricted by the number of interruption signal lines in an I/O bus of an electronic computer system by controlling plural I/O devices through one interruption signal line at the time of using the plural I/O devices. CONSTITUTION:An I/O device registering means 4 checks the existence of I/O devices 3a to 3n to use a specific interruption signal line 2' in the I/O bus 2 and registers information relating to I/O device control means 7a to 7n in an I/O device information registering means 5. When an interruption signal from any one of the devices 3a to 3n is generated in the signal line 2', an interruption control starting means 6 successively checks whether an interruption signal is generated or not from the I/O devices 3a to 3n, and at the time of detecting the I/O device generating the interruption, transfers processing to interruption control based upon the I/O control means concerned out of the I/O device control means 7a to 7n. Thus, the interruption control of the plural I/O devices can be executed by one interruption signal line 2'.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子計算機システムにおいて入出力装置を複
数使用する際の割込制御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method when a plurality of input/output devices are used in an electronic computer system.

〔従来の技術〕[Conventional technology]

従来、電子計算機システムにおける入出力装置の割込制
御は、第4図に示すように、各入出力装置毎に入出力バ
ス上の独立した割込信号線を使用し、割込発生時に割込
制御装置から割込を検出した割込信号線の情報を引き取
ることにより、各入出力装置からの割込を独立した割込
として識別し、該当入出力装置制御手段の割込制御を起
動するという方式となっていた。
Conventionally, interrupt control of input/output devices in computer systems uses independent interrupt signal lines on the input/output bus for each input/output device, and interrupts are sent when an interrupt occurs, as shown in Figure 4. By receiving information on the interrupt signal line where an interrupt is detected from the control device, the interrupt from each input/output device is identified as an independent interrupt, and interrupt control of the corresponding input/output device control means is activated. It was a method.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の割込制御方式では、入出力装置毎に異な
る割込信号線を使用するために、中央処理装置に接続可
能な入出力装置の数が電子計算機システム内の入出力バ
ス中の割込信号線の本数により制限されるという問題が
ある。
In the conventional interrupt control method described above, different interrupt signal lines are used for each input/output device. There is a problem in that it is limited by the number of integrated signal lines.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、中央処理装置と、割込発生機能を持つ
入出力装置と、前記中央処理装置と前記入出力装置とを
結ぶ入出力バスとにより構成される電子計算機システム
において、前記入出力装置からの割込を制御する入出力
装置制御手段と、前記入出力装置の割込信号線情報を規
定した入出力装置情報を生成する登録手段と、前記入出
力装置からの割込信号により対応する割込制御を起動す
る手段とを有し、同一割込信号による入出力割込の制御
を可能としたことを特徴とする電子計算機システムにお
ける入出力装置の割込制御方式が得られる。
According to the present invention, in an electronic computer system including a central processing unit, an input/output device having an interrupt generation function, and an input/output bus connecting the central processing unit and the input/output device, the input/output An input/output device control means for controlling interrupts from the device, a registration means for generating input/output device information specifying interrupt signal line information of the input/output device, and an interrupt signal from the input/output device. According to the present invention, there is provided an interrupt control method for an input/output device in a computer system, which is characterized in that it has a means for activating interrupt control to perform interrupt control, and is capable of controlling input/output interrupts using the same interrupt signal.

〔実施例〕〔Example〕

次に、本発明の一実施例を示した図面を参照して、本発
明をより詳細に説明する。
Next, the present invention will be described in more detail with reference to the drawings showing one embodiment of the present invention.

第1図を参照すると、本発明の一実施例は、中央処理装
置1と、入出力バス2と、入出力バス中の割込信号線2
′と、入出力装置3a、3b、・・・・・・3nとを有
している。
Referring to FIG. 1, one embodiment of the present invention includes a central processing unit 1, an input/output bus 2, and an interrupt signal line 2 in the input/output bus.
', and input/output devices 3a, 3b, . . . 3n.

中央処理装置1は、入出力装置3a〜3nに関する情報
を登録する入出力装置登録手段4と、同一割込信号線を
使用する入出力装置に関する入出力装置情報らと、割込
発生時に割込を発生した入出力装置を識別し該当入出力
装置の割込制御を起動する割込制御起動手段6と、入出
力装置3a〜3nの制御を行なう入出力装置制御手段7
 a +7b・・・・・・7nとを有する。
The central processing unit 1 includes an input/output device registration means 4 that registers information regarding the input/output devices 3a to 3n, input/output device information regarding the input/output devices that use the same interrupt signal line, and an input/output device registering unit 4 that registers information regarding the input/output devices 3a to 3n. interrupt control activation means 6 that identifies the input/output device that has generated the error and activates interrupt control for the corresponding input/output device; and input/output device control means 7 that controls the input/output devices 3a to 3n.
a +7b...7n.

入出力装置登録手段4は、電子計算機システムの初期化
を行なう際に入出力バス2中の特定の割込信号線2′を
使用する入出力装置3a〜3nの有無の確認を行なうと
ともに、該当入出力装置3a〜3nの情報および入出力
装置制御手段7a〜7nに関する情報を入出力装置登録
手段5へ登録する・。入出力装置3a〜3nの登録が終
了し、入出力バス2の特定の割込信号線2′上に入出力
袋W3a〜3nのいずれかからの割込信号が発生した際
には、中央処理装置が割込制御起動手段6を起動する0
割込制御起動手段では、入出力装置情報5に登録されて
いる入出力装置3a〜3nについて、割込をしたか否か
を順に確信してゆき、割込を発生した入出力装置を発見
した時点で、入出力制御手段7a〜7nのうちの該当入
出力装置の割X制御へ処理を移す。
The input/output device registration means 4 checks the presence or absence of input/output devices 3a to 3n that use a specific interrupt signal line 2' in the input/output bus 2 when initializing the computer system, and Information on the input/output devices 3a to 3n and information regarding the input/output device control means 7a to 7n are registered in the input/output device registration means 5. When the registration of the input/output devices 3a to 3n is completed and an interrupt signal from any of the input/output devices W3a to 3n is generated on a specific interrupt signal line 2' of the input/output bus 2, the central processing 0 when the device activates the interrupt control activation means 6
The interrupt control activation means sequentially confirms whether or not an interrupt has occurred for the input/output devices 3a to 3n registered in the input/output device information 5, and discovers the input/output device that has generated the interrupt. At this point, the process is shifted to the split X control of the corresponding input/output device among the input/output control means 7a to 7n.

このような制御を行なうことにより、第2図に示すよう
に、同一の割込信号線2′にて複数の入出力装置の割込
制御を行なうことができる。
By performing such control, as shown in FIG. 2, it is possible to perform interrupt control of a plurality of input/output devices using the same interrupt signal line 2'.

さらに具立的な実施例を第3図に示す、第3図に示した
実施例では、入出力装置として、SMD・ディスク制御
アダプタ3a” 、5T−5,06デイスク制御アダプ
タ3b″、ESDiディスク制御アダプタ3c″を同一
の割込信号線2′に接続して使用する場合を示している
A more concrete embodiment is shown in FIG. 3. In the embodiment shown in FIG. A case is shown in which the control adapter 3c'' is connected to the same interrupt signal line 2'.

電子計算機システム初期化の際に、入出力装置登録手段
であるディスク制御アダプタ登録処理4′にて、システ
ムに接続されているディスク制御アダプタがSMDディ
スク制御アダプタ3a’5T−506デイスク制御アダ
プタ゛3b’ 、ESDiディスク制御アダプタ3c’
の三種類であることを確認し、入出力装置情報であるデ
ィスク制御アダプタ情報5′に上記三種類のアダプタの
接続情報を登録する。システムの初期化が終了し、いず
れかのディスクに対する入出力要求が発生した際には、
入出力装置制御手段であるSMDディスク制御処理7a
’ 、5T−406デイスク制御処理7b’ 、ESD
iディスク制御処理7c’のうち、該当するディスク制
御処理の起動制御処理を起動する。起動制御処理では、
該当ディスク制御アダプタに対して入出力命令を起動し
、ディスク制御アダプタからの割込待ち状態となる。デ
ィスク制御アダプタ側でディスクの動作が終了すると、
中央処理装置、1に対して割込を発生し、中央処理装置
側では割、込の発生により割込制御起動手段である割込
発生アダプタ識別処理6′を起動する0割込発生アダプ
タ識別処理6′では、ディスク制御アダプタ情報5′の
アダプタ接続情報を参照し、接続されているディスク制
御アダプタのうちのどれから割込が発生したかを識別し
、該当するディスク制御処理の割込制御処理を起動し、
該当アダプタからディスク入出力の終了情報を引り取り
、ディスクへの入出力制御を終了する。
When initializing the computer system, the disk control adapter registration process 4', which is an input/output device registration means, determines that the disk control adapter connected to the system is the SMD disk control adapter 3a'5T-506 disk control adapter 3b'. , ESDi disk control adapter 3c'
The connection information for the three types of adapters mentioned above is registered in the disk control adapter information 5' which is the input/output device information. When the system has finished initializing and an input/output request to one of the disks occurs,
SMD disk control processing 7a which is input/output device control means
', 5T-406 disk control processing 7b', ESD
Among the i-disk control processes 7c', the activation control process of the corresponding disk control process is activated. In the startup control process,
An input/output command is activated for the corresponding disk control adapter, and the state is set to wait for an interrupt from the disk control adapter. When the disk operation ends on the disk control adapter side,
0 interrupt generation adapter identification processing that generates an interrupt to the central processing unit, 1, and activates the interrupt generation adapter identification processing 6', which is an interrupt control activation means, on the central processing unit side when the interrupt occurs. 6' refers to the adapter connection information in the disk control adapter information 5', identifies from which of the connected disk control adapters an interrupt has occurred, and executes the interrupt control process for the corresponding disk control process. Start
Receives disk input/output completion information from the applicable adapter and ends disk input/output control.

以上のように、第3図では、同一の割込信号線2′に複
数のディスク制御アダプタを接続して割込制御を行なう
ことができる。
As described above, in FIG. 3, interrupt control can be performed by connecting a plurality of disk control adapters to the same interrupt signal line 2'.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、電子計算機シス
テムにおいて、複数の入出力装置を使用する際に、−本
の割込信号線で複数の入出力装置を制御可能とすること
により、中央処理装置に接続可能な入出力装置の数が電
子計算機システム内の入出力バス中の割込信号線の本数
により制限されないという効果がある。
As explained above, according to the present invention, when a plurality of input/output devices are used in an electronic computer system, by making it possible to control the plurality of input/output devices with - interrupt signal lines, a central This has the advantage that the number of input/output devices connectable to the processing device is not limited by the number of interrupt signal lines in the input/output bus in the computer system.

報、6・・・割込制御起動手段、7a〜7n・・・入出
力装置制御手段、8・・・割込制御装置。
Information, 6... Interrupt control activation means, 7a-7n... Input/output device control means, 8... Interrupt control device.

Claims (1)

【特許請求の範囲】[Claims] 中央処理装置と、割込発生機能を持つ入出力装置と、前
記中央処理装置と前記入出力装置とを結ぶ入出力バスと
により構成される電子計算機システムにおいて、前記入
出力装置からの割込を制御する入出力装置制御手段と、
前記入出力装置の割込信号線情報を規定した入出ガ装置
情報を生成する登録手段と、前記入出力装置からの割込
信号により対応する割込制御を起動する手段とを有し、
同一割込信号による入出力割込の制御を可能としたこと
を特徴とする電子計算機システムにおける入出力装置の
割込制御方式。
In a computer system comprising a central processing unit, an input/output device having an interrupt generation function, and an input/output bus connecting the central processing unit and the input/output device, an interrupt from the input/output device is processed. an input/output device control means for controlling;
comprising a registration means for generating input/output device information defining interrupt signal line information of the input/output device, and means for activating corresponding interrupt control by an interrupt signal from the input/output device;
An interrupt control method for an input/output device in a computer system, characterized in that input/output interrupts can be controlled by the same interrupt signal.
JP18223888A 1988-07-20 1988-07-20 Interruption control system for input/output device Pending JPH0229844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18223888A JPH0229844A (en) 1988-07-20 1988-07-20 Interruption control system for input/output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18223888A JPH0229844A (en) 1988-07-20 1988-07-20 Interruption control system for input/output device

Publications (1)

Publication Number Publication Date
JPH0229844A true JPH0229844A (en) 1990-01-31

Family

ID=16114760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18223888A Pending JPH0229844A (en) 1988-07-20 1988-07-20 Interruption control system for input/output device

Country Status (1)

Country Link
JP (1) JPH0229844A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60222946A (en) * 1984-04-20 1985-11-07 Fujitsu Ltd Check system of channel mounting
JPS61233837A (en) * 1985-04-08 1986-10-18 Mitsubishi Electric Corp Interruption processing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60222946A (en) * 1984-04-20 1985-11-07 Fujitsu Ltd Check system of channel mounting
JPS61233837A (en) * 1985-04-08 1986-10-18 Mitsubishi Electric Corp Interruption processing system

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