JPH0784970A - Interruption control method - Google Patents

Abstract

PURPOSE:To improve the data processing capacity by confirming an interruption adaptor by an interruption controller and specifying an interruption destination CPU, and then eliminating the interruption of data processing by a CPU other than a CPU which performs data processing for the interruption initiating device on the basis of the interruption to the former CPU. CONSTITUTION:Bus adaptors 6a-1-6a-4 whose processes are performed by CPUs 1a-1-1a-4 are selectively assigned, data showing their correspondence relation are sent to the interruption controller 5a, and the ID of a CPU at a interruption destination corresponding to an interruption vector generated by one of the VME bus adapters 6a-1-6a-4 is set in an interruption table 5C. When an interruption is initiated by one VME bus adaptor, the interruption controller 5a reads the ID of the CPU at the interruption destination out of the interruption table 5c on the basis of the interruption vector and specifies the interruption destination CPU. The interruption controller 5a informs the specified CPU of the interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control method in a multiprocessor (hereinafter referred to as MP) type data processor having an I / O (input / output) bus.

[0002]

2. Description of the Related Art FIGS. 4 and 5 are views showing a conventional example, in which 1b-1 to 1b-n are processors (hereinafter referred to as CPs).
U), 2b is a system bus controller, 3b is a bus conversion device, 4b is a VME bus (Versa Mod).
ule Europe (American Institute of Electrical and Electronics Engineers, abbreviated IEEE standard bus) controller, 6b-1 to 6b
-M is VME bus adapter, 7b is system bus, 8b
Is a VME bus, 9b, 10b, 10b-1 to 10b-k
Indicates a signal line, and 11b indicates a table.

FIG. 4 is an explanatory diagram of the VME bus interrupt control circuit, and each CPU executes a program independently.
1b-1 to 1b-n, a system bus controller 2b that controls access on the system bus 7b, a bus converter 3b that connects the system bus 7b and the VME bus 8b on the I / O side, and a VME bus 8b. VME bus controller 4b for controlling access to CPUs and CPUs 1b-1 to 1-1
I / O connected to VME bus controlled by b-n
Various VME bus adapters 6b-1 to 6b-m on the O side
And VME bus adapters 6b-1 to 6b-m to VME
Signal line 9b for notifying the bus controller that an interrupt has occurred
And VME bus adapters 6b-1 to 6b-m to VME
VME bus adapter 6b-1 to bus controller 4b
It is composed of signal lines 10b-1 to 10b-k for notifying an identification number of 6b-m (hereinafter referred to as an interrupt vector) and a correspondence table 11b between the interrupt vector and the CPU.

Next, the operation of the interrupt control circuit shown in FIG. 4 will be described. When an interrupt occurs in any of the VME bus adapters 6b-1 to 6b-m, for example, the VME bus adapter 6b-1, the VME bus controller 4b is notified via the signal line 9b. This makes V
The ME bus controller 4b is, for example, the system bus 7b.
Notify that there is an interrupt to a certain CPU (not specified) above. The CPU notified of this interruption is as described below.
Interrupt occurrence VME through VME bus controller 4b
A process of reading an interrupt vector from the bus adapter 6b-1 (hereinafter referred to as IACK cycle) is executed. Then, this CPU refers to the correspondence table 11b from the read interrupt vector, certifies the CPU that should originally interrupt, and notifies the certified CPU that an interrupt has occurred.

FIG. 5 is an explanatory diagram of the IACK cycle. VME bus adapter 6b-1, 6b-2, 6b-3
When an interrupt occurs in any of ..., The VME bus controller 4 indicates that an interrupt has occurred on the interrupt signal line 9b.
b is notified, and the CPU is also notified.

The IACK cycle is executed by the instruction of the CPU. First, the IACK cycle is executed from the VMEbus controller 4b to the VMEbus adapter 6b-1.
The K signal is input. If VME Bus Adapter 6b-
If 1 is not the source of the interrupt signal, this IACK signal is transmitted from the VME bus adapter 6b-1 to the next VME bus adapter 6b-2. Thereafter, similarly, the IACK signal is sequentially input to the VME bus adapter up to the source of the interrupt signal.

When the IACK signal is input to the VME bus adapter which is the source of the interrupt signal, the VME bus adapter sends V signal from the signal line 10b to the VME bus controller 4b.
The interrupt vector, which is the identification number of the ME bus adapter, is output. The IACK cycle ends.

This interrupt vector is held in the VMEbus controller 4b, and the CPU reads it to recognize the VMEbus adapter which is the source of the interrupt signal.

[0009]

SUMMARY OF THE INVENTION The above-mentioned conventional devices have the following problems. In the interrupt processing of the VME bus of the MP data processing device, the VME bus adapter 6b-1 which generates an interrupt until the CPU reads the interrupt vector based on the IACK cycle.
~ 6b-m cannot be specified. Therefore, in the MP data processing device in which a plurality of CPUs control different VME bus adapters, the VME bus adapter 6b-1 is used.
When an interrupt occurs from ~ 6b-m, the CPU notified of the interrupt must suspend its own data processing due to an interrupt to another CPU which should execute the interrupt request of the VMEbus adapter. There was a problem of wasting performance.

In order to improve this, the present invention identifies the interrupt destination CPU by checking the interrupt generation adapter with the interrupt controller for the interrupt generated on the VME bus controlled in the MP environment, that is, the I / O bus. By doing so, it is possible to prevent interruption of the data processing in the other CPU based on the interruption to the CPU different from the CPU that performs the data processing for the interrupt generation I / O bus adapter as in the prior art, and to obtain the MP data. The purpose is to improve the performance of the processing system.

[0011]

The present invention is configured as shown in FIG. 1 in order to solve the above problems. FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, 1-1, 1-2,
1-n is a CPU, 2 is a system bus controller, 3 is a bus converter, 4 is an I / O bus controller, 5 is an interrupt controller, 6-1, 6-2, and 6-m are devices such as I / O bus adapters. , 7 is system bus, 8 is I /
O buses, 9, 10-1, 10-2, and 10-k represent signal lines, respectively.

[0012]

The operation of the present invention based on the above construction will be described with reference to FIG. When an interrupt occurs in any of the I / O bus adapters 6-1 to 6-m, the interrupt controller 5
To the signal line 9.

As a result, the interrupt controller 5 is
Execute IACK cycle on O-bus 8 to
In order to detect the interrupt source from 1, 6-2 ... 6-m,
The interrupt vector is set to the signal lines 10-1 and 1 by the same method as in FIG.
Read with 0-2 ... 10-k.

Further, the interrupt controller 5 specifies an interrupt destination CPU by referring to an interrupt table omitted in FIG. 1 from the read interrupt vector, and specifies the specified C.
An interrupt is notified to PU.

As described above, in response to the interrupt generated on the I / O bus 8, the interrupt controller 5 confirms the interrupt generation device and identifies the interrupt destination CPU, and then notifies the CPU of the interrupt. Since only the CPU for the device can perform processing, CP
U performance is not wasted.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an operation explanatory diagram thereof. 1a, 1a-1 in the figure
1a-4 are CPUs, and CPU 1-1 in FIG.
1-2, 2a is a system bus controller, which corresponds to the system bus controller 2 in FIG. 1, 3a is a bus converter, which corresponds to the bus converter 3 in FIG. 1, 4a 1 is a VME bus controller corresponding to the I / O bus controller 4 in FIG. 1 and 5a is an interrupt controller corresponding to the interrupt controller 5 in FIG.
b is an interrupt vector display register, 5c is an interrupt table, 6a, 6a-1 to 6a-4 are VME bus adapters, and I / O bus adapters 6-1 and 6-2 in FIG.
.., 7a is a system bus corresponding to the system bus 7 in FIG. 1, 8a is a VME bus corresponding to the I / O bus 8 in FIG. 1, 9
a, 10a-1 to 10a-4 are signal lines corresponding to the signal lines 9, 10-1, 10-2, ... In FIG. 1, FIG. 3 is an operation explanatory diagram in the present invention, and .about. are interrupts. The notification sequence is shown.

Each of the CPUs 1a-1 to 1a-4 independently executes a program and has different V
It controls the ME bus adapters 6a-1 to 6a-4. The system bus controller 2a controls access on the system bus 7a.

The bus conversion device 3a includes a system bus 7a and V
The ME bus 8a is connected to perform format conversion between both buses. VME bus controller 4
a controls access on the VMEbus 8a.

The interrupt controller 5a is provided with an interrupt vector display register 5b and an interrupt table 5c, and V
The interrupt generated in the ME bus 8a is controlled, the VME bus adapter of the interrupt source is recognized, and as will be described later, the CPU that performs the process related to the VME bus adapter of the interrupt source is recognized by referring to the interrupt table 5c.

The interrupt vector display register 5b is the IAC.
The interrupt vector detected in the K cycle is held, and the interrupt table 5c sets the correspondence between the interrupt vector and the interrupt destination CPU.

VME bus adapters 6a-1 to 6a-4
Are controlled by the CPU designated by the interrupt table 5c, and devices such as a file device and a communication system are connected to these VME bus adapters.

Next, the operation of the VME bus interrupt control circuit of FIG. 2 will be described with reference to FIG. The CPU 1a in FIG.
CPUs 1a-1 to 1a-4 in FIG.
The ME bus adapter 6a comprehensively shows the VME bus adapters 6a-1 to 6a-4 in FIG.

First, at the start-up of the system, V which each CPU 1a-1 to 1a-4 performs in advance by an initial program from a service processor (not shown)
The ME bus adapters 6a-1 to 6a-4 are selectively allocated, and data indicating this correspondence is transmitted to the interrupt controller 5a, which causes an interrupt generated by the VMEbus adapters 6a-1 to 6a-4. The ID (identification number) of the interrupt destination CPU corresponding to the vector is set in the interrupt table 5c.

When an interrupt due to, for example, completion of processing or occurrence of an error occurs in the VMEbus adapter, this is notified to the interrupt controller 5a via the signal line 9a. Interrupt controller 5a sends IACK to VMEbus 8a
The cycle is executed, and the interrupt vector of the VMEbus adapter which has generated the interrupt is set in the interrupt vector display register 5b.

Based on this interrupt vector, the interrupt controller 5a receives the interrupt destination CP from the interrupt table 5c.
The U ID is read and the interrupt destination CPU is specified. The interrupt controller 5a notifies the specified CPU of an interrupt.

Upon receiving the interrupt notification, the CPU reads the interrupt vector display register 5b in the interrupt controller 5a and specifies the VMEbus adapter which has generated the interrupt.

The CPU is the VME specified by this.
A predetermined interrupt processing routine is started for the bus adapter and processing based on the interrupt is executed. In the above description, an example in which the interrupt table 5c is set at the time of loading the initial program has been described, but the present invention is not limited to this, and an interrupt vector correspondence table such as that shown in FIG. In view of this, each CPU 1a-1 to 1a-4 may be configured to sequentially control the writing to the interrupt table 5c.

In the above embodiment, the interrupt controller 5
Although a is provided as one LSI separately from the VME bus controller 4a, the interrupt controller 5a is provided as a VME.
It can also be built in the bus controller 4a.

[0029]

As described above, according to the present invention,
Since the interrupt vector can be pre-read by the interrupt controller, the interrupt can be notified to a predetermined CPU from the beginning. Therefore, the processing is not interrupted by the interruption to the other CPU, and the performance of the MP type data processing device can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

FIG. 5 is an explanatory diagram of a conventional IACK cycle.

[Explanation of symbols]

 1-1, 1-2, 1-n CPU 2 System bus controller 3 Bus conversion device 4 I / O bus controller 5 Interrupt controller 6-1, 6-2, 6-m device 7 System bus 8 I / O bus 9 10-1, 10-2, 10-k signal line

Claims (3)

[Claims] 1. A data processing method comprising a plurality of CPUs and a plurality of devices, wherein the CPU performs predetermined data processing on the device, wherein an interrupt signal is output from the device when the interrupt signal is output. An interrupt control method comprising: an interrupt controller (5) for recognizing an original device and notifying an interrupt to a CPU whose correspondence with the interrupt source device is designated in advance. 2. The interrupt controller (5) is an I / O
The interrupt control method according to claim 1, wherein the interrupt control method is built in the bus controller (4). 3. The interrupt control method according to claim 1, wherein the interrupt table stores CPU IDs.