JP2731027B2 - Display control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for realizing a display operation of, for example, a simple matrix type liquid crystal display device.

2. Description of the Related Art For example, in a simple matrix type liquid crystal display device, a plurality of strip-shaped transparent electrodes which are mutually orthogonal are formed as a row direction electrode and a column direction electrode on a pair of transparent substrates, and are arranged in a matrix over the entire display area of the liquid crystal display device. Address is set.
A row direction drive circuit and a column direction drive circuit are connected to the liquid crystal display device, and a CPU (central processing circuit) is connected to the row direction drive circuit and the column direction drive circuit. The row direction drive circuit scans the column direction electrodes in the liquid crystal display device along the row direction and sets row direction address data. on the other hand,
The column direction drive circuit scans the row direction electrodes along the column direction,
Set the column direction address.

When the display control circuit performs display on a liquid crystal display device, for example, a section is set for each unit display area in units of 8 bits along the row direction in the display area, and access is performed for each section. Therefore, when displaying 8-bit display data over a plurality of unit display areas, the CPU processes address data by software and outputs the processed address data to the row direction drive circuit. When display data is written in the display area for each of the 8-bit unit display areas and display is performed, software for performing both the row direction and the column direction becomes a huge program, and it is difficult to realize the software. there were.

Problems to be Solved by the Invention In the conventional example described above, the processing of address data in the CPU is performed by software processing, and the load on the software and therefore the CPU is large. There is a problem that it becomes slow. Further, there is a problem that the display operation in both the row direction and the column direction is not realized, and the usability is low.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned technical problems, to provide a display control device which realizes a high-speed display operation while reducing the load of software in performing a display operation, and is excellent in usability. It is.

Means for Solving the Problems The present invention provides: (a) a display device 11 in which pixels are arranged in an X direction and a Y direction, and display data 76 on the pixels; and (b) a memory device 68, A plurality of bits are set as one bit unit, and a division by the unit area Aij for each of the first plurality of bits is set adjacent to each other in the X direction. Each bit of the unit adjacent Aij corresponds to a pixel, Display device storing display data PM7 to PM0 for each pixel
A memory device 68 to be displayed on the display 11; and (c) the processing means 12, which is composed of a plurality of bits of address data for designating a write or read start address (30, 70) of a pixel, and X from the write or read start address. Processing means 12 for deriving display data corresponding to the address data of the first plurality of pixels successively adjacent in the direction; and (d) address data calculation means 1, The address data is received, and the unit area selection data (X
E3 to XE9) and X-direction address data (XE0 to XE9) having bit position data (XE0 to XE2) indicating which bit of the write or read start address is in the selected unit area Aij (E) the address conversion means 70, and the unit area selection data (XE3 to XE9) of the X-direction address data (XE0 to XE9) from the address calculation means 1.
And (f) address difference calculating means, which outputs selection data AX0 to AX3 for selecting the unit area Aij, and (f) X-direction address data (XE
0 to XE9) in response to the bit position data (XE0 to XE2), and the unit areas A9, A7 selected by the address conversion means 70.
Address difference calculating means for obtaining data SFTi of an address difference between the X-direction start address (24) of 0 and the X-direction start address (30) specified by the processing means 12, (g) writing or reading means When the address data and the display data corresponding to the address data are output from the processing unit 12, the selected unit areas A9, 70 and the selected unit areas A9, 70 are added in the X direction. Another adjacent unit area A1
Address designation with 0, 70 is performed in this order, and in response to the output of the address difference data SFTi from the address difference calculating means, the remaining bits of the address difference of the selected unit area A9, 70 are The display data corresponding to each bit address is written to each bit address, and the display data corresponding to each bit address is written to each bit address of the bit of the address difference in the another unit area A10, 70. A display control device comprising writing or reading means.

The present invention also provides (a) a display device 11 in which pixels are arranged in the X direction and the Y direction and displays display data 76 on the pixels, and (b) a memory device 68, wherein the first plurality of bits are 1 In the X direction, a division by a unit area Aij for each of a plurality of first bits is set adjacent to each other, and each bit of the unit adjacent Aij corresponds to a pixel, and the display data for each pixel is set. Display device that stores PM7 to PM0
A memory device 68 to be displayed on the display unit 11; and (c) the processing means 12, which comprises a plurality of bits of address data for designating a write or read start address (40, 40) of a pixel, and Y from the write or read start address. Processing means 12 for deriving display data corresponding to the address data of the first plurality of pixels successively adjacent in the direction; and (d) address data calculation means 1, The address data is received, and the unit area selection data (X
E3 to XE9) and X-direction address data (XE0 to XE9) having bit position data (XE0 to XE2) indicating which bit of the write or read start address is in the selected unit area Aij (E) the address conversion means 70, and the unit area selection data (XE3 to XE9) of the X-direction address data (XE0 to XE9) from the address calculation means 1.
And (f) address difference calculating means, which outputs selection data AX0 to AX3 for selecting the unit area Aij, and (f) X-direction address data (XE
0 to XE9) in response to the bit position data (XE0 to XE2) and the unit areas A4,4 selected by the address conversion means 70.
An address difference calculating means for obtaining data SFTi of an address difference between the X-direction start address (40) of 0 and the X-direction start address (40) designated by the processing means 12, and (g) writing or reading means. When the address data and the display data corresponding to the address data are output from the processing means 12, the selected unit areas A4, 40 are adjacent to the selected unit areas A4, 40 in the Y direction. The address designation of the first plurality of unit areas A4, 40 to A4, 47 is performed in this order, and in response to the output of the address difference data SFTi from the address difference calculating means, the selected unit area A4, 40 corresponds to each bit address of the bit of the address difference of the first plurality of unit areas A4, 40 to A4, 47 adjacent to the selected unit area A4, 40 in the Y direction. Display data A display control device which comprises a writing or reading means writes sequentially written.

The present invention also provides an address conversion means (X direction 70 and Y
The direction 75) is characterized by comprising a read-on memory.

Operation According to the first aspect of the present invention, as described later with reference to FIGS.
11) By deriving the address data composed of bits and the display data corresponding to the address data of a first plurality (for example, 8) of pixels consecutively adjacent in the X direction, the address data calculating means 1 X-direction address data (XE0 to XE9) is derived based on the address data, and the X-direction address data is used to select a first plurality (for example, 8 as described above) of bit-by-bit unit areas Aij. Unit area selection data (XE3 to XE9) and bit position data (XE0
XXE2), and the address conversion means 70 selects the selection data AX0〜AX3 for selecting the unit area Aij based on the unit area selection data (XE3〜XE9) of the X direction address data (XE0〜XE9). At the same time, the address difference calculating means obtains the address difference data SSTi based on the bit position data (XE0 to XE2), and calculates the address difference data SSTi.
Ti is the address difference between the X-direction start address (24) by the address conversion means 70 and the X-direction start address (30) designated by the processing means 12, and thus the writing means sets the selected unit area A9, The addressing of the other unit area A10, 70 adjacent in the X direction is performed in this order, and the remaining of the address difference of the first unit area A9, 70 is determined based on the address difference data SSTi. The display data is written to each bit address of the minute bits, and the display data is written to each bit address of the bit having the address difference of the next unit area A10, 70. Therefore, the processing unit 12 does not need to access the unit area A9, 70 and the next unit area A10, 70 by dividing the address into two times in total. As a result, the load on software accompanying the display operation by the processing means 12 can be reduced, a high-speed display operation can be realized, and usability is improved.

According to the second aspect of the present invention, the processing means 12 is adjacent to the write start address (40, 40) continuously in the Y direction, as will be described later with reference to FIGS. By deriving the display data for the first plurality (for example, eight) of pixels, the address data calculating means performs the unit area selection data (XE3 to XE9) and the bit position data (XE0 to XE2) in the same manner as described above. X-direction address data (XE0 to XE)
E9), whereby the address converting means 70 and the address difference calculating means process the selected data X0 to X3 for selecting the unit area Aij and the X-direction start address (40) of the selected unit areas A4, 40 with the processing. The data SSTi of the address difference from the start address (40) in the X direction specified by the means 12
Then, the writing means performs the addressing of the first plurality (for example, 8) of unit areas A4, 40 to A4, 47 adjacent in the Y direction from the selected unit area A4, 40 in this order, Based on the data SSTi of the address difference, display data is sequentially written to each bit address of the bit of the address difference. In this way, it is possible to reduce the load of software associated with the display operation by the processing means 12, as in the first aspect of the present invention, and thus it is possible to realize a high-speed display operation and improve usability. Is done.

Regarding reading, the configuration is the same as that of writing, and the same operation is achieved.

According to the third aspect of the present invention, the address conversion means (X direction 70 and Y direction 75) is realized by a read-on memory as in the embodiment described later, and therefore, according to the configuration of the display device 11 and the memory device 68. By doing so, the design and assembly can be simplified.

Embodiment FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2 using a common drive circuit 1, and FIG. FIG. The data processing device 2 has a so-called notebook size, and the first operation unit 3 and the second operation unit 4 are configured to be freely opened and closed by a coupling unit 5. The second operation unit 4 includes a cursor key 6, a function setting key 7, a character input key 8, a numeric key 9, and the like. On the other hand, a so-called transparent touch key 10 and a liquid crystal display element 11 are arranged on the first operation unit 3.

Such a data processing device 2 includes, for example, a CPU (central processing circuit) 12 including a microprocessor or the like.
The CPU 12 has the transparent touch key 10 and the second
A RAM (random access memory) 13 to which each key input means of the operation unit 4 is connected and which is used as a storage area for various input data and a working area for data during operation, and a CPU
A ROM (read only memory) 14 in which programs for defining the control operations of 12, font data for display, calendar data, and the like are stored is connected.

Further, the CPU 12 has a timing circuit 15 for timing, a common drive circuit 1 for controlling the display operation of the liquid crystal display device 11 as described later, and a common drive circuit 1 based on a contrast signal from the common drive circuit 1. A liquid crystal power supply circuit 16 that changes the potential of the liquid crystal battery to be operated and switches between the operation state and the stop state according to a control signal from the CPU 12 is connected. The common drive circuit 1 has a plurality (8 in this embodiment).
), And controls the display state of the liquid crystal display device 11 together with the common drive circuit 1. The liquid crystal display device 11 has a common electrode 1 on a pair of transparent substrates 11a and 11b.
1c, a segment electrode 11d is formed, and a liquid crystal layer 11e is interposed therebetween.

A block diagram of the common drive circuit 1 is shown in FIG. The common drive circuit 1 is supplied with a write / read control signal R / W, a clock signal φ, a busy signal BY, a chip enable signal CE, and the like from the CPU 12, and a control circuit 19 to which address data AD, display data DI, and the like are supplied. Is provided. The display data DI is input through the buffer 20. The common drive circuit 1 is connected to the frame signal FR
And a control signal DIS for controlling ON / OFF of the display by the segment electrode and a clock signal LCK,
Output to As described above, such a data processing device 2 is a notebook-sized portable device, and various reference voltages necessary for the operation of the data processing device 2 are generated from a power supply circuit 26 connected to a battery 25.

A data processing circuit 21 is connected to the control circuit 19 and the CPU 12
After performing a predetermined logical operation (such as SET, AND, OR, XOR, etc.) on the address data and display data transferred from the device, the data is transmitted to the segment drive circuit 17. The memory control circuit 22 determines to which of the segment driving circuits 17 the address data sent from the CPU 12 is to be transferred, and generates a relative address in any of the selected segment driving circuits 17. The timing generation circuit 23 generates a clock signal used for various arithmetic processing in the common drive circuit 1 and the like, and receives a reference clock signal from the oscillator 24.

The common signal control circuit 27 and the common-side decoder 28 use the clock signal generated by the timing generation circuit 23 to generate a common signal supplied to the common electrode of the liquid crystal display device 11. The control circuit 19 is connected to a window processing circuit 29 having a configuration and an operation as described later.The contrast adjustment circuit 46 stores the display density on the liquid crystal display device 11, and the density data is set from the CPU 12. . The contrast adjustment of the liquid crystal display device 11 is performed by the liquid crystal power supply circuit 16 shown in FIG. 2 based on the density data in the contrast adjustment circuit 46, and the liquid crystal power supply potential from the liquid crystal power supply circuit 16 is taken into the common drive circuit 1. LCD voltage input section for
17 are provided.

FIG. 4 is a block diagram of a configuration related to an address control operation in the data processing device 2. An 8-bit data bus 61, a 6-bit address bus 62, and a control line 63 for outputting a selection signal CE for selecting the common drive circuit 1 are provided between the CPU 12 and the common drive circuit 1. Common drive circuit 1 and each segment drive circuit 17-1 to 17-8
Are individually connected to the segment drive circuits 17-1 to 17-8, respectively.
Supply eight selection lines CE1 to CE8 for selecting any one of the above, an 8-bit data bus 65, and 8-bit address data AY in the Y direction in the liquid crystal display device 11. Address bus 66 and X
An address bus 67 for supplying 4-bit address data AX relating to the direction is connected.

The liquid crystal display device 11 of the present embodiment has an address (0,
A virtual address space having virtual addresses from (0) to the lower right corner address (146,896) is set. On the other hand, each of the segment drive circuits 17-1 to 17-8 has a predetermined address width (for example, 11
2 bits). That is, the segment driving circuit 17-1 shares the row address ranges 1 to 112, and the segment driving circuit 17-2 shares the row address ranges 113 to 224. Similarly, the segment drive circuit 17-8 shares the row direction address range 785 to 896.

Further, in this embodiment, when the display data is written to the liquid crystal display device 11, in the case of horizontal writing, as shown in the area E1 of FIG. Rarely, in the case of vertical writing as described later, as shown in the display area E2, 8 characters are displayed in the column direction from the display start address.
Display data is written over a continuous address range of bits.

FIG. 5 is a diagram showing the configuration of the segment drive circuit 17. Each of the segment drive circuits 17-1 to 17-8 is RA
The display data transferred via the data bus 65 from the write start address specified by the address data AX and AY from the address buses 66 and 67 described above in 8-bit units along the row direction. Written in. This RAM68
Is the address range (0,0) in the liquid crystal display device 11 which is shared by the segment drive circuit 17-1.
~ (146,112). Remaining segment drive circuit 1
RAMs 68 having the same memory capacity are also provided in 7-2 to 17-8.

FIG. 6 is a block diagram showing a configuration of the address operation circuit 69 provided in the memory control circuit 22 in the common drive circuit 1. From the CPU 12, 11-bit address data including a sign bit in the X direction of the liquid crystal display device 11 and 10-bit address data including a sign bit in the Y direction are input to the common drive circuit 1. The common drive circuit 1 sends the address data XE0 in the X direction to each data segment drive circuit 17 from the address data.
.. XE9, an extension bit XE and a sign bit XS of 12 bits, and in the Y direction, a total of 11 bits of address data YE0 to YE8, an extension bit YE and a sign bit YS are outputted.

Here, the address data XE0 to XE9; YE0 to YE8 are a substantial part of the address data, and the extension bits XE and YE indicate that the address data input from the CPU 12 to the common drive circuit 1 has exceeded the display capacity of the display area 59. If it is data, the address data is stored in the extended address area outside the display area 59 defined by the substantial address data XE0 to XE9; YE0 to YE8 and set by combining the extension bits XE and YE. It is provided to regulate. Sign bit
XS and YS represent the sign of the address data.

The address data XE3 to XE9 of a part of the X-direction address data XE0 to XE9 are input to a data conversion circuit 70 realized by, for example, a ROM. Data conversion circuit 70
.., Ai14 (i = 1 to 146) in the unit area Ai1, Ai2,..., Ai14 (i = 1 to 146) along the row direction provided for each Y-direction address in the display area 59 of the RAM 68 shown in FIG. Selection data AX0 to AX3 for selecting one is output.

That is, if the selection data (AX0 to AX3) = 0, 1, 2, for example, the unit areas A11, A12, A of the RAM 68 shown in FIG.
13 are selected correspondingly. The starting address of the display data is determined by which bit of the selected unit area Aij starts from the X-direction address data XE0 to XE2.
Are set as described later.

The selection data BX0 to BX2 are input to the selection signal generation circuit 71 from the data conversion circuit 70, and any one of the selection signals CE1 to CE8 is output. On the other hand, the extension bit XE and the sign bit XS pass through an inversion circuit 72,
The valid signal ACX output from 70 is input to the AND circuit 73 together with the valid signal ACX, and the output ACX ′ is input to the AND circuit 74. The output of the AND circuit 74 is input to the selection signal generation circuit 71.

The Y-direction address data YE0 to YE8 is a data conversion circuit.
Similarly to 70, the data is input to a data conversion circuit 75 for address data in the Y direction realized by a ROM or the like, and a valid signal ACY for the Y direction is output from the data conversion circuit 75, and the extension bit YE and the sign bit YS are inverted by the inversion circuit 72. Are input to the AND circuit 73 together with the inverted signal via the, and the output ACY ′ is input to the AND circuit 74. That is, the following arithmetic processing is executed by the inverting circuit 72 and the AND circuits 73 and 74.

ACX '= ACX ・ ▲ ▼ ・ ▲ ▼ (1) ACY ′ = ACY ・ ▲ ▼ ・ ▲ ▼ (2) ACT = ACX' ・ ACY '(3) At this time, the selection signal generation circuit 71 detects that the address data input from the CPU 12 to the common drive circuit 1 is in the address area corresponding to the display area 59, and only at this time, the selection signal CE1 is output.
~ CE8 can be output. The data conversion circuit 75 outputs a stage setting signal BY. This signal indicates whether or not the display area 59 has a configuration in which the common drive circuit 1 extends over one or two or more stages in the Y direction.
This is the case in this case. The data conversion circuit 75 outputs address data AY0 to AY7 in the Y direction supplied to each segment drive circuit 17.

Hereinafter, the operation of the present embodiment will be described. When writing data to the virtual address (30, 70) in the display area 59 shown in FIG. 4, the CPU 12 transfers the address data to the common drive circuit 1 together with the display data. Segment drive circuit
As described above, the unit area Aij of every 8 bits
Are set, and the writing / reading processing of the display data is also performed for each of the divisions. That is, when 8-bit display data continuous in the horizontal direction is written to the address of the address data (30, 70), the address (24, 7) shown in FIG.
The unit areas A9, 70 starting with the address (0) are accessed, and the unit areas A10, 70 starting with the address (32, 70) are accessed. The address (3
8-bit data starting from (0, 70) is written.

Even when the write start address does not extend over two unit areas A as in (24, 70), the write start address is
Two unit areas A9, 70; A10, 70 are accessed twice.

Hereinafter, details of such an access method will be described. Write start address (30, 70) as in the above example
When writing display data from the address of unit area A9,7
The difference between the X-direction start address 24 of 0 and the X-direction start address 30 of the display data is 30−24 = 6, and such a subtraction result generally takes a value of 0 to 7. The data SFTi is associated with the address difference as shown in Table 1 below.

That is, among the X-direction address data XE0 to XE9, the extension bit XE, and the sign bit XS, which are accessed by the common drive circuit 1, the display data is represented by three bits of address data XE0 to XE2 not shown in FIG. Is determined in which bit in each unit area Aij the write start address along the X direction is determined. Therefore, the data SFT0 to SFT7 are expressed as the following formulas 4 to 11.

SFT0 = ▲ ▼ ・ ▲ ▼ ・ ▲ ▼… (4) SFT1 = XE0 ・ ▲ ▼ ・ ▲ ▼… (5) SFT2 = ▲ ▼ ・ XE1 ・ ▲ ▼… (6) SFT3 = XE0 ・ XE1 ・ ▲ ▼… ( 7) SFT4 = ▲ ▼ ・ ▲ ▼ ・ XE2… (8) SFT5 = XE0 ・ ▲ ▼ ・ XE2… (9) SFT6 = ▲ ▼ ・ XE1 ・ XE2… (10) SFT7 = XE0 ・ XE1 ・ XE2… (11) As shown in FIG. 7, when the symbols WBH7 to WBH0; WBL7 to WBL0 are respectively attached to the bits of each unit area Aij, A (i + 1) j, the display data 76 of 8 bits PM7 to PM0 shown in FIG.
The first eight bits WBH7-WBH0 and the second eight bits WBL7-WBL0
The data SFT0 in two continuous unit areas A
When taking the values of .about.SFT7, the area corresponding to the display data 76 takes the area of each of the 8-bit areas SFT0 'to SFT7' shown in FIG. Therefore, WBn = WBHn ・ + WBLn ・ (12) The symbol is used when the data described immediately before accesses the first half 8 bits WBH0 to WBH7 or when the latter half 8 bits WBL0 to WBL7 are accessed. Indicates that

Therefore, if the above twelfth expression is described over the subscripts n = 0 to 7, it is expressed by the following thirteenth to twentieth expressions.

WB0 = ｛SFT0 ・ PM0 ＋ SFT1 / PM1 ＋ SFT2 / PM2 ＋ SFT3 ・ PM
3 + SFT4 · PM4 + SFT5 · PM5 + SFT6 · PM6 + SFT7 · PM7｝… (13) WB1 = {SFT0 · PM1 + SFT1 · PM2 + SFT2 · PM3 + SFT3 · PM
4 ＋ SFT4 ・ PM5 ＋ SFT5 ・ PM6 ＋ SFT6 ・ PM7｝ ＋ ｛SFT7 ・ PM
0｝… (14) WB2 ＝ ｛SFT0 ・ PM2 ＋ SFT1 / PM3 ＋ SFT2 / PM4 ＋ SFT3 ・ PM
5 ＋ SFT4 ・ PM6 ＋ SFT5 ・ PM7｝ ＋ ｛SFT6 ・ PM0 ＋ SFT7 ・ PM
1｝… (15) WB3 = ｛SFT0 ・ PM3 ＋ SFT1 ・ PM4 ＋ SFT2 ・ PM5 ＋ SFT3 ・ PM
6 + SFT4 PM7 + SFT5 PM0 + SFT6 PM1 + SFT7 PM
2…… (16) WB4 = ｛SFT0 / PM4 + SFT1 / PM5 + SFT2 / PM6 + SFT3 / PM
7｝ + ｛SFT4 ・ PM0 ＋ SFT5 ・ PM1 ＋ SFT6 ・ PM2 ＋ SFT7 ・ PM
3｝… (17) WB5 = ｛SFT0 ・ PM5 + SFT1 / PM6 + SFT2 / PM7｝ + ｛SF
T3 ・ PM0 ＋ SFT4 ・ PM1 ＋ SFT5 ・ PM2 ＋ SFT6 ・ PM3 ＋ SFT7 ・ PM
4｝… (18) WB6 ＝ ｛SFT0 ・ PM6 ＋ SFT1 / PM7｝ ＋ ｛SFT2 / PM0 ＋ SF
T3 ・ PM1 ＋ SFT4 ・ PM2 ＋ SFT5 ・ PM3 ＋ SFT6 ・ PM4 ＋ SFT7 ・ PM
5｝… (19) WB7 ＝ ｛SFT0 ・ PM7｝ ＋ ｛SFT1 / PM0 ＋ SFT2 / PM1 ＋ SF
T3 ・ PM2 ＋ SFT4 ・ PM3 ＋ SFT5 ・ PM4 ＋ SFT6 ・ PM5 ＋ SFT7 ・ PM
6｝ (20) That is, when the address (30, 70) is accessed as the write start address, the area SFT6 ′ shown in FIG. 7 is selected and the address data (24, 70) is accessed as the write start address. Is selected from the areas SFT0 'shown in FIG.
Is as follows.

In the case of address (30, 70) (SFT6), WB0 = PM6 ... (21) WB1 = PM7 ... (22) WB2 = PM0 ... (23) WB3 = PM1 ... (24) WB4 = PM2 ... ( 25) WB5 = PM3 ... (26) WB6 = PM4 ... (27) WB7 = PM5 ... (28) In the case of address (24,70) (SFT0), WB0 = PM0 ... (29) WB1 = PM1 … (30) WB2 = PM2… (31) WB3 = PM3… (32) WB4 = PM4… (33) WB5 = PM5… (34) WB6 = PM6… (35) WB7 = PM7… (36) By configuring the common drive circuit 1 with a circuit that realizes the operations of the above-described equations (1) to (36), data processing by the CPU 12 is performed in consideration of the 8-bit division of the RAM 68 shown in FIG. , Writing / reading access is possible.

The above description is about the case where display data is written in the display area 59 along the X direction. Hereinafter, the case where display data is written in the Y direction will be described. When writing 8-bit data in the Y direction from the write start address (40, 40) as in the display area E2 shown in FIG. 4, the write start address (40, 4)
1), ..., (40,47) 8 unit areas A4,40; A4,41; ...; A
This is executed by accessing 4,47 consecutively eight times.

In the case of the unit area A4, 40, the data SFT0 is selected from the first table. For example, if the 8-bit continuous write start address in the Y direction is an address (45, 40),
Data SFT5 is selected from Table 1. In the case of the vertical access, as shown in the memory map of the RAM 68 in FIG. 10, in the eight sets of X-direction 8-bit data written by eight consecutive accesses, the data SFTi
Only the bits selected in (i = 0 to 7) are valid and written.

That is, when writing 8-bit data in the Y direction from the write start address (40, 40) as shown in FIG.
As shown in FIG. 11 (1), each bit data PM7 to PM0 of the display data 76 is in the state of FIG. 11 (2) at the time of the first write operation.
As shown in the above, only one bit of the data of the most significant bit PM7 is written, and thereafter, the remaining bit data PM6 to PM0 are shifted left by one bit.

In this state, at the second write timing, only one bit of the bit data PM6 is written as shown in FIG. 11 (3). Thereafter, by repeating the same processing, 8-bit display data continuous in the Y direction is written.

Such processing is generally expressed by the following equations (37) to (44).

WB0 = SFT7 ・ (PM7 ・ ＋ PM6 ・ ＋ PM5 ・ ＋ PM4 ・
+ PM3 ・ + PM2 ・ ＋ PM1 ・ ＋ PM0 ・)… (37) WB1 ＝ SFT6 ・ (PM7 ・ ＋ PM6 ・ ＋ PM5 ・ ＋ PM4 ＋ P
M3 ・ + PM2 ・ ＋ PM1 / PM0 ・) (38) WB2 ＝ SFT5 ・ (PM7 ・ + PM6 ・ ＋ PM5 ・ ＋ PM4 ・
+ PM3 ・ + PM2 ・ ＋ PM1 ・ ＋ PM0 ・)… (39) WB3 ＝ SFT4 ・ (PM7 ・ ＋ PM6 ・ ＋ PM5 ・ ＋ PM4 ・)
+ PM3 ・ + PM2 ・ ＋ PM1 ・ ＋ PM0 ・)… (40) WB4 = SFT3 ・ (PM7 ・ + PM6 ・ + PM5 ・ + PM4 ・)
+ PM3 ・ + PM2 ・ ＋ PM1 ・ ＋ PM0 ・)… (41) WB5 = SFT2 ・ (PM7 ・ ＋ PM6 ・ ＋ PM5 ・ ＋ PM4 ・)
+ PM3 ・ + PM2 ・ ＋ PM1 ・ ＋ PM0 ・)… (42) WB6 = SFT1 ・ (PM7 ・ ＋ PM6 ・ ＋ PM5 ・ ＋ PM4 ・)
+ PM3 ・ + PM2 ・ ＋ PM1 ・ ＋ PM0 ・)… (43) WB7 ＝ SFT0 ・ (PM7 ・ ＋ PM6 ・ ＋ PM5 ・ ＋ PM4 ・)
+ PM3 • + PM2 • + PM1 • + PM0 •) (44) Specifically, when accessing from the write start address (40, 40) in the Y direction, the data SFT0 is selected and the write start address (45, 40) is selected. In the case of performing 8-bit vertical access from 40), the data SFT5 is selected. Therefore, for example, the values of data WB0 to WB7 for each of eight consecutive write operations (indicated by symbol in FIG. 10) are as follows.

In the case of the write start address (40, 40), it is SFT0, and WB7 = SFT0 • (PM7 • + PM6 • + PM5 • + PM4 •
+ PM3 ・ + PM2 ・ ＋ PM1 ・ ＋ PM0 ・)… (45) For the write start address (45,40), it is SFT5, and WB2 = SFT5 ・ (PM7 ・ + PM6 ・ + PM5 ・ + PM4 ・)
+ PM33 + PM2 ・ + PM1 ・ + PM0 ・) (46) Even when writing continuous 8-bit data in the Y direction to the display area 59 as described above,
By providing a circuit configuration for performing the operations of Expressions to Expression 44,
There is no need for the CPU 12 to perform data processing corresponding to the 8-bit division of the RAM 68 in the segment drive circuit 17, and a display operation is realized.

As described above, in the present embodiment, the various operation processes required for the display operation in the X direction or the Y direction in the display area 59 are realized by the hardware in the common drive circuit 1, so that the display operation is realized. CPU12
That is, the load on software can be reduced, and a high-speed display operation can be realized. Further, as described above, the display operation in the X direction and the Y direction in the display area 59 can be easily performed, and the usability is remarkably improved.

According to the first aspect of the present invention, the processing unit 12 includes the address data designating the write start address (30, 70) and the first plurality of address data consecutively adjacent to the write start address in the A direction. For example, by deriving the pixel data of 8) with the display data, the operation of the address data calculation means 1, the address conversion means 70 and the address difference calculation means allows
The writing means writes the display data by specifying the address of the selected unit area A9, 70 and the next unit area A10, 70 adjacent in the A direction in this order, and writing the display data. The load on the software involved in the display operation can be reduced, so that a high-speed display operation can be realized, and the usability is improved.

According to the second aspect of the present invention, the processing unit 12 derives the write start address (40, 40) and the display data for the first plurality of pixels that are consecutively adjacent in the Y direction from the write start address (40, 40). By means of the operation of the address data calculating means 1, the address converting means 70 and the address difference calculating means, the writing means makes the first plurality of unit areas A4, 40 to A4, 47 adjacent to the selected unit area A4, 40 in the Y direction. Since the address designation is performed in this order and the display data is sequentially written, this configuration can also reduce the load on the software associated with the operation display in the processing 12 and achieve the high-speed display operation. Can be realized, and usability can be improved.

 The configuration, operation and effect are the same for reading.

According to the third aspect of the present invention, the address conversion means (X direction 70 and Y direction 75) is realized by a read-on memory, whereby a read-only memory is configured corresponding to the display device 11 and the memory device 68. Well, design and assembly can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a common drive circuit 1 according to an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2, FIG. 3 is a plan view of the data processing device 2, and FIG. Block diagram illustrating the wiring state of the configuration related to 11,
FIG. 5 is a memory map of the RAM 68 in the segment drive circuit 17, FIG. 6 is a block diagram of an address operation circuit 69 provided in the common drive circuit 1, and FIGS. 7 and 8 are diagrams for explaining the operation of the present embodiment. 9 to 11 are diagrams for explaining another operation of the present embodiment. DESCRIPTION OF SYMBOLS 1 ... Common drive circuit, 2 ... Data processing device, 11 ... Liquid crystal display device, 17 ... Segment drive circuit, 59 ... Display area, 68 ...
RAM, 69: Address operation circuit, 70: Data conversion circuit, 71
... Selection signal generation circuit

Claims (3)

(57) [Claims] 1. A display device 11 in which pixels are arranged in an X direction and a Y direction and display data 76 is displayed on the pixels, and (b) a memory device 68, wherein the first plurality of bits are 1 In the X direction, a division by the unit area Aij for each of the first plurality of bits is set adjacent to each other in the X direction. Each bit of the unit area Aij corresponds to each pixel, and the display data for each pixel Display device 11 that stores PM7 to PM0
And (c) the processing means 12, comprising: a plurality of bits of address data for designating a pixel write or read start address (30, 70); and a X direction from the write or read start address. Processing means 12 for deriving display data corresponding to the address data of the first plurality of pixels successively adjacent to the first and second pixels; and (d) address data calculation means 1, wherein the address from the processing means 12 is Receiving data and selecting unit area selection data (XE3
XE9) and X-direction address data (XE0-XE9) having bit position data (XE0-XE2) indicating which bit in the selected unit area Aij the write or read start address is. (E) address conversion means 70, which is unit area selection data (XE3 to XE9) of the X-direction address data (XE0 to XE9) from the address calculation means 1.
(F) an address difference calculating means, which outputs selection data AX0 to AX3 for selecting the unit area Aij, and (f) an address difference calculating means.
To XE9), the unit areas A9, 70 selected by the address conversion means 70 in response to the bit position data (XE0 to XE2).
X-direction start address (24) and the X-direction start address (3
(G) write or read means, wherein the address data and display data corresponding to the address data are output from the processing means 12. The selected unit area A9, 70 and another unit area A10, 7 adjacent to the selected unit area A9, 70 in the X direction.
Address designation with 0 is performed in this order, and in response to the output of the address difference data SFTi from the address difference calculating means, each bit of the remaining bits of the address difference of the selected unit area A9, 70 Write the display data corresponding to each bit address to the address, write the display data corresponding to each bit address to each bit address of the bit of the address difference of the another unit area A10, 70, or A display control device, comprising: reading means. 2. A display device 11 in which pixels are arranged in an X direction and a Y direction and display data 76 are displayed on the pixels, and (b) a memory device 68, wherein the first plurality of bits are 1 In the X direction, a division by the unit area Aij for each of the first plurality of bits is set adjacent to each other in the X direction. Each bit of the unit area Aij corresponds to each pixel, and the display data for each pixel Display device 11 that stores PM7 to PM0
And (c) the processing means 12, comprising: a plurality of bits of address data for designating a pixel write or read start address (40, 40); and a Y direction from the write or read start address. Processing means 12 for deriving display data corresponding to the address data of the first plurality of pixels successively adjacent to the first and second pixels; and (d) address data calculation means 1, wherein the address from the processing means 12 is Receiving data and selecting unit area selection data (XE3
XE9) and X-direction address data (XE0-XE9) having bit position data (XE0-XE2) indicating which bit in the selected unit area Aij the write or read start address is. (E) address conversion means 70, which is unit area selection data (XE3 to XE9) of the X-direction address data (XE0 to XE9) from the address calculation means 1.
(F) an address difference calculating means, which outputs selection data AX0 to AX3 for selecting the unit area Aij, and (f) an address difference calculating means.
To XE9), the unit areas A4, 40 selected by the address conversion means 70 in response to the bit position data (XE0 to XE2).
X-direction start address (40) and the X-direction start address (4
(G) write or read means, wherein the address data and display data corresponding to the address data are output from the processing means 12. In this case, the address designation of the first plurality of unit areas A4, 40 to A4, 47 which are adjacent to the selected unit areas A4, 40 in the Y direction from the selected unit areas A4, 40 is performed in this order. In response to the output of the address difference data SFTi from the address difference calculating means, the selected unit areas A4 and 40 are output from the selected unit areas A4 and 40.
A total of 4,40 unit areas A adjacent in the Y direction
A display control device, comprising: a writing or reading means for sequentially writing display data corresponding to each bit address of each of the bits of the address difference of 4,40 to A4,47. 3. Address conversion means (X direction 70 and Y direction
3. The display control device according to claim 1, wherein the display control device comprises a read-only memory.