JP2731028B2 - Display control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device that performs display control on display means such as a liquid crystal display device.

FIG. 8 is a block diagram showing a configuration of a typical conventional display control circuit 101. As shown in FIG. The display control circuit 101 includes, for example, a common drive circuit 103 that drives a common electrode of a liquid crystal display element 102 of a simple matrix type, a segment drive circuit 104 that drives a segment electrode, and outputs address data and display data to these drive circuits 103 and 104. And a CPU (Central Processing Circuit) 105, which are mutually connected by a bus line 106.

The CPU 105 reads and stores the display data stored in the segment driving circuit 104 and the display data displayed on the liquid crystal display element 102, which is stored in the segment driving circuit 104, and the write buffer 107 that holds the write data written at a predetermined address of the liquid crystal display element 102. .
A read buffer 108, an arithmetic circuit 109 for performing one of a plurality of types of arithmetic operations on the contents stored in each of the buffers 107, 108, a common drive circuit 103 and a segment drive circuit for holding the arithmetic result and at a predetermined timing 104
And a result buffer 110 for transferring data to the memory. Each buffer 107, 108, 110 has a capacity of, for example, 8 bits, and the symbol "." Shown in the figure represents the most significant bit (MSB) in the 8-bit data.

Hereinafter, a case will be described in which a write LOOP instruction for continuously writing display data in a subsequent address range of the liquid crystal display element 102 is executed.

After transferring the write address where the first display data is written from the CPU 105 to the segment driving circuit 104, the CPU 105
After setting the display data in the write buffer 107 within
The arithmetic circuit 109 performs a predetermined arithmetic operation, stores the result in the result buffer 110, and then transfers the result to the segment driving circuit 104.
Thereafter, the same processing is performed for the succeeding next write address.

That is, in this conventional example, display data is stored in a liquid crystal display element.
When a write command is continuously performed over the subsequent address range of 102, it is necessary to specify a write address for each address, and the operation result of the result buffer 110 is also temporarily saved to another place, and the next At the time of a write command, it is necessary to perform processing such as reading again and transferring it to the segment drive circuit 104. When such processing is performed by the CPU 105, the processing is performed by software processing, and thus there is a problem in that display processing takes time.

When the CPU 105 performs a block transfer LOOP instruction for reading display data from the segment drive circuit 104, the read address of the display data read from the CPU 105 is transferred to the segment drive circuit 104, and then the read data of the address is transferred to the CPU 105. And stores it in the read buffer 108. After various operations are performed on the read data by the arithmetic circuit 109, the read data is stored in the result buffer 110, the write address is transferred to the segment drive circuit 104 by the same processing as the write processing described above, and the display data is transferred. In the case of such a block transfer process, it is necessary to repeat the above-described process for each 8 bits by software processing, and in this case, a problem similar to the above-described problem occurs.

Problems to be Solved by the Invention As described above, when the display processing is performed by software processing, there is a problem that the load of software is large, and the processing requires time, and high-speed display becomes difficult.

An object of the present invention is to solve the above-mentioned technical problems and to provide a display control device that realizes a high-speed display operation in which a load on software is reduced.

Means for Solving the Problems The present invention provides: (a) a display device 11 in which pixels are arranged in an X direction and a Y direction, and display data on the pixels; And a memory device 17 for storing display data for each pixel and displaying the data on the display device 11; and (c) a processing circuit 12, the write start address of the pixel. Address data designating (XW, YW) and display data corresponding to the address data of the first plurality of pixels consecutively adjacent in the X direction from the write start address (XW, YW). A processing circuit 12 for deriving loop number data n; and (d) a data register 36 for storing display data for a first plurality of pixels from a write start address from the processing circuit 12.
(E) a memory control device 40 that outputs a write command LR / W to the memory device 17; and (f) a loop count register that counts the number of times the write command of address data and display data to the memory device 17 is performed. (G) X-direction write start address XW from the processing circuit 12
And (h) a write start address YW in the Y direction from the processing circuit 12.
(I) an X-direction arithmetic circuit 43 for calculating the stored contents of the X-direction write address register 41X each time the write instruction is executed; and (j) an X-direction operation circuit 43 for each time the write instruction is executed. (K) Each time the write command is issued, the Y-direction arithmetic circuit 44 calculates the stored contents of the Y-direction write address register 41Y. Means for writing the display data stored in the data register 36 for the bit unit into the memory device 17 from the address calculated by at least one of the direction calculation circuit 43 and the Y-direction calculation circuit 44. Is a display control device.

The present invention also provides (a) a display device 11 in which pixels are arranged in the X direction and the Y direction and displays display data on the pixels, and (b) a memory device 17, wherein the read start address (X
R, YR), a first plurality of bits successively adjacent to each other in the X direction can be transferred as one bit unit. (C) the processing circuit 12, which derives address data designating a pixel read start address (XR, YR) and a write start address (XW, YW), derives loop number data n, (D) an X-direction read address register 42X for storing an X-direction read start address XR; and (e) a Y-direction read address register 42Y for storing a Y-direction read start address YR. (F) an X-direction write address register 41X for storing the X-direction write start address XW; and (g) a Y-direction write address register for storing the Y direction write start address YW. And 41Y, (h) a memory device 17 in the X and Y directions of the read start address register 42X, from the addressed address by 42Y, the display data of the first plurality of pixels,
X direction and Y direction write start address registers 41X, 41
A loop count register 31 for counting the number of times a transfer command is transferred from the address specified by Y to the address of the first plurality of pixels; and (i) an X-direction read address each time the transfer command is performed. Register 42X and X direction write address register 41X
(J) Each time the transfer instruction is performed, a Y-direction read address register 42Y and a Y-direction write address register 41Y
And (k) an X-direction operation circuit 43 and a Y-direction operation until the loop number data n is counted by the loop number register 31 each time the transfer instruction is executed. The memory device 17 addressed by the X-direction read address register 42X and the Y-direction read address register 42Y calculated by at least one of the circuits 44, respectively.
From the address of
Means for writing to the address of the memory device 17 addressed by the direction write address register 41X and the Y direction write address register 41Y.

Action According to the invention of claim 1, a memory device which is a segment drive circuit, as described in particular below with reference to FIG.
In 17, the processing circuit 12 sends a pixel write start address (XW, Y
W) and the display data of a first plurality (for example, 8) pixels continuous in the X direction from the write start address are transferred, written, and displayed on the display device 11. The device 40 has a write instruction LR / W
Are sequentially output, and the loop count register 31 outputs the write instruction by at least one of the X-direction operation circuit 43 and the Y-direction operation circuit 44 until the loop number data n derived from the processing circuit 12 is counted. The processing circuit stored in the data register 36 for the first plurality of bits from the address of the memory device 17 calculated respectively.
The display data from the address 12 is written, and the address is stored in the X-direction write address register 41X and in the Y-direction write address register 41Y.
And at least one of the Y-direction operation circuit 44. Therefore, the processing circuit 12 does not calculate the address of the memory device 17 in which such writing is performed by software processing, and the processing circuit 12 calculates the address data of the writing start address (XW, YW) and the first plurality of addresses. Only the display data for the pixels are output, and the operation of the address for the loop number data n is performed by the above-described loop number register 31, the X direction write address register 41X, the Y direction write address register 41Y, and the X direction operation circuit 43. And the operation of the Y-direction operation circuit 44. Thus, the load on the software of the processing circuit 12 is reduced, and the display processing is sped up.

According to the second aspect of the present invention, as described later with reference to FIG. 7, the display data of the memory device 17 displayed on the display device 11 has a first plurality (for example, 8) of one bit. The data is transferred as a unit, and the processing circuit 12
Is to derive address data designating a read start address (XR, YR) and a write start address (XW, YW) of the pixel, derive loop number data n, and further output a transfer instruction. , This gives X
Direction read address register 42X, Y direction read address register 42Y, X direction write address register 41X, Y
A direction write address register 41Y is provided, a loop count register 31 is provided, and an X direction operation circuit 43 and a Y direction operation circuit
And a memory device addressed by at least one of the X-direction operation circuit 43 and / or the Y-direction operation circuit 44 until the loop number register 31 counts the loop number data n in order to execute a transfer instruction.
From 17 addresses, X direction write address register 41X
Then, the display data of the first plurality (for example, 8) of bit units are transferred to the address specified by the Y-direction write address register 41Y and written into the memory device 17. In this way, the load on the software for the display processing of the processing circuit 12 is reduced, and the display processing can be sped up.

Embodiment FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2 using a common drive circuit 1, and FIG. FIG. The data processing device 2 has a so-called notebook size, and the first operation unit 3 and the second operation unit 4 are configured to be freely opened and closed by a coupling unit 5. The second operation unit 4 includes a cursor key 6, a function setting key 7, a character input key 8, a numeric key 9, and the like. On the other hand, on the first operation unit 3, a so-called transparent touch key 10 and a liquid crystal display device 11 are arranged.

Such a data processing device 2 includes, for example, a CPU (central processing circuit) 12 including a microprocessor or the like.
The CPU 12 has the transparent touch key 10 and the second
A RAM (random access memory) 13 to which each key input means of the operation unit 4 is connected and which is used as a storage area for various input data and a working area for data during operation, and a CPU
A ROM (read only memory) 14 in which programs for defining the control operations of 12, font data for display, calendar data, and the like are stored is connected.

Further, the CPU 12 has a timing circuit 15 for timing, a common drive circuit 1 for controlling the display operation of the liquid crystal display device 11 as described later, and a common drive circuit 1 based on a contrast signal from the common drive circuit 1. The liquid crystal power supply circuit 16 is connected to a liquid crystal power supply circuit 16 that changes the operating state / stop state according to a control signal from the CPU 12. The common drive circuit 1 has a plurality (8 in this embodiment).
), And controls the display state of the liquid crystal display device 11 together with the common drive circuit 1. The liquid crystal display device 11 has a common electrode 1 on a pair of transparent substrates 11a and 11b.
1c, a segment electrode 11d is formed, and a liquid crystal layer 11e is interposed therebetween.

A block diagram of the common drive circuit 1 is shown in FIG. The common drive circuit 1 is supplied with a write / read control signal R / W, a clock signal φ, a busy signal BY, a chip enable signal CE, and the like from the CPU 12, and a control circuit 19 to which address data AD, display data DI, and the like are supplied. Is provided. The display data DI is input through the buffer 20. Further, the common drive circuit 1 outputs a frame signal
FR, a control signal DIS that controls ON / OFF of display by the segment electrode, and a clock signal LCK are used as segment drive circuits.
Output to 17. As described above, such a data processing device 2 is a notebook-sized portable device, and
The various reference voltages necessary for the operation of are generated from the power supply circuit 26 connected to the battery 25.

A data processing circuit 21 is connected to the control circuit 19 and the CPU 12
After performing a predetermined logical operation (such as SET, AND, OR, XOR, etc.) on the address data and display data transferred from the device, the data is transmitted to the segment drive circuit 17. The memory control circuit 22 determines to which of the segment driving circuits 17 the address data sent from the CPU 12 is to be transferred, and generates a relative address in any of the selected segment driving circuits 17. The timing generation circuit 23 generates a clock signal used for various arithmetic processing in the common drive circuit 1 and the like, and receives a reference clock signal from the oscillator 24.

The common signal control circuit 27 and the common-side decoder 28 use the clock signal generated by the timing generation circuit 23 to generate a common signal supplied to the common electrode of the liquid crystal display device 11. The control circuit 19 is connected to a window processing circuit 29 having a configuration and an operation as described later.The contrast adjustment circuit 46 stores the display density on the liquid crystal display device 11, and the density data is set from the CPU 12. . The contrast adjustment of the liquid crystal display device 11 is performed by the liquid crystal power supply circuit 16 shown in FIG. 2 based on the density data in the contrast adjustment circuit 46, and the liquid crystal power supply potential from the liquid crystal power supply circuit 16 is taken into the common drive circuit 1. LCD voltage input section for
17a is provided.

FIG. 4 is a block diagram showing a specific configuration example of the common drive circuit 1. The control unit 30, the loop counter 31, the command register 32, the status register 33, and the data control circuit 34 constitute the control circuit 19 in FIG. The control unit 30 controls the whole of the common drive circuit 1, and the loop counter 31 manages the number of times the command data set from the CPU 12 in the command register 32 is continuously executed. The status register 33 stores the current operating state of the common drive circuit 1, and the CPU 12
The CPU 12 can detect the operation state of the common drive circuit 1 by reading out the stored contents of the common drive circuit 1. Data control unit
Numeral 34 denotes data transmission / reception with the CPU 12 via the buffer 20.
Manage reception.

Operation circuit 35, data register 36, operation mode register
37 and a mask register 38 are data processing circuits shown in FIG.
The arithmetic circuit 35 forms various logical operations (SET, OR, AND, XOR, etc.) specified by the operation mode register 37 between data from the CPU 12 stored in the data register 36 and segment data described later. When the operation state of the common drive circuit 1 is a write operation state in which data is transferred to the segment drive circuit 17 which is a memory device of the present invention, the obtained data is transferred to the segment drive circuit 17 and the CPU 12
In the case of a read operation state in which data is transferred to the CPU 12, the obtained data is transferred to the CPU 12 via the data control unit.

At this time, the arithmetic processing may be masked by the data of the mask register 38. That is, a case where the calculation is not performed is set. The execution mask data obtained by the window processing circuit 29 as described later is also masked based on the data of the mask register 38.

The memo control circuit 22 includes a write address register 41
X, 41Y and read address registers 42X, 42Y, and the write start address (X
When the CPU 12 stores the read start address (XR, YR) or the read start address (XR, YR) as an absolute address, the memory control unit 40
Outputs selection signals LCE1 to LCE8 for selecting any one of, for example, eight segment drive circuits 17 shown in FIG.
Further, it outputs to each segment drive circuit 17 a control signal LR / W for setting either the write operation state or the read operation state. The addition and subtraction circuits 43 and 44 are provided in the address registers 41X and 41.
Y: After executing the command such as writing the address data of 42X and 42Y, an operation of automatically incrementing or decrementing by ± 8 or ± 1 is performed according to the designation of the addition / subtraction register 45.

The window processing circuit 29 has a window pointer memory 47.
The liquid crystal display device 11 stores two pairs of address data sets each of which defines a plurality of rectangular window regions which are preset in the liquid crystal display device 11 by the number of window regions. The data stored in the window pointer memory 47 is subtracted by a data conversion circuit 49 in a subtraction circuit 48 by using a data conversion circuit 49 to convert the absolute addresses (XW, YW); (XR, YR) stored in the address registers 41X, 41Y; The data is compared with the data obtained by the conversion, and a mask pattern as described later is created and stored in the mask pattern memory 50.

As described above, generally, a plurality of window areas are set in the liquid crystal display device 11, and the number of the display area in which the current data is to be written or read is determined as the number of the window area. The data is stored in the window pointer 51, and the window processing described below is performed for each window area until the current window pointer 52 matches the number data of the window pointer 51 from the 0th page. Outputs the end signal of the mask pattern.

A window mask pattern overlapping process, which will be described later, is performed by the first overlapping unit 54, and the obtained window mask pattern is stored in the window mask unit 55. The second superposition unit 57 performs superposition processing of the superimposed window mask pattern obtained by the first superposition unit 54 and a bit mask register 56 that can specify data for each bit according to the setting from the CPU 12. The finally obtained execution mask is stored in the execution mask unit 58. The arithmetic circuit 35 performs various logical arithmetic processing between the execution mask and the segment data from the buffer 39.

FIG. 5 is a block diagram schematically showing the configuration of the data processing device 2. As shown in FIG. As described above, the common drive circuit 1 and the segment drive circuit 17 are connected to the liquid crystal display device 11, and output common address data and segment address data, respectively, and display data is output from the segment drive circuit 17. In this case, the CPU 12 is the common drive circuit 1
The segment drive circuit 17 performs a mutual transfer between the common drive circuit 1 and the display data and the drive address data between the common drive circuit 1 and the CPU 12. The configuration is not performed.

The common drive circuit 1 includes a write buffer 61 for storing write data from the CPU 12 and a read buffer 62 for storing read data read from the segment drive circuit 17.
An arithmetic circuit 63 for performing an arithmetic operation to be described later on the data stored in each of the buffers 61 and 62;
And a result buffer 64 for storing the result of the operation.
Further, a loop count register 65 for storing the loop count data sent from the CPU 12 regarding the number of repetitions of the calculations performed up to the arithmetic circuit 63, and display control data such as a write address in the next write process following one write process. Is provided in the display control data register 66.

Here, the write buffer 61 is the data register 36, and the write buffer 62 is the buffer 39. The arithmetic circuit 63 is the arithmetic circuit 35 shown in FIG. 4, and the result buffer 64 is realized as the buffer 39. The loop count register 65 is the loop counter 31, and the display control data register 66 is the addition / subtraction register 45.

FIG. 6 is a diagram showing a display example of the liquid crystal display device 11.
In the present embodiment, the display on the liquid crystal display device 11 is performed in units of S bits with the display start address (XW, YW) as the most significant bit in the case of a write command. Continuous write LOOP
Prior to executing the instruction, the CPU 12
The operation mode register 37 specifies the type of operation (SET, OR, AND, XOR, etc.) to be performed on the write data, and the write start address (XW, YW) shown in FIG. Are respectively stored.

In the case of a continuous write LOOP instruction, the write instruction is repeatedly processed a plurality of times. In this case, the loop count data is stored in the loop count register 65, that is, the loop counter.
The designation in the display control data register 66, that is, the addition / subtraction register 45, is stored in the display control data register 66, where the write start address is set in the next write process following the one write process. For example, 0, ±
Arbitrary control data of 1, ± 8 can be set. Correspondingly, the write start address for each write command in the X and Y directions is unchanged, ± 1 increase / decrease, ± 8 increase / decrease. Is set.

After such preprocessing, when the write data, that is, the display data is transferred from the CPU 12 to the write buffer 61, that is, the data register 36, the common drive circuit 1 performs a predetermined operation on the write data in the write buffer 61 by the arithmetic circuit 63. Then, the operation result stored in the result buffer 64 is transferred to the segment driving circuit 17.

In the image G1 of FIG. 6, each time the write data is written, the address in the X direction does not change, and the address in the Y direction is incremented by +1. That is, in FIG. 4, the display control data is set to "0" in the addition / subtraction circuit 43, and the display control data is set to "1" in the addition / subtraction register 45. Here, when the loop number data n is set in the loop number register 65, the count value of the loop number register 65 is decremented by -1 each time a write instruction is performed, and when the count value becomes 0, that is, the loop number data n is counted. Then, the write instruction is stopped. That is, in the image G1, the write start address (XW, Y
The display data of 8 bits is written over the address range of (W) to (XW, YW + n).

In the image G2 shown in FIG. 6, display is realized by the same display processing as that of the display processing of the image G1, but in this case, the addition and subtraction circuits 43 and 44 are set by setting the display control data register 66, that is, the addition and subtraction register 45. For example, the display control data “1” is set in each of the cases.

FIG. 7 is a diagram showing another display example of the present embodiment. This embodiment shows a case in which the image G3 on the liquid crystal display device 11 on which the read start address (XR, YR) is displayed is moved to an area starting from the write start address (XW, YW) as the image G4. Thus, the processing command for the image already displayed on the liquid crystal display device 11 is the block transfer LOOP command.

Prior to the execution of this instruction, the read start address (XR, YR) of the image to be read in the liquid crystal display device 11 and the write address when the read data after the arithmetic processing are written in the liquid crystal display device 11 are shown in FIG. The data is stored in the write address registers 41X and 41Y and the read address registers 42X and 42Y. The designation of the read address after one transfer process is set in the display control data register 66, that is, the addition / subtraction register 45.

After such preprocessing, block transfer LOOP
When the instruction is transferred to the common drive circuit 1, the common drive circuit 1 sends a predetermined read address (X
R, YR) is read out to the read buffer 62 and subjected to a predetermined operation by the arithmetic circuit 63.
The operation result stored in the write address register
Write to the write start address (XW, YW) specified by 41X, 41Y.

If the loop count data n is set in the loop count register 65, the read data over the read start address range (XR, YR) to (XR, YR + n) in the liquid crystal display device 11 is changed to the write data range. (XW, YW) ~
It will be written in the address range of (XW, YW + n). In this display example, the write address registers 41X and 41Y and the read address register 4
In this case, data 0 is set in the X direction and data +1 is set in the Y direction for both 2X and 42Y. In such a loop process, the count value of the loop number register 65 is 0.
Stop when it becomes.

As described above, in the present embodiment, the continuous write LOOP command, the block transfer LOOP command, and the like used for various display operations in the liquid crystal display device 11 are realized by the hardware provided in the common drive circuit 1. As a result, it is possible to reduce the load on the hardware that regulates the operation of the data processing device 2, and to speed up the display operation.

According to the first aspect of the present invention, as described above with reference to FIG. 6 in particular, the processing circuit 12 includes the address data for designating the write start address (XW, YW) of the pixel and the first data. The display data for a plurality of (for example, 8) pixels are derived, and the loop count data n is derived, whereby the address for the write operation to the memory device 17 can be written by the write command LR / Since the calculation is performed by the loop count register 31 by W, the X-direction write address register 41X, the Y-direction write address register 41Y, the X-direction operation circuit 43, and the Y-direction operation circuit 44, the software load on the processing circuit 12 is reduced. The display processing can be sped up.

According to the second aspect of the present invention, the processing circuit 12 specifies the read start address (XR, YR) and the write start address (XW, YW) of the pixel, as described above with reference to FIG. In addition to deriving the address data, deriving the loop count data n and outputting the transfer instruction, the address for transferring the read and write display data of the memory device 17 is changed to the X-direction read address register 42X,
Y direction read address register 42Y, X direction write address register 41X, Y direction write address register 41Y,
Since the address calculation is performed by the loop count register 31, the X-direction operation circuit 43, and the Y-direction operation circuit 44, the load on the software of the processing circuit 12 is reduced, and the display processing can be sped up.

[Brief description of the drawings]

1 is a block diagram of a common drive circuit 1 according to one embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2, FIG. 3 is a plan view of the data processing device 2, and FIG. 1 is a block diagram showing a configuration example, FIG. 5 is a block diagram schematically showing a configuration related to the liquid crystal display device 11, FIGS. 6 and 7 are diagrams showing a display example of the present embodiment, and FIG. 1 is a block diagram illustrating a configuration example of a typical conventional display control circuit 101. FIG. DESCRIPTION OF SYMBOLS 1 ... Common drive circuit, 2 ... Data processing device, 11 ... Liquid crystal display device, 17 ... Segment drive circuit, 61 ... Write buffer, 62 ... Write buffer, 63 ... Operation circuit, 64 ... Result buffer, 65 ... Loop count register, 66… Display control data register

Claims (2)

(57) [Claims] 1. A display device 11 in which pixels are arranged in an X direction and a Y direction and display data is displayed on the pixels, and (b) a memory device 17, wherein the first plurality of bits are A memory device 17 that is writable in bit units, stores display data for each pixel, and causes the display device 11 to display the data; and (c) a processing circuit 12, which stores a pixel write start address (XW, YW). From the specified address data and the write start address (XW, YW), display data corresponding to the address data of the first plurality of pixels successively adjacent in the X direction is derived, and the loop count data n And (d) a data register 36 for storing display data for a first plurality of pixels from a write start address from the processing circuit 12.
(E) a memory control device 40 that outputs a write command LR / W to the memory device 17; and (f) a loop count register that counts the number of times the write command of address data and display data to the memory device 17 is performed. (G) X-direction write start address XW from the processing circuit 12
And (h) a write start address YW in the Y direction from the processing circuit 12.
(I) an X-direction arithmetic circuit 43 for calculating the stored contents of the X-direction write address register 41X each time the write instruction is executed; and (j) an X-direction operation circuit 43 for each time the write instruction is executed. (K) Each time the write command is issued, the Y-direction arithmetic circuit 44 calculates the stored contents of the Y-direction write address register 41Y. Means for writing the display data stored in the data register 36 for the bit unit into the memory device 17 from the address calculated by at least one of the direction calculation circuit 43 and the Y-direction calculation circuit 44. A display control device characterized by the above-mentioned. 2. A display device 11 in which pixels are arranged in an X direction and a Y direction and display data is displayed on the pixels, and (b) a memory device 17, wherein a read start address (X
R, YR), a first plurality of bits successively adjacent to each other in the X direction can be transferred as one bit unit. (C) the processing circuit 12, which derives address data designating a pixel read start address (XR, YR) and a write start address (XW, YW), derives loop number data n, (D) an X-direction read address register 42X for storing an X-direction read start address XR; and (e) a Y-direction read address register 42Y for storing a Y-direction read start address YR. (F) an X-direction write address register 41X for storing the X-direction write start address XW; and (g) a Y-direction write address register for storing the Y direction write start address YW. And 41Y, (h) a memory device 17 in the X and Y directions of the read start address register 42X, from the addressed address by 42Y, the display data of the first plurality of pixels,
X direction and Y direction write start address registers 41X, 41
A loop count register 31 for counting the number of times a transfer command is transferred from the address specified by Y to the address of the first plurality of pixels; and (i) an X-direction read address each time the transfer command is performed. Register 42X and X direction write address register 41X
(J) Each time the transfer instruction is performed, a Y-direction read address register 42Y and a Y-direction write address register 41Y
And (k) an X-direction operation circuit 43 and a Y-direction operation until the loop number data n is counted by the loop number register 31 each time the transfer instruction is executed. The memory device 17 addressed by the X-direction read address register 42X and the Y-direction read address register 42Y calculated by at least one of the circuits 44, respectively.
From the address of
Means for writing to the address of the memory device 17 addressed by the direction write address register 41X and the Y direction write address register 41Y.