JPH0497292A - Display control circuit - Google Patents

Abstract

PURPOSE:To reduce the load of software for regulating operation and to rapidly execute display processing by executing display processing in plural addresses and various operation due to the display processing by a hardware stored in a row direction driving means. CONSTITUTION:A control means 12 outputs address data and display data to the column direction driving means 1, the means 1 stores operational frequency data obtained from the means 12 in a frequency storage data storing means 65 and stores display control data relating to the display status of computed result display data in a display control data storing means 66 and an arithmetic means 63 executes the operation of the display data outputted from the means 12 and a row direction driving means 17 based upon the operational frequency data. The computed result is outputted to the means 17 together with driving address data, the column direction address is outputted and displayed to/on a display device 11. Consequently, the load of the software for regulating operation can be reduced and display processing can rapidly be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display control circuit that controls display in a display means such as a liquid crystal display device.

BACKGROUND ART FIG. 8 is a block diagram showing the configuration of a typical conventional display control circuit 101.1 The display control circuit 101 is a common drive circuit that drives a common electrode of a simple matrix type liquid crystal display element 102, for example. 103, a segment drive circuit 104 that drives the segment ti, and a CPU (central processing circuit) 105 that outputs address data and display data to these drive circuits 103 and 104.
These are connected to each other by a pass line 106.

The CPU 105 has a write buffer 10 that holds write data to be written to a predetermined address of the liquid crystal display element 102.
7, display data stored in the segment drive circuit 104 and displayed on the liquid crystal display element 102 is sent to the CPU 10.
5 reads and stores the data, and an arithmetic circuit 109 that performs one of a plurality of predetermined types of arithmetic operations on the contents stored in each of these buffers 107 and 108.
and.

The calculation result is held and the common drive circuit 1 is activated at a predetermined timing.
03 and a result buffer 110 that transfers data to the segment drive circuit 104. Each buffer 107, 108, 110.

For example, it has an 8-bit capacity, and the symbol "
.'' represents the most significant bit (MSB>) in 8-bit data.

Hereinafter, a case will be described in which a write LOOP command for continuously writing display data into successive address ranges of the liquid crystal display element 102 is executed.

After transferring the write address where the first display data is written from the CPU 105 to the segment drive circuit 104,
After display data is set in the write buffer 107 in the CPU 105, a predetermined calculation is performed in the calculation circuit 10.
After being stored in the result buffer 110, it is transferred to the segment drive circuit 104. Thereafter, similar processing is performed for the next subsequent write address.

That is, in this conventional example, display data is transferred to the liquid crystal display element 1.
When executing write commands continuously over the consecutive address range of 0'2, it is necessary to specify one write address for each address, and the operation results in the result buffer 110 must also be temporarily saved to another location. , it is necessary to perform processing such as reading the data again and transferring it to the segment drive circuit 104 at the time of the next write command. When such processing is performed by the CPU 105, it is performed by software processing, and therefore there is a problem that display processing takes time.

In addition, the CPU 105 transfers display data to the segment drive circuit 1.
When performing block transfer reading from 04 and executing ○○P command,
After transferring the read address of the display data read from the CPU 105 to the segment drive circuit 104, the read data at the address is transferred to the CPU 105 and stored in the read buffer 108. After the read data is subjected to various calculations in the calculation circuit 109, it is stored in the result buffer 110, and the write address is transferred to the segment drive circuit 104 in the same process as the write process described above, and display data is transferred. In the case of such block transfer processing, it is necessary to repeat the above-mentioned processing every 8 bits by software processing, and in this case, the same problems as those described above occur.7 Problems to be Solved by the Invention As described above. When display processing is performed by software processing, there is a problem that the burden on the software is large and the processing takes time, making high-speed display difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display control circuit that solves the above-mentioned technical problems and realizes high-speed display operation that reduces the burden on software.

Means for Solving the Problems The present invention provides a row direction driving means connected to a display means for displaying addresses set in a matrix in a display area and outputting row direction address data and display data; and a display means. Column direction driving means connected to the row direction driving means and outputting column direction address data to the display means and outputting display data such as drive address data defining the row direction address data to the row direction driving means; The column direction drive means includes a control means for outputting address data and display data to the column direction drive means; a number data storage means for storing calculation number data;
The present invention is a display control circuit characterized by comprising display control data storage means for storing display control data regarding a display state of display data as a calculation result.

According to the present invention, when displaying a plurality of consecutive addresses on the display means in which addresses are set in rows and columns in the display area, the control means sends address data and display data to the column direction driving means. The 0 column direction driving means for outputting the data stores the calculation number data from the control means in the number storage data, and stores the display control data for the display state of the display data of the calculation result in the display control data storage means. Further, the calculation means performs calculations on the display data from the control means and the row direction driving means based on the calculation number data stored in the number data storage means. The column direction driving means outputs the calculation result together with drive address data to the row direction driving means, and also outputs the column direction address to the display means. In this way, display is realized by the display means.

Since display processing over a plurality of consecutive addresses and various calculations associated with such display processing are realized by hardware provided inside the column direction driving means, the operation of the display control circuit is regulated. The burden on the software is reduced and the display processing speed is significantly increased.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2 in which the common drive circuit 1 is used, and FIG. 3 is a block diagram of the data processing device 2.
FIG. This data processing device 2 is so-called a notebook size, and a first operating section 3 and a second operating section 4 are configured to be openable and closable at a connecting section 5. The second operation section 4 is provided with a cursor key 6, a function setting key 7, a character input key 8, a number key 9, and the like. On the other hand, so-called transparent touch keys 10 and a liquid crystal display device 11 are arranged in the first operation section 3 .

Such a data processing device 2 includes, for example, a CPU (central processing circuit) including a microprocessor, etc.
12, and the transparent touch key 10 is connected to the CPU 12.
and a RAM (Random Access Memory) 13 to which each key manual means of the second operation unit 4 is connected, and which is used as a storage area for various input data and a working area for data during movement, and a control operation of the CPU 12. A ROM (read only memory) 14 in which programs, display font data, calendar data, etc. are stored is connected.

Furthermore, the CPU 12 includes a clock circuit 15 for timekeeping, a common drive circuit 1 that controls the display operation of the liquid crystal display device 11 as described later, and a contrast signal that is supplied to the common drive circuit 1 based on a contrast signal from the common drive circuit 1. A liquid crystal power supply circuit 16 is connected to the liquid crystal power supply circuit 16 which changes the liquid crystal power supply potential and which is switched between an operating state B and a stopped state by a control signal from the CPU 12. A plurality of (eight in this embodiment) segment drive circuits 17 are connected to the common drive circuit 1 and control the display layer of the liquid crystal display device 11 together with the common drive circuit 1. The liquid crystal display device 11 includes a pair of transparent substrates 11a,
Common electrode fffillc segment electrode li on llb
d, with a liquid crystal layer lie interposed therebetween.

A block diagram of the common drive circuit 1 is shown in FIG. The common drive circuit 1 is a control circuit that is supplied with a write/read control signal R/W, a clock signal φ, a busy signal BY, a chip enable signal CE, etc. from the CPU 12, and is also supplied with address data AD, display data DI, etc. 19. Of these, the display data DI is input via the buffer 20. Further, the common drive circuit 1 outputs a frame signal FR, a control signal DIS for controlling 0N10FF displayed by the segment electrodes, and a clock signal LCK to the segment drive circuit 17. As described above, such a data processing device 2 is a notebook-sized portable device, and various reference voltages necessary for the operation of the data processing device 2 are generated from a power supply circuit 26 connected to a battery 25.

A data processing circuit 21 is connected to one control circuit, and the CP
L! Logical operations (SET, AND,
R, XOR, etc.), the segment drive circuit 17
Send data to. The memory control circuit 22 is the CPU 12
It is determined to which segment drive circuit 17 the address data sent from is to be transferred, and a relative address in any of the selected segment drive circuits 17 is generated.

The timing generation circuit 23 generates clock signals and the like used for various calculation processes in the common drive circuit 1.
A reference clock signal from an oscillator 24 is provided.

The common signal control circuit 27 and the common side decoder 28 use the clock signal generated by the timing generation circuit 23 to generate a common signal to be supplied to the common electrode of the liquid crystal display device 11. Further, two window processing circuits having the configuration and operation described below are connected to one control circuit, and the contrast adjustment circuit 46 stores the density displayed on the liquid crystal display device 11, and the density data is set by the CPU 12. Ru. Contrast adjustment of the liquid crystal display device 11 is performed by the liquid crystal power supply circuit 16 shown in FIG. 2 based on density data in the contrast adjustment circuit 46, and the liquid crystal power supply potential from the liquid crystal power supply circuit 16 is taken into the common drive circuit 1 A liquid crystal voltage input section 17 is provided for this purpose.

FIG. 4 is a block diagram showing a specific example of the configuration of the common drive circuit 1. The control section 30, loop counter 31, command register 32, status register 33, and data control circuit 34 constitute the control circuit 19 in FIG. The control unit 30 controls the entire common drive circuit 1, and the loop counter 31 inputs CP to the command register 32.
It manages the number of consecutive executions of the command data set from U12. The status register 33 stores the current operating state of the common drive circuit 1, and stores the current operating state of the common drive circuit 1.
By reading the contents stored in the status register 33, the CPU 12 can detect the operating state of the common drive circuit 1. The data control unit 34 manages data transmission and reception with the CPU 12 via the buffer 20.

The arithmetic circuit 35, the data register 36, the arithmetic mode register 37, and the mask register 38 constitute the data processing circuit 21 shown in FIG. AN
(D In the case of a read operation state in which the obtained data is transferred to the segment drive circuit 17 and the data is transferred to the CPU 12, the obtained data is transferred to the CPU 12 via the data control section 34.

At this time, the arithmetic processing may be masked by the data in the mask register 38. In other words, a case is set in which no calculation is performed. In addition, the execution mask data obtained by the two window processing circuits as described later is also masked based on the data in the mask register 38.

The memory control circuit 22 includes a write address register 4
1X, 41Y and read address registers 42X, 4
2Y, and the write address (XW, YW) or read address (XR, Y
R) is stored as an absolute address from the CPU 12, the memory control unit 40 outputs selection signals LCEI to LCE8 for selecting any one of the eight segment drive circuits 17 shown in FIG. It also outputs a control signal LR/W for setting each segment drive circuit 17 to either a write operation state or a read operation state. Addition and subtraction circuits 43 and 44 correspond to the address registers 41X and 41Y.
, 42X, 42Y after executing a command such as writing the address data, according to the specification of the addition/subtraction register 45,
Automatically increments or decrements by ±8 or 1.

The two write processing circuits each include a window pointer memory 47, and use two sets of address data defining a plurality of rectangular window areas preset in the liquid crystal display device 11 as the number of window areas. only. The data stored in the window pointer memory 47 is sent to the address register 41X in the subtraction circuit 48.
, 41Y; Absolute address (XW, YW) stored in 2X, 42Y; (XR, YR) is the data conversion circuit 4
9 and the data obtained by conversion, a mask pattern as described below is created and stored in the mask pattern memory 50.

As mentioned above, a plurality of window areas are generally set in the liquid crystal display device 11, and the number of window areas is determined by the display area in which data is currently being written or read. The data is stored in the window pointer 51, and the current window pointer 52 is set to perform window processing as described later for each window area from the 0th sheet until the number of sheets matches the number data of the window pointer 51. When the number of sheets matches, the matching circuit 53 A mask pattern>' end signal is output.

Wind mask pattern overlay processing, which will be described later, is performed in the first overlay section 54, and the obtained wind mask pattern is stored in the wind mask section 55. 1st
The second superposition section 57 performs superposition processing on the superimposed wind mask pattern obtained by the superimposition section 54 and the bit mask register 56 that can specify data for each bit according to settings from the CPU 12. The execution mask thus obtained is stored in the execution mask unit 58. The arithmetic circuit 35 performs various logical operations between this execution mask and the segment data in the buffer 39.

FIG. 5 is a block diagram schematically showing the configuration of the data processing device 2. As shown in FIG. As mentioned above, the common drive circuit 1 and the segment drive circuit 17 are connected to the liquid crystal display device 11.
Common address data and segment address data are output, respectively, and display data is output from the segment drive circuit 17. In this case, the CPU 12 mutually transfers display data and address data with the common drive circuit 1, and the segment drive circuit 17 mutually transfers the display data and drive address data with the common drive circuit 1. The configuration is such that direct data transmission/reception is not performed.

The common drive circuit 1 includes a write buffer 61 that stores write data from the CPU 12, and a segment drive circuit 1.
A read buffer 62 in which the read data read from 7 is stored, and an arithmetic circuit 63 that performs calculations described later on the data stored in each of these buffers 61 and 62.
and a result buffer 6 that stores the calculation results of the calculation circuit 63.
4 is provided. Furthermore, there is a loop count register 65 that stores loop count data sent from the CPU 12 regarding the number of repetitions of the calculation performed in the arithmetic circuit 63, and a display of write attribution data for the next write process following one write process. A display control data register 66 is provided in which control data is stored.

Here, the write buffer 61 is connected to the data register 36.
The number of write buffers 62 is the three buffers mentioned above. Further, the arithmetic circuit 63 is the arithmetic circuit 35 shown in FIG.
The result buffer 64 is implemented as three buffers. The loop count register 65 is the loop counter 31, and the display control data register 66 is the addition/subtraction register 45.

FIG. 6 is a diagram showing a display example of the liquid crystal display device 11.
In this embodiment, the display on the liquid crystal display device 11 is performed in units of 8 bits, with the display start address (xw, yw) in the case of a write command being the most significant bit. Prior to executing the continuous write LOOP command, the CPU 12 sets the type of operation to be performed on the write data (SET, OR, AND,
R, etc.) and write address registers 41X, 4
1Y is the write start address (xW, Y
W) are stored respectively.

In addition, in the case of a continuous write LOOP instruction, the write instruction is processed multiple times, and the loop count data in this case is stored in the loop count register 65, that is, the loop counter 31, and the The designation of the write start address in the write process is stored in the display control data register 66, that is, the addition/subtraction register 45. The addition/subtraction register 45 has
For example 0. ±1. Any control data within ±8 can be set, and correspondingly, the write start address for each write command can be set to no change, an increase/decrease of ±1, or an increase/decrease of ±8 in the X and Y directions. will be done.

After such preprocessing, when the CPU 12 transfers the write data, that is, the display data to the write buffer 61, that is, the data register 36, the common drive WiJI 11
After performing a predetermined operation on the write data in the write buffer 61 in the arithmetic circuit 63, the operation result stored in the result buffer 64 is transferred to the segment drive circuit 17.

In image G1 in Figure 6, each time write data is written, the address in the X direction does not change, and the address in the Y direction changes.
It is incremented by 1.

That is, in FIG. 4, the display control data in the addition/subtraction circuit 43 is set to "0", and the display control data in the addition/subtraction register 45 is set to "1". Here, when loop number data D is set in the loop number register 65, the count value of the loop number register 65 is decremented by -1 each time a write command is executed, and when the count value reaches 0, the write command is stopped. That is, in image G1, write start addresses (XW, YW) to (xw, yw, +n
) 8-bit display data is written over the address range.

The image G2 shown in FIG. 6 is displayed using the same display processing as described for the display processing of the image G1, but in this case, the display control data register 66, that is, the addition/subtraction register 4
FIG. 7 is a diagram showing another display example of the present embodiment, in which the display control data "1" is set in each of the adder/subtractor circuits 43 and 44 due to the settings in FIG. In this embodiment, the image G3 on which the display start address (XR, YR) on the liquid crystal display device 11 is displayed is
This shows the case where the image G4 is moved to the area starting from the display start address (XW, YW). in this way,
The processing command for the image already displayed on the liquid crystal display device 11 is a block transfer 00P command.

Prior to executing this command, the reading start address (XR, YR
) and the read data after arithmetic processing are displayed on the liquid crystal display device 11.
The write address for writing to is stored in the write address register 41X41Y and the read address registers 42X and 42Y shown in FIG. Further, the designation of the read address after one transfer process is set in the display control data register 66, that is, the addition/subtraction register 45.

After such pre-processing, block transfer L from the CPU 12
When the OOP instruction is transferred to the common drive circuit 1, the common drive circuit 1 reads 8-bit data at a predetermined read address (XR, YR) from the segment drive circuit 17 into the read buffer 62, and performs a predetermined operation in the arithmetic circuit 63. After that, the calculation result stored in the result buffer 64 is written to the write start address (XW, YW) specified by the write address registers 41X, 41Y.

Here, if the loop number data n is set in the loop number register 65, the read data over the address range from the read start address range (XR, YR) to (XR, YR+n) in the liquid crystal display device 11 will be stored in the write data range. It will be written in the address range of (XW, YW) to (XW, YW+n). In this display example, the addition/subtraction circuit 43
．． 44, write address registers 41X, 41Y
and data o in the X direction and data +1 in the Y direction for both read address registers 42X and 42Y.
This is the case when . Such loop processing stops when the count value of the loop number register 65 becomes 0.

As described above, in this embodiment, the continuous write L○○P command, block transfer LOOP command, etc. used for various display movements in the liquid crystal display device 11 are realized by the hardware included in the common drive circuit 1. . This makes it possible to reduce the burden on the hardware that defines the operation of the data processing device 2, and also to speed up the display operation.

Effects of the Invention As described above, according to the present invention, display processing over a plurality of consecutive addresses in the display means and various calculations associated with such display processing are realized by hardware provided inside the column direction driving means. This reduces the burden on the software that regulates the operation of the display control circuit, and greatly speeds up the display process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the common drive circuit n1 according to an embodiment of the present invention, FIG. 2 is a block diagram of the data processing device 2, FIG. 3 is a plan view of the data processing device f2, and FIG. 4 is the common drive circuit. FIG. 5 is a block diagram schematically showing the configuration related to the liquid crystal display device 11, FIGS. 6 and 7 are diagrams showing display examples of this embodiment, and FIG. 1 is a block diagram showing a configuration example of a typical conventional display control circuit 101. FIG. 1... Common drive circuit, 2... Data processing device, 11
...Liquid crystal display device, 17...Segment drive circuit,
61--Write buffer, 62--Read buffer, 6
3... Arithmetic circuit, 64 - Result buffer, 65... Loop count register, 66... Display control data register Agent Patent attorney Number of strokes Keiichiichi X Figure 6

Claims (1)

[Scope of Claims] A row direction driving means connected to a display means for displaying addresses set in a matrix in a display area and outputting row direction address data and display data, a display means and a row direction driving means. a column direction drive means connected to the column direction drive means for outputting column direction address data to the display means and outputting drive address data defining the row direction address data and display data to the row direction drive means; The column direction driving means includes a control means for outputting address data and display data, and the column direction driving means includes a calculation means for performing calculations on the display data from the control means and the row direction driving means, and the calculation number data input from the control means. a memorized number of times data storage means;
1. A display control circuit comprising: display control data storage means for storing display control data regarding a display state of display data as a calculation result.