JP2728663B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to an image processing apparatus, in particular, a high-speed decompression of image data.
The present invention relates to an image processing apparatus that performs the following. [Prior art] Generally, when processing images at high speed,
Software processing is used as the processing.
However, as image data becomes enormous, higher speed is required.
Come. There are two methods for speeding up,
One is a sequential processing type hardware called a pipeline method.
One method is to use hardware, and the other is to place multiple processors.
It is called parallel processing type. The former is image data
The clock frequency increases with the high-speed processing of
is there. On the other hand, the latter requires more processors to be placed in parallel.
As a result, the speed can be increased as much as possible. Extremely
In other words, by placing processors for the number of images,
Attention now because it is possible to get great speed
This is one of the technologies that are being used. By the way, at this time, communication processing between pixels is important.
It is necessary to proceed with the process while performing mutual communication.
In such a parallel processing method, the processor is used for each pixel.
Is not possible when dealing with high-resolution data.
Become. For example, take an image of A4 read at 16 pixels / mm (pel).
When handling, the number of pixels is about 16M pixels (pixels),
It is impossible to have all these processors at the same time. [Problems to be Solved by the Invention] The present invention provides high-speed compression of an image in units of divided areas.
An image processing apparatus for performing parallel processing is provided. [Means for Solving the Problem] To solve the problem, an image processing apparatus according to the present invention is used.
Compresses an image in units of areas divided into predetermined sizes
An image processing apparatus, comprising: a plurality of pixels corresponding to the number of pixels in the area.
Number of memory elements to store image data.
Image memory (corresponding to 291 in FIG. 21 in the embodiment)
And a plurality of processor elements corresponding to the number of pixels in the area.
Element from the plurality of memory elements.
The image data read in parallel is compressed for each area.
In order to achieve this, the processor
Transfers image data calculated in the monitor element
Processor that processes the transferred image data
(In the embodiment, FIG.
And FIG. 23, page 47, line 4 to page 49, line 3)
And characterized in that: Example An example of the present invention will be described below. The configuration of the image processing apparatus of the present embodiment is a
Peripheral parts such as the resource 1 and the processor unit 2 and input / output devices
It consists of part 3. Fig. 1 shows the principle configuration of only the basic part.
The processor unit 2 is stored in the image memory 1.
Have been contacted. N × m at an arbitrary position on the image memory 1
The image data is stored in an n × m processor element 2a.
To the processor unit 2 consisting of
After the high-speed processing, the image data is returned to the image memory 1 again. n
Each processing in an array of × m processor elements 2a
Are performed simultaneously, so-called parallel processing architecture
It is. 9 (a) and 9 (b) show other configurations.
did. In FIG. 9 (a), under the control of the control circuit 94,
The image data from the input side image memory
Multiple in processor unit 92 consisting of support elements
The pixels are subjected to predetermined processing in parallel and stored in the output side image memory 93.
Is stored. On the other hand, in FIG. 9B, there is an image memory 91.
I and 93, the processor unit 92, and the input device 96
The output devices are connected by a common bus. Hereinafter, the image memory 1 will be described in detail. For the sake of simplicity, assume that the image size is 1024 x 1024 pixels,
We will proceed with an image memory having bit / pixel data.
Changing the image size expands the architecture of this embodiment.
Only need to be stretched. Also, processor unit 2 is 4 ×
4 consisting of a total of 16 processor elements 2a
And FIG. 2 is a diagram showing the configuration of the image memory 1. Image
If the configuration is made of 1024 x 1024 pixels as shown in the figure,
If this is divided into 4 × 4 units, 256 × 256 total 64
It is divided into K (= 65536) blocks. Now, this
As shown in Fig. 3, reorganization is performed in 4x4 pixel units, and 4x4 pixels are 64
Assume that there are K (8 bits long data for each pixel
Yes). Therefore, the address space of the memory is 4 × 4 × 64K
Is a three-dimensional address specification. One 64K image in 4x4
Assuming that one memory chip handles the element, 64K
Memory with each address being 8 bits deep in the address space of
・ A chip is required. This is a 512K bit (= 64K byte)
G) requires a memory chip with a capacity of
Is a set of two 256K-bit dynamic RAM (D-RAM)
Use together. That is, 64K of 256K bit D-RAM
A 64K × 8 bit using two × 4 bit configuration
Used. These two memory chips will be recorded in the future.
Called Re-Elent 1a. The above image memory 1 corresponds to 4 × 4 matrix.
Is composed of 16 memory elements 1a. Fig. 4
Shows the configuration of such a 4 × 4 memory element 1a.
Each memory element 1a has a row address and a column address.
Address is specified and the 64k address of one of the 4x4 pixels
Input / output image data of dress space. Row address
A generator 4 and a column address generator 5
Gives an address to each 4 × 4 memory element 1a
I can. Note that memory element 1a is loaded in the DRAM
Address and column address given by time sharing
In this case, only one address generator is required.
At this time, time division of row address and column address
Exchange control is required. Each address from the address generator
4 × 4 pixel memory element
1a can be read / written. That is, once
Simultaneous image data of 4 × 4 pixels by address specification
It can be driven. Therefore, the data line
An 8-bit data line directly from each memory element 1a
Assume that the row address is A (0 ≦ A ≦ 255) and the column address is
Data is B (0 ≦ B ≦ 255) from the image memory 1.
If it is called, the image data
4 × 4 pixels corresponding to the address (A, B) in the figure
Image data having a length of 8 bits is read. Generalize the simultaneous access of multiple pixels and explain
I will tell. FIG. 10 shows one page of the image as it is.
Of the image data of k × l
Divided by the block of pixels, as shown in Fig. 11,
Corresponds to the re-element 1a. Also, a block of k × l pixels
From the end, (0,0), (0,1), (0,2), (0,3) ...
Numbered k × l memory elements as shown in FIG.
This corresponds to the memory unit 1 composed of the element 1a. Thirteenth
The figure shows the memory unit 1 in two dimensions.
You. The memory size to be accessed is a block of k × l pixels.
Since it is a unit of the check size, a block of k × l pixels at an arbitrary position
Even when the lock R is accessed, k × l memories
All elements 1a are accessed and one memo
Access to one address for each re-element 1a
Becomes In this manner, a plurality of k × l adjacent pixels at an arbitrary position in an image
After accessing and reading pixel image data at once
Processing is performed by the processor unit 2. Processor Yu
The image data processed in nit 2 is again k ′ ×
1 'pixel block size, and any position
You can access and write. Where k '= k, l' =
It will be described in the future as l. The above-mentioned memory access of only k ′ × l ′ pixels
To further explain, the processing in processor unit 2
If the processing is spatial filtering, etc.
Access on the writing side than the block size k × l
Block size may be reduced. General
Generally, the block size k ′ × l ′ on the writing side is 1 × 1.
There are many processes that become Also in processor unit 2
Even if the processing to reduce the image is
Access on the write side of the block size k × l
Block size is reduced. Generally, the block size k '× l' on the light side is vertical and horizontal.
Let k '≧ αk, l ′ ≧ βl be the reduction ratio of α and β
The minimum integer to be satisfied is k ', l'. Read and write
Same k × l memory configuration with the same memory
In the case of performing the processing as in the above two examples,
Smaller than the configuration size k × l of the memory unit 1 on the remote side
Must be written to a small size k '× l'.
No. In this case, k × l squares of the memory element 1a are used.
Do not give access to everything, and write
Mask the memory element 1a so that it is not accessed
Must. However, k × l memories
・ The image memory 1 composed of the elements 1a
Data that can be accessed and read
The maximum number is k × l, but smaller neighboring
K ′ × l ′ image data is also
Can be freely accessed. Mask and only k '× l'
Accessing at the same time depends on the chip of memory element 1a.
It is easily possible by operating the enable of the loop. Next, the memory access of a predetermined pixel at an arbitrary position is sequentially performed.
In the embodiment of the process, the memory unit configuration is 4 × 4
And k × l are explained, and the mask mask
The control of the chip enable for this is also described. First, when the block size k × l is 4 × 4
An example is shown. FIG. 5 is an enlarged view of a part of FIG. Image
Reads image data of an arbitrary 4 × 4 block S in the memory 1.
After processing it in the processor unit 2
In the process for transferring to an arbitrary 4 × 4 block T,
explain about. 4 × 4 squares in FIGS. 5 and 6
Separates 4x4 16 memory elements 1a
Eyes. Aa, A are temporarily stored in these 16 memory elements 1a.
Name them b,…, Ba, Bb,… Ca,… Dc, Dd. First of all
When reading a 4 × 4 block S, 16 memory
Of the element 1a, the memory element Dd (low load
(N, M) is given as the address, column address).
(N, M + 1) is assigned to memory elements Db, Dc, and Dd.
(N + 1, M) remaining memory for elements Ad, Bd, Cd
The elements are given (N + 1, M + 1). this is
Row address generator 4 and column address described above
Generated by the generator 5 Also, 4 × 4 block
Once the position of the end point u of the stick S is determined, its horizontal direction and vertical
Divide the position address in the direction by 4 and calculate the remaining numbers n and m.
Lower row allocated to memory elements Aa to Dd
It is clear that dress and column addresses are uniquely determined.
is there. Assuming that the position address of u is u (Y, X), Y = 4N + n (n = 0,1,2,3) X = 4N + m (n = 0,1,2,3) For example, the address generators 4,5 Then, the information of M and N and m,
n information into a lookup table, etc.
Output address given to elements Aa to Dd
It is conceivable. At this time, the output is M, N, M + 1, N + 1
Is clear from the above description. Also this
Utilizing the properties, as shown in Fig. 7,
Input n or m to the device and output 0,1 according to this value
The address N given to the memory elements Aa to Dd or
Should control whether M is incremented or not.
No. The row address generator 4 uses n and N,
In the column address generator 5, m and M are used. Thus, 4 × 4 16 memory elements
As described above, address generators 4 and 5
Address, you can get 16 data at the same time
You. These 16 data are stored in processor unit 2
Without any processing, or without any processing,
And transferred to a 4.times.4 block T shown in FIG. Only
While reading from the 16 memory elements Aa to Dd
Image data is not necessarily the same memory element
Are not necessarily transferred to the comments Aa to Dd. 4x in Fig. 5
4 memory blocks S are converted to 4 × 4 memory blocks T.
If it is sent, the memory
The data read from the memory element Aa is stored in the memory
• Must be transferred to element Dc. Then, the 4 × 4 memory blocks S and T assign their endpoints u and v.
At the desired position (Y, X), (Y ', X')
The 16 read data of the memory elements Aa to Dd
Which memory element of the re-elements Aa to Dd
I will explain if it should be included. As shown in FIG. 5, Y = 4N + n (n = 0, 1, 2, 3) X = 4N + m (m = 0, 1, 2, 3) Y '= 4P + p (p = 0, 1, 2, 3) X '= 4Q + q (q = 0,1,2,3), pn = 4y' + y (y '=-1,0 y = 0,1,2,3) ... qm = 4x '+ X (x' =-1,0 x = 0,1,2,3) ... x and y are obtained. First, a row array A consisting of (Aa, Ab, Ac, Ad) is shifted rightward by x
Rotate once. This is named a row array A '.
Similarly, row arrays B, C, and D were rotated x times to the right.
Those are named row arrays B ', C', D '. Next, an array (ABCD) 'composed of row arrays A', B ', C', and D '
Is rotated downward y times. In the case of Fig. 5, n, m, p, q are 3,3,2,1 from Fig.5.
Is clear, y '=-1, y = 3, x' =-1,
Obtain x = 2. Therefore, the following matrix is obtained from the above description. When rotated twice to the right, the row array A '= (Ac, Ad, Aa, Ab) B' = (Bc, Bd, Ba, Bb) C '= (Cc, Cd, Ca, Cb) D' = (Dc, Dd, Da, Db) When rotated downward three times, (Bc, Bd, Ba, Bb) (Cc, Cd, Ca, Cb) (Dc, Dd, Da, Db) (Ac, Ad, Aa, Ab)… Compare this matrix with the basic array below
And Aa, Ab, Ac, Ad Ba, Bb, Bc, Bd Ca, Cb, Cc, Cd Da, Db, Dc, Dd ... Basic array The basic array is the read data of memory elements Aa to Dd.
Are arranged two-dimensionally from left to right and top to bottom.
The matrix is written in memory elements Aa-Dd.
The two-dimensional array of data to be inserted
Hit. That is, as an example, read from memory element Aa
In the array, the output data is written in the fourth row and third column.
I will be absorbed. If you refer to this basic array, the 4th row and 3 columns
Since it is Dc in your eyes, make a note on memory element Dc.
What is necessary if read data of re-element Aa is written
I understand. To give a supplementary explanation, the memory element Aa shown in FIG.
It is only necessary that the read data be written to the location of Dc.
As you can easily notice, the displacement from Aa to Dc
Equal to the displacement from u to v from the address. Also, memory
Since the configuration of element 1a is 4 × 4, horizontal and vertical
The remainder of dividing the direction position by 4 is the memory element
Can be considered as the displacement x, y of. For example, if u, v displacement is a multiple of 4,
If there is, the displacement x, y becomes 0, and a certain memory element
The data read from
It is written to the memory element. The hardware implementation of the above processing will be briefly described.
You. FIG. 8 shows 4 × 4 16 memory elements 1a.
Data read simultaneously from memory element 10
Data is processed by the processor unit 2 and the data
In the x-displacement rotator 81 for each of the four elements
Rotate by number. Then y displacement rotation
Rotate by the number of y according to tab 82, and
Aa ~ Ad, Ba ~ Bd, Ca ~ Cd, Da ~ Dd
The configuration is such that the data is written to the port 1a. The y-displacement rotator 82 has four inputs each.
Data, so four exactly the same as x displacement rotator 81
It goes without saying that it can be composed of Also, the rotator
Has the same number of bits as the depth of the memory data.
Good, one bit deeper to memory data deeper
Needless to say, the same number as above may be used. or,
Rotator can use shift register, barrel shifter, etc.
It is easy to guess. Considering this more generalized, the memory block is k
Xl size, the memory element 10
The configuration is also k × 1. In this case, k at an arbitrary position
Xl memory block S is processed by processor unit 2.
After processing, the memory block T of k × l at an arbitrary position
When transferring, Y = kN + n (n = 0,1, ..., k-1) X = lM + m (m = 0,1, ..., l-1) (N, M, P, Q are 0,1,2 , 3 ...) Y '= kP + p (p = 0,1, ..., k-1) X' = lQ + q (q = 0,1, ..., q-1) where the position address of the end point of S is (Y, X), the position address of the end point of T is (Y ', X') ... (1
0) The following n, m, p, q are obtained, and pn = Ky '+ y (y' = 1,0, y = 0,1,2,3, ..., k-1) qm = lx ' + X (x '=-1,0, x = 0,1,2,3, ... l-1) ... (1
1) Using x and y, for example, the x displacement rotation shown in Fig. 8
The processing should be performed using the data 81 and y displacement rotator 82.
No. In this case, the x displacement rotator 81 has l inputs.
That is, a shift from 0 to l-1 can be performed. y displacement lowey
Data 82 has k inputs and shifts from 0 to k-1
it can. Moreover, the k inputs of the y displacement rotator 82 are
Since each element has l elements, a rotator with one input element
Becomes l configurations. As shown in FIG. 10, the k '× l'
Control of memory elements for time access
Will be described. The position address of the block end point i of k ′ × l ′ is (f,
g). Method to access according to the above formula (10)
To read memory, substitute f and g for Y and X and access
If writing to memory to be performed, substitute f and g for Y 'and X'
You. By substituting the result into equation (11) to obtain y, x,
Generalization of the embodiment shown in FIGS. 7 and 8 to k × l
Can be applied as is. At this time, of the k × l memory elements,
Enable only k '× l' memory elements
To This enable chip is k '× l'.
If only the position address of (f, g) of the end point i is determined, the equation (1)
0), n, m or p, q are uniquely determined, and all
K ′ × l ′ memory elements are also uniquely determined.
You. By the way, as described above, the memory element of k × l
Read access side in a memory configuration consisting of
To the block of k '× l' at the same time,
To access the block of k ″ × l ″ at the same time
(However, 0 ≦ k ″ ≦ k, 0 ≦ l ″ ≦ l)
These are the same as described above. In this case, the memory
Example of control of chip enable given to element
It is shown in Figure 14. k '× l', k "xl" block address
Where (Y, X) and (Y ', X') are
n, m and p, q are obtained. These n, m and p, q are selector data.
Input to the data input. Further, the selector selection control signal and
The memory access read / write signal R / W
Select and output n and m when reading, and p and q when writing
Select output. Similarly, block sizes k ', l' and k ", l" are also selected.
And the R / W signal is input as the selection control signal.
Have been. During reading, k 'and l' are selected and output, and
In this case, k ″, l ″ is selectively output. By the way,
The memory elements to be read are n, m, k ', l' on the read side,
Or uniquely determined if k ", l", p, q on the light side are determined
It is clear that these data output from the selector
Input to the lookup table, and
Controls which memory elements are accessed
Output signal. By the way, the images before and after processing by the processor unit 2
The image memory 1 is another memory, and its memory configuration is
In the case of k × l and K × L, respectively, as shown in FIG.
It is easy to think that a look-up table should be used.
I can understand. In this case, the look-up table 151 and the look-up
The up table 152 is a table having different contents. There is no problem even if k = K and l = L. Before
With the configuration described above, the memory element to be accessed is
Not all k × l memory elements
It is possible to partially mask. And k × l
The configuration of the moly element is the largest required k × l
Just set it to Next, how to access the memory element
Whether to process all image data corresponding to the entire screen,
Explains how to scan all memory data
I do. For example, the end point of an adjacent k × l block to be accessed
u position address, that is, from the end in the vertical direction, starting from 0
The number when counting is Y, and from the end in the horizontal direction from 0
When Y and X are determined when the number counted in order is X
The method of accessing the memory has already been described. So
Scans X and Y in any order and processes all images.
An example will be described. (First example) An image for accessing a k × l memory element
The position addresses Y and X of the image data are each an integral multiple of k and l
In the method of scanning by increasing or decreasing, for example, first, Y, X
It is set to 0, and X is sequentially increased by l. To the end point in the horizontal direction
After increasing X, set X to 0 next and increase Y by k
Then X is increased by 1 again. This is a sequential
The entire screen or a part of the screen is repeatedly scanned. Temporary
This is referred to as a first sequential scan method. (Second example) Also, increase and decrease of XY should not be performed sequentially as described above.
Then, the continuous k × l block of the whole image
Access the locks intermittently, and
If X and Y at the time of displacement are integer multiples of k and l,
Is referred to as a first random scan method. (Third example) An image for accessing a k × l memory element
Increase / decrease the image data position addresses Y and X by integers, respectively.
For example, first set Y and X to 0.
And X is sequentially increased by one. X to end point in horizontal direction
After increasing, then reset X to 0 again and increase Y by 1.
And then increase X by one. This is Sequencer
Scan the entire screen or a part of the screen repeatedly.
This is temporarily named the second sequential scan method.
You. In this case, the same memory data is accessed many times.
You. (Fourth example) In addition, increase and decrease of X and Y are performed sequentially as described above.
No, there is a block of k × l here and there on the whole image.
And jump to all Y, X
You. Or X, Y of all continuous parts of the entire screen
Run about. When it is random, this is
It is tentatively named Nandskyan method. (Fifth example) In a memory configuration having k × l memory elements,
And the memory block to access is k '× l'
And (1 ≦ k ′ ≦ k, 1 ≦ l ′ ≦ l) location addresses Y and X
increase or decrease by an integer multiple of k ', l'
The first sequence is a method that scans the entire screen repeatedly.
The blockwise sea method is distinguished from the
It is named the Känshärskiyan method. (Sixth example) In addition, increase and decrease of X and Y are sequentially determined as in (Fifth example).
Don't do it all over the image full screen
k '× l' blocks are accessed discretely and their Y,
If X is a displacement that is an integral multiple of k '× l',
Is called a blockwise random scan method. (Seventh Example) The seventh example relates to the memory configuration of k × l of memory elements.
That scans the sequence, such as any
Scan by changing X and Y every number d 'and f'
Is simply referred to as a sequential scan method. 4 (Eighth example) (Seventh example)
Example), note all combinations of X and Y
If no re-access, simply random scan
Let's call it an expression. As described above, various scanning methods are conceivable.
Apart from this, the memory access on the read side is
Access to the memory on the read side.
Scan method and write-side memory access scan method
Not necessarily. In addition, this scanning method uses a write method if the read side is determined.
X 'and Y' to be accessed by the processor unit 2
Determined by the processing content. Also, the scanning method on the light side first
You may decide. In this case, the scan on the lead side is in process.
Determined by volume. In addition, a blocker to be accessed on the read side and the write side
If the k ', l' may be different, the memory element
The size of the configuration k × l may be different. In an embodiment of the present invention to be described later, a processor
The processing performed in nit 2 is image compression.
Memory elements that constitute the image memory on the write and write sides
The numbers k × l and K × L of the elements are not limited to these.
No. Also, access is made within the memory on the read side and the write side.
For pixel block sizes k '× l' and K '× l'
It is not limited to the examples described below. Where 1 ≦ k ′ ≦
k, 1 ≦ l ′ ≦ l, 1 ≦ K ′ ≦ K, 1 ≦ L ′ ≦ l. For memory access scan in the embodiment described later
If it is supplementary explanation, it is limited to read side and write side
The pixel size to be accessed for each
Each image if it is equal to the size of the memory element
Scan by image memory in first sequential scan mode
What can be done can be easily inferred from the above (first example). Also,
Each image memory is stored in the image memory on the card side and the light side.
Smaller than the size of the memory elements that make up the memory
When accessing a pixel size that is not
Example) blockwise sequential scan method
It goes without saying that you can scan. As described above, a rectangular region m pixels ×
At the same time, image data in the image memory
Access and block the rectangular area in the original image memory.
Is m × n less processor elements
Image data to a processor unit consisting of
After capturing at the same time, each processor element
While communicating information such as image data with each other,
The compression processing of the input image data
And block the result into a rectangular area on the input original image memory.
A rectangle on the output side image memory smaller than
The original image data on the input side
The process of compressing is described. I'll keep it simple in the description
The block size of the rectangular area of the input image memory
M = n = 4, a processor element which is an arithmetic element
Is 2 blocks of the rectangular area of the image memory on the output side.
Size 1 × 1 = 1. FIG. 18 shows an input image corresponding to the original image memory 260 on the input side.
The raw block 261 and each pixel 261a,
The unit 262 and its components, the processor
Element 263a, 263b and output compressed data
The output pixel 264a for the output side image memory 264
FIG. The control signal from the control unit 265 is
Input to the Rosetta Unit 262 and the original image memory 260 on the input side.
16 pixels in the input source image memory 260
Access the image data block 261 at the same time,
Each processor in processor unit 262
The necessary image data is taken into the elements 263a and 263b.
Processor Unit 262 is based on 16 pixel image data
The representative density information 271 and the detailed information 272 as shown in FIG.
The corresponding position in the output image memory 264 on the output side.
Output compressed image data as output pixel 264a
You. Here, the processing unit 262 in the processor unit 262
Two processor elements 263a and 263b, one of which is 16
Dedicated calculation of representative density information 271 of pixel image data
Processor element 263a and the other
Perform based on image information such as fixed thresholds that match image characteristics.
Calculates detailed information 272
Element 263b. Raw image data input above
1 is an outline of an apparatus for compressing a file and a processing flow. Less than
Below, details of each processor element 263a, 263b
A detailed process will be described. A processor / element that exclusively calculates the representative density information 271
The element 263a converts the image data of 16 pixels as shown in FIG.
It consists of a buffer 281 for temporary storage and an arithmetic
Calculate the average density value of the raw image data and calculate this value as the representative density
The information is output to the image memory 264 on the output side. on the other hand,
Processor element 2 dedicated to detailed information 272
63b also has a buffer 281 for 16 pixels as shown in Fig. 20
It has the structure of the operation unit 282, and the characteristics of the input original image
According to the equipment not shown
Block obtained by binarizing the gradation information of 16 pixels with
Pattern information in the block, thresholds and each image in the block
Detailed information consisting of distributed information etc. obtained from raw image data
Information 272 and the representative density information 271 in the image memory 264 on the output side.
Output in the beginning. At this time, the two processor elements 263a and 263b
Can operate in parallel and perform high-speed compression processing
Can be. The compression processing described above requires the input side image memory to store 4 × 4 pixels.
Access to the sequential in memory block units
The last 4x4 memory block of the original image memory
By repeating until the processing of the
Image can be compressed. In the description, the detailed information in the compressed data is calculated.
Use a fixed threshold that is predetermined
However, this value is the value of the other processor element 263a.
It is easy to use the average density value output to
Can be inferred. In addition, the processing unit
Number of processor elements in the unit 263 is 1
It is easy to guess what is good. As described above, according to the present embodiment, the input original image
The raw image data is stored in an m × n (eg, 4 × 4) memory block.
The screen on the input side is used to access the sequential
Each pixel in the image memory is not accessed multiple times,
In addition, image data of m × n pixels can be simultaneously accessed.
Image data can be transferred at high speed.
Wear. Also, the image data is encoded in block units of m × n pixels.
The size of the memory block on the input side
n, one memory access makes one code
Since the encryption process can be performed, the process can be performed at high speed and the device
The configuration can be simplified. Furthermore, the operation unit
Number of processor elements in a processor unit
Is smaller than the number of pixels m × n in the memory block on the input side.
Number m '× n' and separate for each processor element
Reduce processing unit cost by performing various processes
And improve processing speed by parallel processing.
Can be. Next, another embodiment will be described. Image data corresponding to the rectangular area m pixels x n pixels on the original image
Access the image data on the memory at the same time,
In response, one processor element (operator)
Mxn processor elements corresponding to
Image data into a processor unit
After that, each processor element
The process of applying the compression process and outputting the result to the image memory
explain. In the description, m = n = 4 for simplicity
You. FIG. 21 shows input pixel blocks 291 and 291 corresponding to the original image 290.
And each pixel 291a, a processor unit 292 which is an arithmetic unit
And its component processor element 292a;
The relationship between the output image data 293a in the output image memory 293 is shown.
FIG. According to the control signal from control unit 294 in the figure
Therefore, the corresponding 16 pixels in the original image memory 290 on the input side are
Simultaneous access to image data 291
Each processor element 292 in unit 292
Import image data into a. Processor Unit 292
16 pixels as shown in Fig. 19 from the 16 pixel image data 291
Calculate the representative density information 271 and detailed information 272 of the
Output to the image memory 293. Here, each processor in the processor unit 292 is
Element 292a corresponds to each 4 × 4 pixel,
It is composed of 4 × 4 = 16 pieces in a square lattice. This is the picture
4 is an outline of image data compression processing. Below,
A detailed process of the process element 292a will be described.
You. Each processor and element in processor unit 292
Number 292a in the row and column directions, respectively.
As shown in Figs. 22 and 23, each processor
Distinguish element 292a. First, representative density information 271 is created from 16 pixel image data.
The process will be described. The 16 processors and processors shown in FIG.
The image data corresponding to each of the elements 292a
Shall be Each processor element (1,1),
… (4,4) calculates 1/16 of the density data of each pixel in parallel
And calculate the result as a processor element (1,1).
Add all the values and find the average value of the density information of 16 pixels.
Of the representative density information 271 in the compressed data shown in FIG.
Output to the output image memory as a value. Next, detailed information 272 in the compressed data shown in FIG. 19 is obtained.
The following describes the process of setting. Each processor and element shown in Fig. 23
The comments are the same as those shown in FIG. First, the 16 processor elements 292a have
The gradation information of each pixel is stored in the processor
Binarization based on the average density information output by element (1,1)
Pattern information of each pixel obtained by
High-speed distributed information obtained from each pixel data in the block
To find the 4x4 processor element in the 23rd
It is divided into 4 blocks of 2 × 2 shown by the solid line in the figure.
Calculates in parallel within 4 blocks of × 2 and intermediates the result.
The result is four central processor elements (2,
2), (2,3), (3,2), and (3,3)
Perform the above operation in a 2x2 block and save the final result
Determine the value of the Rosetsusa element (2,2)
Output to the output image memory as detailed information 272 of 16 pixels.
You. The above processing is performed by inputting the original image memory into 4 × 4 blocks.
Access to the sequence in units of
The compression processing of the last 4 × 4 block of the image memory is completed.
The compressed data for one page of the original image
Data can be obtained. As described above, according to the present embodiment, the input original image
The raw image data is stored in an m × n (eg, 4 × 4) memory block.
To access the sequential for each check, the input side
Each pixel in the image memory cannot be accessed multiple times.
And simultaneously access m × n pixel image data
Image data can be transferred at high speed.
it can. Also, the image data is encoded in block units of m × n pixels.
The size of the memory block on the input side
n, one memory access makes one code
Since the encryption process can be performed, the process can be performed at high speed and the device
The configuration can be simplified. Furthermore, the input in the processor unit
M × n processes equal to the size of the memory block on the side
Tusa elements can be processed in parallel
Therefore, the processing speed of the arithmetic unit can be increased. Another embodiment will be described. For a rectangular area m × n pixels on the input-side original image memory
Access multiple image data at the same time,
Image data is imported to a certain processor element and
After performing image data compression processing,
Smaller than m '× n'(m> m ', n>n')
Output to the corresponding position on the output side image memory. Also
Conversely, the block size of the image memory on the input side
Access m ′ × n ′ pixels at the same time,
After importing image data into the nit and performing decompression processing,
Size m × n (m>) larger than the block size at the time of input
m ', n>n') Image data of all pixels is output
Output to memory at the same time. Memory block size at this time
Mxn, m'xn 'are fixed, and compression and decompression
M × n on the input side and m ′ ×
n ', or conversely m' × n 'on the input side and m ×
n (where m>m'n> n ') is switched to perform the processing.
Things. Hereinafter, the process of the compression and decompression processing will be described.
However, for simplicity, let m = n = 4 and m ′ = n = 1,
The number of processor elements in a processor unit is two.
I do. First, at the time of compression, as in the case of FIG.
4 is input to the processor unit 241.
The input side block size is 4 × 4, the output side size
Is determined to be 1, and the corresponding
Access image data for 16 pixels
Each processor element in the seta unit 241
The necessary image data is taken into the comment 241a. Processor
Unit 241 is shown in Fig. 19 from 16 pixel image data.
Calculate and output representative density information 271 and detailed information 272
The image is compressed to the corresponding position in the output image memory 242.
Output image data. On the other hand, the processing when decompressing the compressed encoded data
explain. FIG. 24 shows the encoded data 240a of the input side image memory 240.
And the processor element 241a
The output to the unit 241 and the playback image memory 242 on the output side
FIG. 14 is a diagram showing the relationship between the output pixel block 243 and the output pixel 243a.
is there. A control signal from the control unit 244 shown in FIG.
Input to the processor unit 241 and block on the input side
The size is determined to be 1 and the output block size is determined to be 4x4.
From the image memory on the input side as shown in Fig. 19.
One piece of data is input to the processor unit 241.
Processor element 241a performs each processing,
The reproduced 16-pixel image data is converted to image data 24 on the output side.
2 are simultaneously output to the corresponding 4 × 4 rectangular area. This
Here, each processor in the processor unit 241 which is the arithmetic unit
The set element 241a is the reverse of the compression process described above.
Processing, eg, representative density information 271 in coded data and details
The density of the 16-pixel image data is
To obtain 16-pixel image data.
Play at the same time. At this time, multiple processor elements
241a can operate in parallel, making decompression processing faster
It can be carried out. The above decompression processing is sequentially performed on the encoded data on the input side.
Access to the image data on the output side
Also output sequentially in 4 × 4 block units
Perform the operation until there is no more encoded data on the input side.
Therefore, the encoded data is reproduced from one page of image data.
Image data can be created. In the description, it is assumed that detailed information in the compressed data is calculated.
Use a fixed threshold that is predetermined
However, this value is output by the other processor element.
It is easy to guess that the average concentration value can be used.
be able to. In addition, a processor unit that is an arithmetic unit
That the number of processor elements in one can be one
Can also be easily inferred. Input or output the number of processor elements
Side block size is larger, 4 in the case of this embodiment.
It is also easy to arrange × 4 in a square lattice
Can be inferred. In this embodiment, the block
The size is 4x4 and 1, but these sizes are
But good things can easily be inferred. As described above, according to the present embodiment, the input original image
Raw data or reproduced image data on the output side
(For example, 4 × 4) memory block
In order to access, each pixel in the input side image memory is
Multiple circuits are not accessed, and m × n pixels
Since image data can be accessed simultaneously,
Image data can be transferred quickly. Also, set the block size of the image memory on the input and output sides.
Switch to (4 × 4 and 1) (1 and 4 × 4)
Therefore, do not use separate compressor and decompressor.
And only one device is required, and
It became possible to make it small. In addition, make the input block sizes different.
To read unnecessary image data,
The need for masking to avoid rewriting is eliminated. In addition, each processor element in the processor unit
Can be processed in parallel.
Can be raised. Second Embodiment k × l for Accessing k × l Data Simultaneously
Of image data allocation to memory elements
Example 2 will be described. Figure 16 is on the top of the image 1 screen
This is a diagram showing the state in which the
It is divided into l equal directions and k equal parts in the vertical direction. At this time
In order to explain the area divided into k × l, (0,
0), (0,1), ... (0, l), ..., (k, l)
As shown in Fig. 17, each area has its own memo.
Assign to the element. The assignment method is shown in Fig. 16.
The hatched portion shown by the broken line indicates the 0 of each memory element.
Addresses and then store the next image data in each memory
・ Assigned to the first address of the element, and
When all lines have been assigned, repeat the second line.
All the image data is allocated from left to right
wear. Then, all k × l memory elements
In contrast, the row address generator 4 shown in FIG.
And the address given by the column address generator 5
Are all the same, as indicated by the shaded area in FIG.
You can access discrete image data at once
You. With this configuration, you can specify a certain address
To read the image memory 1 and the processor unit 2
K × l memory elements
Data without changing the address when writing to
Data can be written. For example, as shown in FIG.
Thus, when the area is composed of K × L pixel data,
In this case, one part of one screen of the image is horizontally an integral multiple of L,
Performs processing such as displacement, movement, and transfer in the vertical direction that is an integral multiple of K.
In this case, the read address and the write address are
I don't know. For this purpose, the row address generator 4,
Address control related to the RAM address generator 5 etc.
The load is extremely reduced. This transfer and transfer processing is performed by the processor unit 2.
Be processed. Figure 16 shows the processor unit 2
As shown by the hatched dashed lines, k × l image data,
Image data covering the entire screen is input, and the data
Each one has horizontal and vertical displacements of integer multiples of L and K
K × l units in processor unit 2
Data conversion and transfer
For all addresses in sequence from 0
What is necessary is just to perform a process. As a result, processing on the entire screen
it can. In this embodiment, k × l memory configurations are changed to, for example, 1 × l, k
× 1 or other configuration, one horizontal line in one image, or
By assigning one vertical line to each memory unit
Processing in processor unit 2 is
Operations such as histogram calculation and one-dimensional Fourier transform
It can be inferred that it can be applied to seed image processing. Also, multiple pixels
At the time of simultaneous access, the data in one screen
Restrict which address of the re-element is assigned
Not. [Effects of the Invention] According to the present invention, the compression of an image is improved in units of divided areas.
It is possible to provide an image processing apparatus that performs parallel processing at high speed. Sand
That is, a plurality of memory elements and a plurality of processors
Each element corresponds to the divided area, and multiple
Processor element between the processor elements of the
Transfer the image data calculated in the
Because image data is processed, image compression can be performed at high speed.
Column processing is possible. In particular, images between processor elements
Special configuration for such transfer as it transfers data
And a simple configuration can be achieved without the need for

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the configuration of an image processing apparatus according to the present embodiment, FIG. 2 is a diagram in which one image corresponds to the address of a memory element, and FIG. FIG. 4 is a diagram showing a memory and an address generator provided thereto, FIG. 5 is a diagram showing a portion of an image, FIG. 6 is a diagram showing memory allocation of a portion of an image, FIG. 7 is a diagram showing a memory address control circuit, FIG. 8 is a block diagram of pixel data control, and FIGS. 9 (a) and 9 (b) are diagrams showing the configuration of another image processing apparatus of the present embodiment. FIG. 10 is a diagram showing one image screen, FIG. 11 is a diagram showing k × l memory elements, FIG. 12 and FIG. 13 are diagrams showing one memory element, FIG. FIG. 15 shows a control circuit for memory element access, and FIG. 16 shows one image screen. FIG. 17, FIG. 17 is a diagram showing k × l memory elements, FIG. 18 is a diagram showing the relationship between an input side image memory, a processor unit and an output side image memory in this embodiment, FIG. Is a format diagram of the compressed image data used in the present embodiment, FIG. 20 is a functional diagram of each processor element in the present embodiment, and FIG. 21 is a diagram showing the input side image memory and the processor unit in the present embodiment. FIG. 22 and FIG. 23 are schematic diagrams of the operation of each processor element in the present embodiment, and FIG. 24 is an input image memory and a processor during decompression processing in the present embodiment. FIG. 3 is a diagram showing the relationship between a processor unit and an output image memory. In the figure, 1 ... image memory, 1a, 1b ... memory element, 2 ... processor unit, 2a ... processor
Element 3, peripheral part, 4 ... row address generator, 5 ... column address generator, 91 ...
… Input side image memory, 92 …… Processor unit, 93
…… Output image memory, 94… Control circuit, 95… Input device, 96… Output device, 240,260,290 …… Input side image memory, 261,291 …… Input image block, 240a, 261a, 291a…
… Input pixels, 241,262,292 …… Processor unit, 2
41a, 263a, 263b, 292a …… Processor element, 242,
264, 293... Output image memory, 243... Output image block, 243a, 264a, 293a... Output pixels, 244, 265, 294.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Naoto Kawamura               3-30-2 Shimomaruko, Ota-ku, Tokyo               Inside Canon Inc.                (56) References JP-A-62-13165 (JP, A)                 JP-A-60-185987 (JP, A)                 JP-A-61-107475 (JP, A)                 JP-A-61-16369 (JP, A)

Claims (1)

(57) [Claims] What is claimed is: 1. An image processing apparatus for compressing an image in units of a region divided into a predetermined size, comprising: a plurality of memory elements corresponding to the number of pixels of the region; an image memory for storing image data; A plurality of processor elements corresponding to the plurality of memory elements, and image data read out in parallel from the plurality of memory elements are compressed by the plurality of processor elements in the processor element so as to be compressed in units of the area. An image processing apparatus comprising: a processor that transfers image data that has been transferred and performs arithmetic processing on the transferred image data.