DE3845004C2 - High speed parallel image processing appts. - Google Patents

Abstract

The image memory contains independently addressable storage elements. Image element data of an image divided into regions have associated addresses corresp. to the regions. A processor unit consisting of processor elements corresp. to the storage elements simultaneously processes the stored data for a number of image elements. Each processor element has a density convertor which converts the density of the image elements enabling the processor unit to perform density conversion of the image. It also contains a colour distinguishing device and a colour converter. Image element data are converted to a defined colour when the distinguishing device detects a preselected colour.

Description

The invention relates to an image processing device, where with a large number of processors at the same time Image processing is performed.

As a result, parallel processing is required processing using a finite number of Processors. In US 4,786,820 there is one Methods for such parallel processing are provided suggest that the division of the image data into a Large number of blocks from several image data each post and processing the image data into each Block through one of a variety of zen tral units. The arrangement is so that each central unit corresponds to the image data of the blocks and the image data of the neighboring ones Blocks and that the central processing unit the image data of the corresponding block processed.

However, the proposed system leaves a lot of play room for improvement in terms of performance construction and open.

J. L. Potter: "Image Processing an the Massively Parallel Processor ", Computer, January 1983, pp. 62- 67, addresses the problem that arises when calculating Values at the edges of a processor array arise. This There is a problem with both serial and parallel Computers and is a function of memory size versus the total amount of data to be processed. If more data too save than the computer memory can hold according to the document this problem by overlapping the Data on the next buffer resolved so that all values can be calculated. The optional Accessibility of the level memory to the programmer Selection of any degree of overlap. The However, publication does not describe how a variety from processor elements to pixel data in each divided area accesses two-dimensionally overlapping to picture elements in question in a border section to process. This is also the A. Rosenfeld publications: "Parallel Image Processing Using Cellular Arrays", Computer, January 1983, pp. 14-20, and T. Kushner, A. Y. Wu, A. Rosenfeld: "Image Processing on ZMOB", IEEE Trans. On Computers, Volume C- 31, No. 10, October 1982, pp. 943-951.

The invention has for its object one by one Variety of processor devices performed To improve image processing.

This object is achieved by the Image processing device according to claim 1 solved.  

Advantageous further developments are in the subclaims specified.

The invention is based on execution examples with reference to the drawing he refines, in their figures the same reference numeral Chen denote the same or similar parts.

Fig. 1 is a block diagram showing a Bildverarbei processing device according to an embodiment.

FIG. 2 is a diagram illustrating the relationship between a frame and addresses of memory elements.

Fig. 3 is a diagram showing a memory with 4 × 4 memory elements as a whole.

Fig. 4 shows a memory with assigned address generators.

Fig. 5 shows a part of an image.

Fig. 6 shows the assignment of a memory for a part of an image.

Fig. 7 is a block diagram of a memory address control circuit.

Fig. 8 is a block diagram of a pixel data control circuit.

Fig. 9 (a) and (b) are block diagrams showing the construction of the image processing device according to other examples approximately exporting.

Fig. 10 is an illustration of a frame.

Fig. 11 shows k × ℓ memory elements.

FIGS. 12 and 13 show a single spoke clean unit.

FIGS. 14 and 15 are block diagrams of memory element fetch control circuits.

Fig. 16 shows a still image.

Fig. 17 shows k × ℓ memory elements.

Fig. 18 is a block diagram of an address conversion circuit.

Fig. 19 (a) is a block diagram illustrating the concept of designing a processor element.

Fig. 19 (b) is a block diagram of a processor element in which a logic arithmetic unit of Fig. 19 (a) is formed by a microprocessor.

Fig. 20 is a graph for Erläute tion of a density conversion.

Fig. 21 illustrates a masking operation.

Fig. 22 is a flow chart of a method for the density conversion.

Fig. 23 is a flowchart of a method for color conversion.

Fig. 24 is a flow chart of a method for masking.

Fig. 25 shows an image data arrangement before rotation.

Fig. 26 shows a state that results when rotation is performed in picture element block units.

Fig. 27 shows a state which arises when the rotation in picture element units has been carried out within the blocks.

Fig. 28 shows the arrangement of picture elements in blocks before the rotation and after the rotation in picture element block units.

Fig. 29 shows the arrangement of the picture elements in the blocks after the rotation within the picture element blocks.

Fig. 30 is a block diagram of a circuit for performing a rotation.

Fig. 31 shows a block data selection circuit.

Fig. 32 shows an example of a Adressenum setting circuit for translating addresses within blocks.

Fig. 33 shows a circuit for generating addresses within blocks prior to implementation.

Fig. 34 is a block diagram of another circuit for performing rotation.

Fig. 35 shows area divisions and scans with respect to an image.

Fig. 36 shows partial areas that are not subjected to spatial frequency filtering.

Fig. 37 is a block diagram of Bildverar beitungseinrichtung for spatial frequency filtering.

Fig. 38 (a) illustrates the enlargement and scanning of areas formed by dividing a frame.

Fig. 38 (b) shows a part of an area.

Fig. 39 is a block diagram showing another arrangement of an image processing device for spatial frequency filtering.

Fig. 40 shows a data control circuit.

Fig. 41 is a block diagram of a processor element.

Fig. 42, the relationships between the format of an input picture element region shows an input-side memory, the format of an output pixel region of an output-side memory and the matrix format of a processor unit.

Fig. 43, the data transfer illustrated Zvi rule processor elements of a processor unit.

Fig. 44 shows a coefficient matrix for a spatial frequency filtering means of the processor unit.

Fig. 45 is a block diagram of a circuit for spatial frequency filtering.

Fig. 46 is a block diagram illustrating the concept for enlargement.

Fig. 47 is a block diagram of an address generator portion of a processor unit.

Fig. 48 is a block diagram illustrating the concept for the internal structure of the processor unit.

Fig. 49 shows schematically a data select circuit in a respective processor element.

Fig. 50 is a block diagram of the data selection circuit.

Fig. 51 is a block diagram showing details of a main scan selector and a sub- scan selector shown in Fig. 50.

Fig. 52 is a schematic diagram of a circuit for two-dimensional linear interpolation.

Fig. 53 illustrates the relationship between formats of input / output picture element areas and the matrix format of a processor unit.

Fig. 54 shows the relationship between an input-side frame memory, a processor unit and an output-side frame memory play at a Ausführungsbei.

Fig. 55 shows the format of image reduction data used in the embodiment.

Fig. 56 is a representation of the function of each processor element in the embodiment.

Fig. 57 shows the relationship between an input-side frame memory, a processor unit and an output-side image memory in another example guidance from the image processing device.

Fig. 58 and 59 the function illustrate schematically example of each processor element in the execution.

Fig. 60, the relationship between an input image memory, a processor unit and an off shows input image memory while executing a magnification to the image processing device according to a Ausführungsbei game.

Fig. 61 shows the relationships between Bildspei manuals and processor units in one embodiment, the image processing device.

Fig. 62 shows details of a processor unit in the embodiment.

Fig. 63 is a flowchart of a color control in an embodiment of the image processing device.

Fig. 64 illustrates a data exchange in a color correction.

Fig. 65 illustrates an image offset.

FIG. 66 shows the structure of a processor unit 312 according to FIG. 46 and an area called up in an input image memory 316 by means of the processor unit 312 .

FIG. 67 illustrates the relationships between respective processor elements PE according to FIG. 65 and an output image memory 317 .

Fig. 68 shows the structure of respective digital integrators according to Fig. 66.

A first embodiment of the image processing device will now be described with reference to FIG. 1.

The image processing device according to this embodiment has an image memory 1 for storing the image of a page, a processor unit 2 and a peripheral part 3 such as an input / output unit. Veran Fig. 1, only the arrangement illustrates these basic components and shows that the processor unit 2 is connected to the image memory 1. According to Fig. 1 n x m image data item at any points in the image memory 1 are sent to the processor unit 2 transmitted, the sorelementen of an n × m matrix of Prozes 2 is formed a, in which the data are processed at high speed, according to which they are returned to the image memory 1 . The n × m processor elements 2 a in the matrix execute the processing simultaneously.

The overall equipment is thus one for so-called parallel processing. The Fig. 9 (a) and (b) show other possible arrangements. According to Fig. 9 (a), image data are supplied from an input image memory 91 to a processor unit 92 which contains a plurality of processor elements in which a plurality of image elements are subjected to the prescribed parallel processing, after which the resulting image data is converted into an output image memory 93 can be stored. This is done under control by a control circuit 94 which is connected to the image memories 91 and 93 and to the processor unit 92 . According to FIG. 9 (b), the image memory 91 or 93 is integral with the processor 92, an input unit 95 and an output unit 96 via a common manifold connected.

The image memory 1 will now be described in detail.

For the sake of simplicity it is assumed that an image has the format 1024 × 1024 picture elements and that the image memory stores data in the form of eight bits per picture element. A change in the image format is accomplished only by changing the architecture of the exemplary embodiment. Furthermore, it is assumed that the processor unit 2 is formed from 4 × 4, that is to say a total of 16 processor elements 2 a.

Fig. 2 illustrates the configuration of the image memory 1. Assuming that, according to the illustration, an image is composed of 1024 × 1024 picture elements and the picture is divided into units of 4 × 4 picture elements, the picture is divided into 256 × 256 blocks, that is a total of 64k (= 65536) blocks. This can be illustrated in FIG. 3, in which 64k units of 4 × 4 picture elements are assumed, each of which has the length of 8 bits. With regard to the address areas of the memory, addressing is therefore carried out in three dimensions with 4 × 4 × 64k. If 64k picture elements for a picture element location from the 4 × 4 matrix of the picture elements are assigned to a single memory module, as shown in FIG. 3, a memory module is required in which each address has a depth of 8 bits for the 64k address locations. This would require a memory module with a capacity of 512 kBit (= 64 kByte). In the exemplary embodiment described, two dynamic read / write memories (DRAM), each for 256 kbit, are used in combination. That is, two dynamic 256 kBit memories are used for each 64k × 4 bit and used in the form 64k × 8 bit. These two memory modules are referred to as a memory element 1 a. In the following, a processor unit is referred to as "PU", a processor element as "PE" and a memory element as "ME".

The image memory 1 is composed of 16 picture elements 1 a corresponding to a matrix of 4 × 4 picture elements. Fig. 4 shows the arrangement of these 4 × 4 memory elements 1 a. For each memory element 1 a, its row address and its column address are determined, so that image data for the 64k address locations for a single image element from the 4 × 4 image elements can be entered into and output from each memory element. At each of the 4 × 4 memory elements 1 a, the addresses of a row address generator 4 and a column address generator 5 are created. It should be noted that a single address generator is sufficient if the memory elements 1 a are dynamic memories and the row and column addresses are created in time division multiplex. If this is the case, a switch control for the time-division interleaving of the row and column addresses is required. The row and column addresses each correspond to A and B for a block designated by (A1, B1) in a respective single image according to FIG. 2.

By applying the addresses from the respective address generators 4 and 5 can be written into the memory elements 1 a for the 4 × 4 picture elements or read from them. That is, 4 × 4 memory elements can be operated simultaneously by a single address determination. It is assumed that for this purpose data lines for eight bits lead away directly from each of the memory elements 1 a.

If data with the row address A (0 ≦ A ≦ 255) and the column address B (0 ≦ B ≦ 255) are retrieved from the image memory 1, the image data corresponding to the address (A, B) according to FIG × 4 picture elements, each of which is eight bits long.

Simultaneous access to a large number of picture elements will now be described in general terms.

Fig. 10 shows an image side. According to the illustration, the image data are subdivided into adjacent blocks each consisting of k × ℓ picture elements. As shown in Fig. 11, the k × ℓ picture elements in each block with k × ℓ memory elements 1 a are related or assigned to them. The blocks formed from these k × ℓ picture elements are marked with (0, 0), (0, 1), (0, 2), (0, 3),. , , numbered and correspond to the storage unit 1 from the k × ℓ. Memory elements 1 a according to FIG. 12. In FIG. 13, the memory unit 1 is shown in two dimensions. The storage format when the storage unit 1 is called up is block format units from k × ℓ. Picture elements. Therefore, when a block R is retrieved from k × auch picture elements in any position in memory unit 1, all k × ℓ memory elements 1 a are retrieved. In addition, an address is retrieved for each memory element 1 a. Accordingly, k × ℓ picture elements are picked out at the same time.

In this way, image data from k × ℓ adjacent image elements at any point in the image are retrieved and read, after which this image data is processed by means of the processor unit 2 . The image data processed by the processor unit 2 can be rewritten into a block H from k '× ℓ' image elements of the memory unit 1 by accessing any locations of the memory unit 1 . The following description is based on the assumption that k '= k and ℓ' = ℓ.

Access to a memory for only k '× ℓ' picture elements will now be explained in addition. If the processing carried out by the processor unit 2 is a spatial or spatial frequency filtering according to a calculation process using a target picture element and the picture elements surrounding it, the write-side block format k '× ℓ' is smaller than the read-side block format k × ℓ. In general, therefore, processing takes place in such a way that the write-side block format k '× ℓ' becomes 1 × 1. Even if the processing carried out by the processor unit 2 is not a spatial frequency filtering but an image reduction, the block format k '× ℓ' called up on the write side becomes smaller than the block format k × ℓ called up on the read side.

In general, with regard to the block format k '× klein' on the writing side, the values k 'and ℓ' are the smallest integers which satisfy the conditions k '≧ αk and ℓ'<βℓ, where α and β are the longitudinal reduction ratio and the transverse reduction ratio, respectively , If in the execution of the processing according to the above two examples the read memory and the write memory are identical or the same k × ℓ memory arrangement is used, the write side must be written in a format k '× ℓ' which is smaller than is the format k × ℓ of the storage unit 1 . In such a case, not all k × ℓ memory elements 1 a are accessed. Instead, the design must be made in such a way that the memory elements 1 a not required for the write operation are masked and not accessed. The masking of the memory elements not required for the write operation and the simultaneous access to only k '× ℓ' memory elements can be accomplished in a simple manner in that release signals only to the k '× ℓ' elements from the components of the k × ℓ memory elements 1 a and not to the remaining (k × ℓ) - (k '× ℓ') storage elements.

With regard to an embodiment in which the prescribed the picture elements can be called up at any point, will now be a case where the storage unit 4 × 4 arrangement has described, as well as a case in which the memory unit has k × ℓ arrangement. Furthermore, the building block Release control for the above masking described.

The exemplary embodiment for the case is first described ben that the block format k × ℓ is the format 4 × 4.

In FIG. 5 is a part of FIG. Magnified. 2 The processing will be described for a case that image data is read out from any 4x4 block S in the image memory 1 , the data is processed by the processor unit 2 , and the results are transferred to any 4x4 block T. , (According to FIG. 5, the block S can overlap several blocks shown in FIG. 2.) The 4 × 4 cells shown in FIGS. 5 and 6 delimit 4 × 4 or 16 storage elements 1 a. It is assumed that these 16 memory elements 1 a with Aa, Ab,. , ., Ba, Bb,. , ., Ca,. , , Dc, Dd are designated. If the 4 × 4 block S is read out first, (N, M) are applied as row and column address to the memory element Dd from the 16 memory elements 1 a. Furthermore, (N, M + 1) are applied to the memory elements Da, Db and Dc, (N + 1, M) to the memory elements Ad, Bd and Cd and (N + 1, M + 1) to the remaining memory elements. These addresses are generated by the row address generator 4 and the column address generator 5 . It is obvious that when the location of a corner point u of the 4 × 4 block S has been determined, the location addresses in the horizontal and vertical directions are divided by four and the row and column addresses for the storage elements Aa to Dd are clearly divided by residues n and m are determined. The local address u (Y, X) is assumed for the corner point u. The following then results:

Y = 4N + n (n = 0, 1, 2, 3)

X = 4M + m (m = 0, 1, 2, 3)

For example, an arrangement is conceivable in which the information M and N and the information m and n are entered in look-up tables and the addresses are output to the memory elements Aa to Dd by means of the address generators 4 and 5 . From the above description, it can be seen that the output value at this time is any of the values M, N, N + 1 or M + 1. Using this property, it is sufficient to enter n or m in a lookup table, to output "0" or "1" depending on the entered value, and to perform control to determine whether the address to be applied to the memory elements Aa to Dd N or M is to be ranked or not, as shown in FIG. 7. Here, the values n and N are used on the row address generator 4 and the values m and M on the column address generator 5 .

In this way, addresses from the address generators 4 and 5 are applied to the 4 × 4 matrix of the 16 memory elements 1 a via a look-up table 71 and adders 72 a to 72 p according to FIG. 7, so that 16 data items can be obtained simultaneously ,

These 16 data items are transferred after any processing in the processor unit 2 or without processing in the block T for 4 × 4 picture elements shown in FIG. 5. However, the image data read from the 16 memory elements Aa to Dd do not necessarily have to be transmitted to the same memory elements Aa to Dd. If the 4 x 4 pel memory block S of Fig. Is transferred in the 4 × 4 picture elements memory block T 5, which from the memory element Aa of the 4 × 4 picture elements memory block S read out data must be transferred to storage element Dc become.

It will now be described in which memory elements the memory cher elements Aa to Dd from the storage elements Aa to The 16 data items read are to be registered if Starting and corner points u and v of the 4 × 4 memory blocks S and T have any location addresses (Y, X) and (Y ', X').

If Y, X, Y 'and X' are expressed as follows:

Y = 4N + n (n = 0, 1, 2, 3)

X = 4M + m (m = 0, 1, 2, 3)

Y '= 4P + p (p = 0, 1, 2, 3)

X '= 4Q + q (q = 0, 1, 2, 3)

x and y result from:

p - n = 4y '+ y (y' = -1, 0 y = 0, 1, 2, 3) (1)

q - m = 4x '+ x (x' = -1, 0 x = 0, 1, 2, 3) (2)

First, row row A is made up of storage elements Aa, Ab, Ac and Ad with cyclical swapping x times after offset to the right. This results in a row A '. On in the same way row rows B, C and D are below  cyclic exchange shifted to the right, causing rows of lines labeled B ', C' and D 'result.

Next, the column rows (ABCD) 'from the rows rows A ', B', C 'and D' with cyclic reversal y- sometimes shifted down.

From Fig. 5, it is seen that n, m, p and q in each case the values of 3, 3, 2 and 1 have. Therefore, the following results from equations (1) and (2): y '= -1, y = 3, x' = -1, x = 2. As a result, the following matrix is achieved as described above:
If a double cyclic swap is made to the right, the result is:

A '= (Ac, Ad, Aa, Ab)
B '= (Bc, Bd, Ba, Bb)
C '= (Cc, Cd, Ca, Cb)
D '= (Dc, Dd, Da, Db)

If a cyclical downward swap is then carried out three times, the matrix results:

(Bc, Bd, Ba, Bb)
(Cc, Cd, Ca, Cb)
(Dc, Dd, Da, Db)
(Ac, Ad, Aa, Ab) (3)

The matrix ( 3 ) is now compared with the following basic or original matrix ( 4 ):

Aa, Ab, Ac, Ad
Ba, Bb, Bc, Bd
Ca, Cb, Cc, Cd
Da, Db, Dc, Dd (4)

The origin matrix ( 4 ) is simply formed by two-dimensionally arranging the data read from the memory elements Aa to Dd in the sequence from left to right and from top to bottom. The matrix ( 3 ) corresponds to a matrix which is achieved by arranging the data to be written into the memory elements Aa to Dd in a two-dimensional manner in the sequence. In detail, the matrix ( 3 ) shows as an example that the data read from the memory element Aa are written into the fourth row and third column. The origin matrix ( 4 ) shows that the fourth row, third column is Dc. As a result, it can be seen that the data read out from the storage element Aa is to be written into the storage element Dc.

Since it is easy to see that the data read from the storage element Aa in FIG. 5 is to be written into the location Dc, the shift from Aa to the location Dc is equivalent to a transition from the location address u to the location address se v. Furthermore, since the memory elements 1 a have the 4 × 4 arrangement, the residues obtained by dividing the location addresses in the horizontal and vertical directions by "4" can be regarded as offsets x and y of the memory elements. For example, if the offsets of the location addresses sen u and v are multiples of "4", the offsets x and y become "0" so that the data read from a particular memory element is written into the same memory element after processing.

The execution of the above processing by circuit equipment will now be briefly described. The Fig. 8, according to the can be processed simultaneously from the SpeI chereinheit 1 with the 4 x 4 matrix of 16 memory elements 1 a read-out data by means of the processor unit 2 is a block diagram. These data d by cyclic permutation in x-displacement circulation exchangers 81 a to 81 x-times shifted to four elements simultaneously. The results are then offset y-times by means of a y-displacement circulation exchanger 82 by cyclic exchange and are written into the storage elements Aa to Ad, Ba to Bd, Ca to Cd and Da to Dd, respectively.

The data entered into the y-displacement circulation exchanger (rotator) 82 is the data for four elements, so that the y-displacement circulation exchanger 82 can of course be formed from four circulation exchangers which are exactly the same as the x-displacement Circulation exchangers 81 a to 81 d are. Of course, the circulation exchangers must have the same bit number depth as the storage data depth and the number of circulation exchangers used must be equal to the depth of the storage data. Slider registers or bubble accumulators can be used as circulation exchangers.

The above will now be considered in more general terms tet.

If a memory block has the format k × ℓ, the storage unit 1 receives a k × ℓ arrangement. In this case, if the memory block S from k × ℓ picture elements is processed at any point by means of the processor unit 2 and the results are transferred to the memory block T from k × ℓ picture elements at any point, the values n, m, p and are obtained q from the following equations:

Y = kN + n (n = 0, 1,..., K - 1)

X = ℓM + m (m = 0, 1,..., ℓ - 1) (N, M, P, Q = 1, 2, 3,...)

Y '= kP + p (p = 0, 1,..., K - 1)

X '= ℓQ + q (q = 0, 1,..., ℓ - 1) (10)

where the location address of the corner point of the block is S (Y, X) and the location address of the corner point of the block T is (Y ', X'). Inserting x and y in

p - n = Ky '+ y (y' = 1, 0, y = 0, 1, 2, 3,..., k - 1)

q - m = ℓx '+ x (x' = 1, 0, x = 0, 1, 2, 3,..., ℓ - 1) (11)

it is sufficient to use the x-displacement circulation exchangers 81 a to 81 d and the y-displacement circulation exchanger 82 of the type shown in FIG. 8 to carry out the processing. In this case, the x-displacement circulation exchanger has ℓ inputs and enables a displacement from 0 to ℓ - 1. The y-displacement circulation exchanger has k inputs and enables a displacement from 0 to k - 1. Since, in addition, the k input signals of the y-displacement circulation exchanger 82 each have ℓ elements, ℓ circulation exchangers are arranged for an input of k elements.

Next, the memory element access control for simultaneous access to the aforementioned k '× ℓ' block shown in Fig. 10 will be described.

Assume that the location address is a vertex i of the k '× ℓ' block (f, g). If the memory retrieved according to equation (10) is read, f, g is substituted in Y, X. If the memory is written according to the access according to equation (10), f, g is inserted in Y ', X'. If the result is put into equation (11) to obtain y, x, the circuit according to the embodiment shown in FIGS. 7 and 8 can be directly applied as a generalized arrangement for k × ℓ.

Here, only the building blocks for the k × ℓ 'storage elements  from the k × ℓ memory elements switched on or free given. If the local address (f, g) the corner point i of the k '× ℓ' block has been determined, are the values n, m or p, q by equation (10) clearly determined, so that access to the k '× ℓ' Spei elements is clearly determined.

In the case of a memory arrangement comprising k × ℓ memory elements as described so far, a case can be considered in which a k '× ℓ' block is read out simultaneously for reading and a k "× ℓ" block is simultaneously read out for writing ( where 0 ≦ k "≦ k and 0 ≦ ℓ" ≦ ℓ applies). The above description also applies in this case. An exemplary embodiment for the block release control to be carried out in this case on the memory elements is shown in FIG. 14.

If the location addresses of the corner points of the blocks k '× ℓ' and k "× ℓ" are (Y, X) and (Y ', X'), respectively, the values n, m and p, q from the equation (10) receive. These values n, m and p, q are applied to the data inputs of a selector 141 a. A memory access read / write signal R / W is applied to the selector as the dial control signal. Selectively, n and m are output for reading the data, and p and q are selectively output for writing the data.

In the same way, the block formats k × ℓ and k “× ℓ” are input into a selector 141 b, on which the signal R / W serves as a selection control signal. When the data is read, k 'and ℓ' are selectively output, while when the data is written, k "and ℓ" are selectively output. It is obvious that if the values n, m, k 'and ℓ' for reading and k ", ℓ", p and d have been defined for writing, the storage elements 1 a are uniquely determined for access are. Therefore, the data output from these selectors 141 a and 141 b are entered into a look-up table 142 , the signals for controlling the memory elements 1 a to be retrieved from the k × ℓ. Emits storage elements.

It can be seen that if the image memory for storage before processing by the processor unit 92 shown in FIG. 9 (a) and (b) is different from the image memory for storage after processing and the memory arrangements are each k × ℓ. or K × L, two look-up tables len 151 and 152 according to FIG. 15 must be used. In this case, look-up tables 151 and 152 have different contents.

There are no problems even if k = K and ℓ = L applies. If the arrangement described above is used the memory elements to be retrieved do not all have to be k × ℓ Be storage elements and it's a partial masking possible. It is sufficient if the arrangement of the k × ℓ Storage elements on the format k × ℓ is selected, which is the largest format required.

There is now access to the storage elements for the Processing of all image data of a full image is described. That is, the following description relates to a scan Query procedure for the retrieval of all stored data.

Referring to Figs. 5 and 6, access has already been described to a memory in the case that the local address of the start or vertex has already been established and the block of each other angren collapsing k × ℓ picture elements, namely, Y, X have been defined, where Y is the number obtained from the corner point in the successive count from 0 in the vertical direction, and X is the number obtained from the corner point in the successive count from 0 in the horizontal direction. The following examples will now be used to describe the sequence in which X and Y are to be queried for processing the full image.

example 1 First follow-up query procedure

This is a method in which location addresses X, Y of Bildda queried for the retrieval of k × ℓ memory elements that the values are an integer multiple of k or ℓ can be graded or graded. For example, who initially set the Y and X to "0" and X will be on subsequently increased in stages ℓ. If X up to the final value in the horizontal direction has been increased, X becomes "0" reset, Y increased by k and X increased in steps ℓ. This is repeated successively to the whole picture or to sample part of it. This procedure is called called the first follow-up query procedure.

Example 2 First random polling procedure

X and Y are not as described above successively increased or decreased. Instead be successive k × ℓ- here and there in the full screen Blocks accessed at random, which are currently values X and Y are dislocations, are the integer multiples of k and ℓ. This method is called the first random polling procedure.

Example 3 Second follow-up query procedure

In this method, the location addresses X, Y of the image da ten to access the k × ℓ storage elements by opening increment or increment by an integer. example Y and X are initially set to "0", after which X is successively increased in steps "1". If X up to the final value has been increased in the horizontal direction,  X is then reset to "0", Y is increased by "1" and X in Levels "1" increased. This is repeated in sequence, to scan all or part of a frame. This procedure is called the second follow-up query procedure records. In this case, the same storage data is used richly queried several times.

Example 4 Second random polling procedure

X and Y are not in the manner described above successively increased or decreased. Instead be here and there in the full screen k × ℓ blocks under Zu case distribution retrieved, what for all values X and Y leads. Alternatively, this processing can be done for the values X and Y of successive partial areas in the full image can be executed. If this happens randomly, the procedure will be the second random polling procedure records.

Example 5 Block-sequential scan method

If a block of memory to be retrieved is a k '× ℓ' block of memory in a memory arrangement with k × ℓ memory elements, place addresses Y, X (1 ≦ k '≦ k, 1 ≦ ℓ' ≦ ℓ) are integers Multiples of k 'and ℓ' increased or decreased, which match which is repeated to scan a frame. This procedure is used to distinguish the first fol interrogation procedure referred to as block follow-up interrogation procedure net.

Example 6 Block-random interrogation methods

X and Y are not as described above Example 5 successively increased or decreased. instead of here and there, successive ones lying in the full screen become  k '× ℓ' blocks retrieved at random, where X and Y are offsets, the integer multiples of k 'and ℓ'. This procedure is called block random interrogation procedure.

Example 7 Sequential query procedure

The query takes place sequentially with no connection to the Memory arrangement of the k × ℓ memory elements. For example the query is made by changing X, Y by each second arbitrarily chosen number d ', f'. This is simply called called sequential query.

Example 8 Random interrogation

If the memory query is not in the case of the random query according to Example 7 or 4 with respect to all combinations of X and Y is executed, the process is simply considered too referred to if necessary query.

According to the above, some query ver drive can be considered and it is the memory close grabbed the read-side memory and the write-side Memory possible, the polling method for reading do not necessarily save using the query method for the Write memory must match.

When the read-side query method has been determined, the values X 'and Y' on the write side are determined by the content of the processing carried out by the processor unit 2 . It is also possible to first determine the write-side query method, in which case the read-side query method is then determined by the content of the processing carried out by the processor unit 2 .

If the block formats k × ℓ that in the read memory and the blocks to be retrieved from the write memory memory formats also differ element arrangement k × ℓ.

The Fig. 19 (a) is a circuit diagram illustrating the concept of construction on a processor element PE. A logical and arithmetic arithmetic unit 12 , which receives data from one or more memory elements via a data input unit 11 and data from one or more processor elements via a receive buffer 13 , performs predetermined logical and arithmetic arithmetic processes according to this data and outputs the results via a Data output unit 15 to one or more storage elements. The logical and arithmetic arithmetic unit 12 also sends the data from the data input unit 11 or the results of the logical and arithmetic arithmetic operations via a transmission buffer or transmission buffer 14 to one or more processor units.

Fig. 19 (b) is a block diagram according to which the logic and arithmetic arithmetic unit 12 is formed by a microprocessor.

To an internal bus 10 , a central processing unit (CPU) 12 a, a read-only memory (ROM) 12 b for storing a control program and a read / write memory (RAM) 12 c are connected as auxiliary storage, which together form the logical and arithmetic computing unit 12 . Further, to the bus 10, the data input unit 11 , the data output unit 15 , the reception buffer 13 and the transmission buffer 14 are connected, which are shown in Fig. 19 (a).

The individual processor elements carry the same or each because it has its own processing and data exchange with the  other processor elements. Under the control according to one previously stored in the respective processor element Control program or under the control of an external Control circuit or a processing computer performs the whole process formed from this processor element group Soreinheit the predetermined processing in parallel.

Density conversion, color conversion and masking of image data

The density conversion, the color conversion and the like can by means of a system in which both reading the first follow-up query process on both sides and on the write side is applied. This will now be described in detail.

The color conversion is a processing in which if Image data contain certain color information, the color Formations in other predetermined color information be set.

When masking, as shown in FIGS. 21 (a) to 21 (c), only a certain part of the image data is output unchanged, while the rest of the image data is output as a background, such as a white background. Other data can also be output as a background, for example for "gray", "colorless" or the like. Fig. 21 (a) shows data indicating an area to be masked, Fig. 21 (b) shows an image to be masked, and Fig. 21 (c) shows the outputted results.

For the density conversion, for example, each processor element 2 a works in the processor unit 2 according to the flow diagram in FIG. 22. Here, an output value Vout (according to FIG. 20) corresponding to an input value Vin is determined by the following equation:

Vout = Vin ^2/64 (12)

The processor unit contains 16 processor elements, each of which corresponds to 4 × 4 picture elements with a length of 8 bits. In this processor unit 2 , the 4 × 4 data items corresponding to the address (A, B) according to FIG. 2 and 8 bits long are entered. The processor elements 2 a work in parallel and each deliver data. As a result, the 4 × 4 8-bit data items retrieved simultaneously are processed simultaneously in the processor unit 2 , after which the results are output simultaneously. In this way, high speed image processing is made possible.

The processor elements 2 a carry out processing such as conversion, color conversion and masking.

As described above, density conversion comprises changing an input value to a corresponding output value in accordance with a predetermined input density / output density correlation and outputting the output value. In this way, the contrast of an image can be increased and its brightness changed. FIG. 20 illustrates a density conversion, in which the computing operation according to equation (12) is executed.

For a color conversion, for example, each processor element 2 a works in the processor unit 2 according to the flow chart shown in FIG. 23. Here, a color information is expressed as a combination of, for example, red R, green G and blue B, wherein the above-mentioned image memory is provided for R, G and B, and each image memory for storing data with a length of 8 bits is designed. The individual identical processor elements are assigned to corresponding image memory cells for R, G and B. A combination of certain R, G and B values is stored in advance as a certain color, while likewise the color information after a change is pre-stored as a combination of certain R, G and B values. Of course, several specific colors can be stored.

For masking, for example, each processor element in the processor unit operates according to the flowchart shown in FIG. 24. Here, the masking relates to bit data in a memory which is formed by a bit directory memory whose bits correspond to the respective cells of the above-mentioned image memory. These data indicate whether or not they are within a mask. In this case, a single processor element is also assigned to the corresponding cells of the mask memory and the image memory.

Is if the design is made such that a data transfer between the processor elements 2a of beschrie surrounded processor unit 2 allows both a spatial, or spatial frequency filtering can be executed as a character recognition, compression, and decoding in the Prozes soreinheit. 2

A second exemplary embodiment will now be described in which image data for the simultaneous retrieval of k × ℓ data items are assigned to k × ℓ storage elements. Fig. 16 illustrates a state that occurs when the information for one frame is replaced by data. The information is divided horizontally into ℓ identical sections and vertically into k identical sections. To describe the k × ℓ areas resulting from this subdivision, they are denoted by (0, 0), (0, 1),. , , (0, ℓ),. , , (k, ℓ) denotes net, with each individual area being assigned an individual memory element 1 b as shown in FIG. 17. That is, the number of the memory elements 1 b is equal to the number of the divisions shown in FIG. 16. When the areas are assigned, each shaded partial area according to FIG. 16 is assigned to the address 0 of the corresponding memory element 1 b, while the adjacent image data are assigned to the address 1 of the corresponding memory element, etc., until all the data of a single line in a respective area are fully assigned. Then he assigns in the same way for the second line from left to right. This is repeated until all image data have been assigned. If all addresses are identical, which are applied by the row address generator 4 and the column address generator 5 according to FIG. 4 to all k × ℓ memory elements 1 b, any image data can be called up simultaneously, as is shown by the shaded partial areas in FIG. 16 ,

With this arrangement, it is possible to choose a specific address, to read the data at this address from the image memory 1 , to process the data in the processor unit 2 and then to process the resulting data into the k × ℓ memory elements 1 without changing the address b enroll. For example, if each of the areas shown in Fig. 16 is composed of K × L image data, it does not matter if the read address and the write address are the same if processing for moving or transferring a portion of a frame by an offset is carried out which a is an integer multiple of L in the horizontal direction and an integer multiple of K in the vertical direction. As a result, the load on the address control components such as the row address generator 4 and the column address generator 5 is considerably reduced.

The processing for moving or transferring is carried out by the processor unit 2 . The processor unit 2 receives an input of k × ℓ image data items according to the representation by the dashed partial areas in FIG. 16 and an input of image data over the entire individual image. Since the individual of these data items are offset by an integer multiple of L and K in the horizontal and vertical directions, the k × ℓ data items are exchanged or moved and transmitted in the processor unit 2 , the processing successively in the order from 0 can be executed with respect to all addresses of the memory elements. As a result, the whole frame can be processed.

In this embodiment, it can be considered by using a 1 × ℓ or k × l arrangement for the k × ℓ memory composition and by associating a horizontal or a vertical line in a frame with each of the memory elements that is executed in the processor unit 2 Processing to be used for various image processing, such as a histogram or frequency distribution preparation for a single line of an image or for a one-dimensional Fourier transformation. In addition, with simultaneous access to a large number of picture elements, there is no restriction as to which addresses of which storage elements are assigned to the data in a single picture.

Image data rotation

An example of the application of such a memory arrangement will now be described. Since a transfer of the data has been described above, a rotation of the data will now be explained. For the sake of simplification it is assumed that k = ℓ applies to the k × ℓ subdivisions of a k × ℓ memory element arrangement, so that a ℓ × ℓ arrangement results. Furthermore, for an area with K × L pixel data, assume that K = L. In this case, if a single image is to be pivoted through + 90 ° or -90 ° with the center of the image as the axis, the processor unit exchanges four data items from the ℓ × ℓ image data items, namely four data items offset from one another with respect to the center pivoted. If this is repeated with respect to the entire individual image, the individual image is thereby rotated by 90 °. As a result, the above-mentioned panning ℓ is carried out ^2/4 times for rotating the whole frame. In the case of a 180 ° rotation, it is sufficient to swivel or swap two data items offset by 180 ° relative to the center. To rotate an entire image frame by 180 °, the tilting takes place ℓ ^2/2-times. In this way, a single image is roughly rotated with this process. This corresponds to a rotation from the ℓ × ℓ regions according to FIG. 25 to the ℓ × ℓ regions according to FIG. 26. In fact, the rotations by + 90 °, -90 °, + 180 ° and the like must be carried out in the same way within the same areas.

The rotation within a frame would be without the rotation incomplete within the ranges. Now there is the rotation described within a range. This process includes a processing in which one when reading out a memory elements valid address to a when registered in a memory element applicable address is implemented. The Addresses are converted to those in the table below le 1 shown way.  

Table 1

A circuit for this processing is shown in Fig. 18 in detail as a block diagram, according to which a dial signal is changed depending on the rotation angle and is input as dial control signal in dialers 181 , 182 , 183 and 184 .

Normally, at the angle of rotation 0 °, the output signals of the row address generator 4 and the column address generator 5 are each fed directly via the selector 181 and 183 or 182 and 184 to the row and column addresses of the memory elements. If the angle of rotation is + 90 ° or -90 °, the column and row addresses are output signals a and b of the selector 181 and 182 respectively.

If the angle of rotation is 0 ° or 180 °, the output signals a and b of the selectors 181 and 182 respectively give the row and column addresses. At the angles of rotation 90 ° and 180 °, the output signal of a computing unit 186 is selected by the selector 184 . At the rotation angles -90 ° and 180 °, the output signal of a computing unit 185 is selected by the selector 184 . In the arithmetic units 185 and 186 , the input data are subtracted from the length L of one side of an area and signals for the result are output. With such an arrangement, the processing for rotating a whole frame shown in Table 1 is carried out.

There is now access to the storage elements for the Processing of all image data across a full frame described. That is, the following description relates to one Sampling or query procedure for access to all storage cherdaten.

Access to a memory in described the case that the local address of the start or Corner point u of adjacent k × ℓ blocks to be retrieved has been set, namely Y, X have been set, where Y which by counting in sequence from "0" to in number obtained in the vertical direction from the corner point and X is the one by counting in sequence from "0" obtained in the horizontal direction from the corner point Number is. An example will now be used to describe in the order in which the values X and Y are to be called up in order to Process full screen.

It will be an example of those to be applied to the storage elements  Query addresses explained. By dividing one Single image in ℓ × ℓ. Sections obtained correspond to areas the respective storage elements. Therefore, to be scanned of a single picture the same addresses to all memory elements elements and the addresses consecutively from "0" incremented. Since the addresses of the storage elements and row addresses, they are both both set to "0" then the column address from "0" to the last address is upgraded. Then the row address level, after which the column address of "0" up to the last address. This is for repeated access to all storage elements.

There will now be a more concrete example of processing for Rotation of an image described.

A method is explained below, according to which the simultaneous retrieval of a plurality of blocks of one original image the data from these blocks in parallel entered, processed in parallel and output in parallel the output after processing for rotation at angles of 0 °, 90 °, 180 ° and 270 °.

Fig. 25 shows the original image divided into blocks in a state which is achieved when an area of 256 x 256 picture elements is divided into blocks of 4 x 4 picture elements each.

Fig. 26 shows a state which is achieved when the original image is rotated 90 ° counterclockwise in block units. Fig. 27 shows a state that is achieved when the original image is rotated counterclockwise by 90 degrees in image element units within each block.

FIGS. 28 and 29 show the relative positions of the pixels in the respective blocks of the shown in FIG. Ur sprünglichen image or the rotated image shown in Fig. 27 25. In the images shown in FIG. 25 and 26 are the relative positions of the image elements in the respective blocks equal. If this is shown in the form shown in FIG. 28, the state shown in FIG. 29 results from the pivoting of the respective picture elements in each block by 90 ° counterclockwise.

In order to obtain an image produced by rotating the original image by 90 ° counterclockwise, the original image shown in FIG. 25 is processed with regard to the relationships between the blocks to the arrangement shown in FIG. 26, and then the picture elements in the respective blocks may be changed from the relative arrangement shown in FIG. 28 to the arrangement shown in FIG. 29.

Fig. 30 is a block diagram of an example of a circuit arrangement for executing a sequence of the processes described above. 251 and 1602 designate image memories for storing all image elements of original images shown in FIGS. 25 to 29, image memory 1601 being used for input and image memory 1602 for output. With 1603 is an arithmetic or arithmetic circuit with a processing circuit for processing picture element data items which are respectively read out in parallel. A processing circuit is provided for each block, so that the data from the blocks are each input to a corresponding one of the processing circuits, after which the processed data are output to respective output blocks. 1604 denotes a block data selection circuit, the details of which are shown in FIG. 31. 1605 denotes a circuit for the output of addresses which, as "inner block addresses", determine the positions to be called up in the blocks of the input image memory (input address generator). 1606 denotes a circuit for the output of addresses which, as inner block addresses, determine the positions to be selected in the blocks of the output image memory. 1607 denotes a control circuit for controlling circuits 1604 , 1605 and 1606 as a function of the angle of rotation.

The Blockdatenwählschaltung 1604 according to Fig. 31 formed by voters whose number is equal to the number of blocks, namely, in this embodiment Example 64. Each selector corresponds to a respective block of the output memory. A selector corresponding to a block in the i-th row and j-th column of the output memory, hereinafter referred to as block (i, j), receives data from four blocks (i, j), (m-j + 1, i ), (m - j + 1, m - j + 1) and (j, m - j + 1) of the input memory. Here, m means that the input-side memory and the output-side memory both consist of m × m blocks. This embodiment is described on the assumption that m = 8 holds. Furthermore, 1 ≦ i ≦ m and 1 ≦ j ≦ m.

When the original image is to be rotated 0 ° counterclockwise, the control circuit 1607 controls the block data selection circuit 1604 so that each selector (i, j) outputs. Similarly, the control circuit 1607 controls the block data selection circuit 1604 such that a counterclockwise rotation (j, m - j + 1) is selected for a 90 ° rotation and a counterclockwise rotation (m - j + for a 180 ° rotation) 1, m - j + 1) is selected and for a rotation by 270 ° counterclockwise (m - j + 1, i) is selected. In this way, an implementation or rotation corresponding to the illustration in FIGS. 25 to 27 is brought about.

The control circuit 1607 controls the inner block addresses of the address output circuits or address generators 1605 and 1606 . If a block contains n × n picture elements and an output is to be made to a picture element at one point (k, ℓ) in this block, the inner block address for the input side is used for the output when the original picture is rotated counterclockwise by 0 ° Block controlled on (k, ℓ). In the same way, the address is set to (ℓ, n - k + 1) for a 90 ° rotation, (n - k + 1, n - ℓ + 1) for a 180 ° rotation and for 270 ° rotation controlled to (n - ℓ + 1, k). In the described embodiment, n = 4. This can be done, for example, by using a look-up table as shown in FIG. 32 as circuit 1605 and an up counter as shown in FIG. 33 as circuit 1606 . Conversely, it is of course also possible to use the counter according to FIG. 33 as circuit 1605 and the look-up table according to FIG. 32 as circuit 1606 . In this way, a conversion or rotation can be accomplished which corresponds to that from FIG. 25 to FIG. 27 (or from FIG. 28 to FIG. 29).

From Fig. 30 it can be seen that, according to Fig. 34, the block data selection circuit can of course also be arranged at the output of the computing circuit. In this case, the output of each processing circuit of the arithmetic circuit is input to each of the four selectors of the block data selection circuit. In other respects, the arrangement is entirely the same as that shown in FIG. 30.

In the embodiment described above multiple items of image data corresponding to the rotation Recorded at the same time, which means that processing is quick processing is possible and the rotation of the image by means of a small-scale circuit can be accomplished.  

An exemplary embodiment will now be described below in addition wrote.

If the addresses assigned to the k × ℓ memory elements are retrieved in the sequence from address 0 to an end address in the manner described above, the respective k × ℓ. Storage elements output the image data from each of the areas, each corresponding to 1 / (k × ℓ) of the frame. If one considers only a single image element, the image of a partial area corresponding to a single area is successively queried and read out in the horizontal and vertical directions. If this is applied to the conventional processing of an image that is successively scanned horizontally and vertically across a frame, a processing speed can be achieved that is k × ℓ times as large as the conventional one. In addition, since the treated image area becomes smaller, the line buffers and the like also become smaller. As a result, the processor unit 2 can be constructed in a simple manner as a matrix processor. This is described in detail below.

Spatial frequency filtering

According to the foregoing, the image data from the k × ℓ memory elements 1 b are successively input into the processor unit 2 , which performs the spatial or spatial frequency filtering for the readout of the memory during the successive query. Although this will only be described after the following, the processor unit 2 contains buffers for a plurality of horizontal lines with a capacity for a rectangular area, in which individual processor elements, which are the components of the processor unit, each have a single one of the k × ℓ formed by the division Areas correspond. After the two-dimensional spatial or spatial frequency filtering, the resulting data are successively written in on the output side by a call which is identical to the call on the input side for reading. This embodiment will now be described in detail.

Referring to FIGS. 35 to 38 a single frame in 2 x 2 areas is divided while the memory elements 1 b, namely IMP EXP including four memory elements than 2 × 2 matrix are arranged. In this case, the image memory on the read side is read out in such a way that, according to FIG. 35, the areas are scanned simultaneously in the horizontal and vertical directions. However, since the image is assigned to the memory in the above-mentioned manner, the memory addresses are fetched in such a manner that the vertical address is incremented by "1" from 0 to the end address each time the horizontal address is from 0 to the end address has been upgraded, which is repeated with regard to all memory addresses.

Storage elements R1, R2, R3 and R4 according to FIG. 37, which form the read-side image memory, store the images of areas 1 , 2 , 3 and 4 according to FIG. 35 in this exemplary embodiment.

From an address set controlled by a control circuit nerators are applied to the read-side image memory Addresses to the memory elements R1 to R4 are the same Addresses created. These addresses are preceded by the described or retrieved. The from the Image elements read out from memory elements R1 to R4 each entered in processor elements PE1 to PE4. The Processor elements PE1 to PE4 take out as input signals the control circuit required control signals that the Determine the content of the processing. By means of the processor elements  PE1 to PE4 is the spatial or spatial frequency filtering executed. However, since the processor elements PE1 to PE4 each Because line buffers are included, the address genera Tor supplied horizontal addresses. Alternatively, the Hori zontal addresses generated in the processor elements PE1 to PE4 become.

The by the processor elements PE1 to PE4 of the spatial frequency Filtered output data are divided into respective Memory elements W1 to W4 are written, which write form image storage. In doing so, the memory elements W1 to W4 of the image memory on the write side same addresses. The addresses created are however, by delaying the read-only memory created addresses. The extent of the delay corresponds to the amount of delay of the target picture elements in the line buffers that are in the processor unit for the Spatial frequency filtering are provided.

With the arrangement described above, the spatial frequency filtering can be carried out with respect to almost the whole. Room in the full screen. However, since the partial areas shown in FIG. 36 by oblique lines and by shading are the peripheral edges of the areas, these partial areas remain unprocessed since the two-dimensional mask for spatial frequency filtering survives. To fill the unprocessed areas, the control circuit on the address generator causes the generation of addresses for the partial areas represented by the oblique lines, the shaded partial areas and the memory area corresponding to the extent. The image data are recorded successively from the image memory on the read side, after which the spatial frequency filtering is carried out by means of a central unit in the control circuit. The results of the filtering are written into the image memory on the write side. With regard to the addresses, the control circuit controls the address generator in such a way that the write-side image memory is addressed in exactly the same way as the read-side image memory. In the above-described embodiment, a certain processing time is required due to the fact that the spatial frequency filtering using the portions shown in Fig. 36 by the oblique lines is carried out by the central unit in the control circuit. However, since the ratio of the slant line portions and the shaded portions in Fig. 36 to the whole frame is very small, the effect on the processing time is almost negligible.

An embodiment will now be described in which this CPU processing is not carried out.

FIG. 39 is a simplified block diagram of this embodiment. With the exception that the entire single image is divided into 3 × 3 areas and that a data control circuit is provided, this embodiment is identical to the embodiment described above. The exemplary embodiment is therefore only described in detail when considering the differences.

In the exemplary embodiment, a single image is in 3 × 3 Areas are divided, however, is also considered to be more general Case described a case in which a single image in m × n Ranges is divided, where m and n are integers.

The Fig. 38 (a) and (b) show how a whole, che in 3 × 3 preparation divided frame is scanned.

For each area obtained by dividing a frame, an enlarged area as shown by the broken lines is formed, and the output signal for the enlarged area is input to a respective processor element ( 1 , 1 ) to ( 3 , 3 ). An enlarged area is given a format with which those which have remained unprocessed according to FIG. 35 after the spatial frequency filtering. Sub-areas are covered, namely in particular z. B. the unprocessed subareas at the borders between the loading areas ( 1 , 1 ), ( 1 , 2 ), ( 2 , 1 ) and ( 2 , 2 ) with regard to the area ( 1 , 1 ). Furthermore, with regard to any area (k, ℓ) (with 1 ≦ k ≦ m and 1 ≦ ℓ ≦ n), the area is enlarged in such a way that the unprocessed partial areas at the borders of the area (k, ℓ) to the areas (k , ℓ + 1), (k + 1, ℓ) and (k + 1, ℓ + 1) are also included in the spatial frequency filtering.

In the case of 3 × 3 smoothing processing using the processes sensor unit remains, for example, a picture element on the computer th edge of each area (k, ℓ) unprocessed. By doing adjacent area (k, ℓ + 1) remains a picture element on the left margin unprocessed. Therefore, the area (k, ℓ) around a total of two picture elements extended to the right. the same is an enlargement by two picture elements downwards required.

The enlarged portions (1, 1) to (3, 3) are Abta stung as shown in Fig. 38 (a) and (b) in the processor elements (1, 1) to (3, 3) is entered. The addressing of the memory elements will now be briefly described. The control circuit controls the address generator so that the horizontal address is sequentially incremented from 0 to the maximum address. After that, the address is incremented from 0 to the address of the area enlarged to the right. If two picture elements are expanded to the right, addresses 0 and 1 are output, after which address 0 is output as the horizontal address. Next, the vertical address is incremented from 0 and the scanning of the horizontal address is repeated. Then the vertical address is upgraded again and the scanning of the horizontal address is repeated. After repetition of these operations, the vertical address, the maximum address and the scanning of the horizontal address are completed, whereupon the vertical address is then brought to 0 and the above operations are repeated up to the address of the area enlarged downwards. The data control circuit transmits the data in such a sequence that the output signals from the enlarged areas ( 1 , 1 ) to ( 3 , 3 ) are assigned to the processor elements ( 1 , 1 ) to ( 3 , 3 ).

Next, the data control circuit shown in Fig. 40 will be described. In the generally applicable case, the kth circuit is formed from m × n 4: 1 selectors.

The to a processor element (1, 1) output signal output of a selector (1, 1) is one of the (2 2) input signals from the memory elements (1, 1), (1, 2), (2, 1) and. In response to a selection control signal from the control circuit, each selector outputs one of the four input signals applied. The input signals applied to the selectors at the output to the processor elements (k, ℓ) come from the memory elements (k, ℓ), (k, ℓ + 1), (k + 1, ℓ) and (k + 1, ℓ + 1). However, if the values k + 1 and ℓ + 1 exceed the corresponding values m and n with regard to the range subdivisions m and n for any values k and ℓ, no or empty data are accordingly entered at the input.

There will now be described the dial control signal output from the control circuit for the voters. During the time that the control circuit controls the address generator to step the horizontal address from 0 to the end address and then to scan from 0 to the address of the enlarged area as described above, namely the area (k, ℓ + 1) is covered, the output signal (k, ℓ + 1) is selected and output. Further, during the time that the vertical address is incremented from 0 to the end address and then scanned from 0 to the address of the enlarged area (which is "1" in 3 × 3 spatial frequency filtering, for example) if the range (k, ℓ) overlaps with the range (k + 1, ℓ), the output signal (k + 1, ℓ) is selected and output. If both are the case, namely the enlarged area overlaps the area (k + 1, ℓ + 1), the output signal of the memory element (k + 1, ℓ + 1) is selected by means of the control circuit. This is additionally explained with regard to a data control circuit between the processor unit and the write-side image memory. The circuit arrangement is similar to that of FIG. 40. In this case, however, the input signals for the output of the output signal of a selector to a memory element (k, ℓ) are the signals (k, ℓ), (k, ℓ - 1), (k - 1, ℓ) and (k - 1, ℓ - 1). If the enlarged areas of the type shown in Fig. 38 (a) do not cover the unprocessed partial areas of the three areas on the left, below and below left with respect to the area (k, ℓ), but the areas are enlarged in such a way that only the upper, lower, right and left unprocessed partial areas within the area (k, ℓ) are detected, a data control circuit between the processor unit and the writing image memory is not required. In this case, for the selector output signal (k, ℓ), the input signals of the data control circuit between the read-side image memory and the processor unit must have the signals (k, ℓ), (k - 1, ℓ - 1), (k - 1, ℓ ), (k - 1, ℓ + 1), (k, ℓ - 1), (k, ℓ + 1), (k + 1, ℓ - 1), (k + 1, ℓ) and (k + 1 , ℓ + 1). This is easily seen from Fig. 38 (b). It should be added that the voters must select the data from nine areas contained in the enlarged areas, namely nine memory elements, and must enter this data into the processor element (k, ℓ) of the processor unit. A data control circuit is required to control k × ℓ voters.

Next, the data output from the data control circuit is input into the respective processor elements that constitute the processor unit. The processor elements ( 1 , 1 ) to ( 3 , 3 ) contain line buffers for several lines of the extended areas. After the spatial frequency filtering, the data are output via the data control circuit, not shown in FIG. 39, to the memory elements ( 1 , 1 ) to ( 3 , 3 ) which form the image memory on the write side. The data control circuit also corrects the results of the spatial frequency filtering when an area is an enlarged partial area. Here, the addresses applied to the respective memory elements of the write-side image memory by the address generator are identical. With respect to the addresses applied to the read-side image memory, however, the addresses applied to the write-side image memory are delayed by a time period which corresponds to a delay in the processor elements. Even if spatial frequency filtering is carried out in the enlarged areas, the edges of the enlarged areas are essentially not subjected to spatial frequency filtering. For example, in processing for 3 × 3 smoothing or the like, the output areas are made smaller by the width of one picture element to the left, right, up and down at the same time than the enlarged areas. The image memory on the write side is only switched on when data are output for an area that has been subjected to spatial frequency filtering.

If in spatial frequency filtering using a processor elements the width of the output area at the top, bottom, left and decreased right, the area is the same  Format returned as that of the range (k, ℓ), wel cher the memory element (k, ℓ) of the picture-side image memory chers corresponds. Therefore, there is no data control circuit between the processor unit and the picture-side image memory required.

The bil in this embodiment the processor unit The processor elements are now described in detail.

The Fig. 41 is a block diagram according to an example of the structure of a 3 × 3 smoothing filter room or spatial frequency filter. The image data applied to a processor element from a read-side memory element via the data control circuit are input into a buffer memory 2604 and a line buffer 2601 . The output signals of the line buffer 2601 are input into a buffer 2607 and a line buffer 2602 . The output signals of line buffer 2602 are input to a buffer 2610 . The line buffers 2601 and 2602 are supplied with an address from a counter 2603 and an address from an address counter (not shown) as shown in FIG. 39. The counter 2603 receives an image transfer clock signal from the control circuit at every second horizontal picture element of the enlarged area to thereby increment the address, and as an input signal from the control circuit a delete signal at every horizontal line, whereby the address is deleted. The line buffers are designed for simultaneous reading of input signals and writing of output signals.

As a result of this function, image data from specific locations on three contiguous horizontal lines are entered into buffers 2604 , 2607 and 2610 . Between memories 2604 to 2612 are formed by D flip-flops. The output signals of buffers 2604 , 2607 and 2610 are successively output to buffers 2606 , 2609 and 2612 via buffers 2605 , 2608 and 2611 by the image transfer clock signals from the control circuit .

The output signals of the latches 2604 to 2612 at this point in time are 3 × 3 contiguous picture elements in a single picture. These output signals are applied to an adder 2613 which calculates or summarizes the total number of picture elements. The result is input to a divider 2614 which multiplies the input signal by 1/9 to perform 3 × 3 smoothing. The resulting output signal of the divider 2614 is output to the write-side memory element or the data control circuit connected to the write-side memory element.

Although the spatial frequency filtering process has been described, however, of course, the processor unit forming processor elements each by processors such as Central units should be formed.

Furthermore, the edge region of a single image, namely the shaded or gray partial region shown in FIG. 36, cannot of course be subjected to the spatial frequency filtering in the case of both spatial frequency filtering processes.

Since, according to the preceding explanations, a single image in m × n Areas is divided, the image area is reduced is associated with a single storage element. This one Requires corresponding spatial frequency filter processor just a line buffer for a small area. hereby it becomes possible to have a processor with a high degree of integration use that contains a variety of buffers. As a pro processor can be a central processing unit (CPU) or a central processing unit  with an internal read / write memory (RAM) or Ar be used memory. Since m × n areas at the same time the spatial frequency filtering is the Verar processing time considerably reduced.

In the above-described embodiments uses an array of m × n memory elements, what that simultaneous retrieval and processing of m × n picture elements enables so that fast image processing is achieved becomes.

Furthermore, by using an arrangement for a sys tem, in which m × n contiguous picture elements in one zelbild m × n memory elements are assigned such that the Image elements can be called up simultaneously, or for a system in which m × n randomly distributed picture elements in one Single image m × n memory elements assigned in the manner are that these picture elements are retrieved simultaneously can, the two-dimensional filtering is smaller gender spaces in the former case and processing to Moving or moving in the latter case easier. On this is the memory access for executing the for the image processing enables suitable processes.

Furthermore, in the above-described embodiments play as a result of the k × ℓ memory element arrangement instead retrieval of all memory elements enables masking. That is, when processing such as the local fre frequency filtering, the processing often proceeds in such a way that the processing results blocks of small format like the Format 1 × 1. However, processing becomes possible in the embodiment as described above play the format of the memory element array and that Format of the retrieved image are different from each other.  

In this way, with the exemplary embodiments, an image processing device created that image processing through parallel processing in a finite small Number of processors running at high speed.

Based on the drawing, the processing for room or Spatial frequency filtering further described. The following will described a process in which the respective rectangular Areas of m × n picture elements of an original picture corresponding image data in an image memory at the same time the image data are retrieved from a matrix processor unit from m × n processor elements, of which each is assigned to a corresponding picture element by the matrix processor unit out the spatial frequency filtering leads and the results are output.

Fig. 42 shows the mapping between a one ur sprünglichen image corresponding input block 281, Figu elements 281 a in the input block, a matrix processing unit 282, processor elements 282 a in the matrix processor unit, an output block 283 and picture elements 283 a in the output block. Here, m = n = 4. As a result, 16 picture element data of the input-side memory are called up simultaneously and recorded by the matrix processor unit. The matrix processor unit consists of 16 processor elements. The matrix processor unit carries out spatial frequency filtering in an area of 3 picture elements × 3 picture elements and outputs the results to a block of the output-side memory formed from 2 picture elements × 2 picture elements, namely a total of 4 picture elements.

The processor elements in the matrix processor unit are arranged corresponding to the 4 × 4 picture elements to form a square grid-like 4 × 4 matrix. The processor elements are numbered sequentially in the row direction and column direction. Referring to FIG. 43, the processor elements can be distinguished by their vonein other designation with the row number and the column number.

The spatial frequency filtering consists in that, using a coefficient matrix of the type shown, for example, in FIG. 44, the product of coefficients for each corresponding picture element is formed and the sum is output in a memory location corresponding to a central location. This is described with reference to FIG. 42. Specifically, the processor elements ( 1 , 1 ), ( 1 , 2 ), ( 1 , 3 ), ( 2 , 1 ), ( 2 , 2 ), ( 2 , 3 ), ( 3 , 1 ), ( 3 , 2 ) and ( 3 , 3 ) formed 3 × 3 area subjected to a computing process by means of the processor element ( 2 , 2 ). The data are recorded from the other processor elements and the spatial frequency filtering is carried out. In a similar manner, the spatial frequency filtering is carried out on the processor elements ( 1 , 2 ), ( 1 , 3 ), ( 1 , 4 ), ( 2 , 2 ), ( 2 , 3 ), ( 2 , 4 ), ( 3 , 2 ), ( 3 , 3 ) and ( 3 , 4 ) 3 × 3 area formed by the processor element ( 2 , 3 ) and on the by the processor elements ( 2 , 1 ), ( 2 , 2 ), ( 2 , 3 ), ( 3 , 1 ), ( 3 , 2 ), ( 3 , 3 ), ( 4 , 1 ), ( 4 , 2 ) and ( 4 , 3 ) through the processor element ( 3 , 2 ). Furthermore, the processor elements ( 2 , 2 ), ( 2 , 3 ), ( 2 , 4 ), ( 3 , 2 ), ( 3 , 3 ), ( 3 , 4 ), ( 4 , 2 ), ( 4 , 3 ) and ( 4 , 4 ) formed 3 × 3 area of the spatial frequency filtering by the processor element ( 3 , 3 ).

The processor elements ( 2 , 2 ), ( 2 , 3 ), ( 3 , 2 ) and ( 3 , 3 ) for the spatial frequency filtering contain a circuit of the type shown in Fig. 45 by which the spatial frequency filtering is carried out. In the circuit of Fig. 45, the data is HEADPHONES from the eight adjacent processor elements by means of Addie adds 221-227 and then processing by means of a sliding formwork and a shift register 228 multiplied by 1/8. A subtractor 229 calculates the difference between the output signal of the shift register 228 and a value for the target picture element, which is taken up by the processor element with this circuit itself or directly and is first delayed by means of a delay circuit 231 . An adder 230 adds the difference output by the subtractor 229 with the value directly received by the processor element after its delay by means of a delay circuit 232 . In this way, a 4 × 4 picture element area is input and an output signal is output to a 2 × 2 picture element area.

In this description, spatial frequency filtering of a 3 × 3 picture element area with a 4 × 4 picture element area as input and a 2 × 2 picture element area as output is explained. However, there is no limitation to this arrangement. Rather, it is obvious that the spatial frequency filtering for a p × q picture element area with m ≧ k + p and n ≧ ℓ + q can be carried out with an input of an m × n picture element area and an output of a k × ℓ picture element area. In addition, with regard to the coefficients for spatial or spatial frequency filtering, there is no restriction to those shown in FIG. 44. It is only necessary to use a processor element with a processing circuit which corresponds to a coefficient matrix.

While processing according to the prior art for a every single output pixel is repeated in the described embodiment, the results of Processing for multiple output pixels in the same Cycle output, so that a very high processing area speed can be reached.

By entering coherent, closely related Neighboring picture elements at the entrance can be the spatial frequency filtering can be carried out in one cycle so that it is possible is the results of spatial frequency filtering for a  Output a plurality of output pixels simultaneously.

By simultaneously retrieving and processing a lot Number of data entered is the processing speed compared to the individual retrieval of the data elevated. In addition, processing (spatial frequency filtering, color processing, etc.) where the context between simultaneously retrieved data by a data exchange between processor elements is to be taken into account, be carried out by a single input data retrieval.

Image data expansion and reduction

In further exemplary embodiments of the image processing device described below, an image enlargement is carried out in the processor unit 2 . However, there is no restriction on the number k × ℓ or K × L of the memory elements that form the read-side image memory and the write-side image memory. Although only the expansion or enlargement is described in this exemplary embodiment, a reduction or reduction is achieved in the same way. Furthermore, there is no restriction with regard to the block formats k '× ℓ' or K × L 'of the picture elements called up on the read side and on the write side. However, it must be assumed that when the image is enlarged by means of the processor unit 2, the format obtained by enlarging the format k '× ℓ' retrieved on the read side must meet the conditions K '<αk' and L '<βℓ', where α and β are the maximum Longitudinal magnification factors are 60895 00070 552 001000280000000200012000285916078400040 0002003845004 00004 60776 and transverse direction.

Next, the enlargement will be described. According to Fig. 46 312 includes a processor unit an address generator 313 and a computing circuit 315 and is operated under the control of a control circuit 311. The address generator 313 generates a start address for an input image memory 316 which contains input image data required for the calculation. A respective processor element in the arithmetic circuit 315 calculates output image data for output to an output-side image memory 317 from the input image data. The arithmetic circuit 315 receives all image data of a data area with the start address as an edge of the image area. Each processor element selects the input image data corresponding to the position in the output image memory 317 for the output of the processing results from the recorded data, carries out a two-dimensional interpolation and outputs the results.

This is described in somewhat more detail. For the description it is assumed that the processor unit 312 is equipped with processor elements for four columns in a main scanning direction and four lines in a sub-scanning direction, namely with 16 processor elements. The input image memory 316 simultaneously outputs to the processor unit data for five columns in the main scanning direction and five lines in the sub-scanning direction, namely a data area of 25 picture elements. The address generator 313 determines which data in the data area is output from 5 × 5 picture elements. The structure and function of the address generator 313 will now be described with reference to FIG. 47. The address generator 313 is constructed with a main scanning direction circuit, hereinafter referred to as a main scanning circuit 1 , which outputs an address determining the main scanning from the addresses of a predetermined 5 × 5 pixel area, and with a sub-scanning direction circuit, which follows is referred to as subsampling circuit 1 and outputs an address determining the subsampling direction from the addresses of the predetermined 5 × 5 pixel area. In a register 321 , the control circuit 311 presets a value which is four times the reciprocal of the magnification factor for the main scanning direction. In a register 322 , a value is preset by the control circuit 311 which is four times the reciprocal of the magnification factor for the sub-scanning direction. A latch 325 is cleared to an "0" by an operation sync signal for the sub-scan, after which the latch receives the output of an adder 323 upon an operation sync signal 327 for the main scan. In response to the operating synchronization signal 327 for the main scanning direction, the value set in the register 321 is added by the adder 323 to a value stored in the buffer memory 325 and the result is output. As a result, by synchronizing the function for the main scanning direction, the value output from the buffer 325 is gradually increased by a value which is four times the reciprocal of the magnification factor for the main scanning direction, after which the buffer is cleared to "0" as soon as the synchronization for the sub-scanning direction takes place. Register 322 , adder 324, and latch 326 operate in exactly the same way when sub-scan synchronization replaces main scan synchronization and page synchronization replaces sub-scan synchronization. In this embodiment, a signal defining a 5 × 5 pixel area in the input frame memory 316 is formed depending on the integer parts stored in the latches 325 and 326 . In accordance with this determination signal, the input frame memory 316 outputs the 25 picture element data for an area having five picture elements in the main scanning direction and five picture elements in the sub-scanning direction starting from the above address. With respect to the addresses for the output-side frame memory 317, the Adres be sen for four pixels of the output image memory 317 corresponding to the main scanning synchronization and in the sub-scanning the addresses for four picture elements of the image memory 317 is increased in accordance with the Unterabtastungssyn chronisation in the main scanning direction.

From an input correction part 314 in the processor unit 312 , suitable four picture element data are selected from the entered 25 picture element data and address correction signals for the application of an interpolation coefficient for the interpolation to the 16 processor elements in the computing circuit 315 are generated.

FIG. 48 shows the structure of processor unit 2 or 312 , in which 331 denotes the address generator 313 described with reference to FIG. 47. The address correction part 314 includes sections 332 and 332 'of main scanning circuits 2 , 3 and 4 and sub-scanning circuits 2 , 3 and 4 , respectively, which are similar to the main scanning circuit 1 and the sub-scanning circuit 1 described in connection with FIG. 47. Of the main scanning registers 321 in the Hauptab 2 tastschaltungen to 4 includes the register 321 in the Hauptabtastschaltung 2 is a value which is always to the reciprocal of the magnification for the main scanning direction larger than the value in the register 321 of the Hauptabtastschaltung. 1 Similarly, of the registers 321 in the circuits, the register in the main scanning circuit 3 contains a larger value than the register in the main scanning circuit 2 and the register in the main scanning circuit 4 contains a larger value than the register in the main scanning circuit 3 . On the other hand, the values in the subsampling registers 322 in the subsampling circuits 2 to 4 are each larger by the reciprocal of the magnification factor for the subsampling direction, the value in the subsampling circuit 4 being larger than that in the subsampling circuit 3 , the value in the subsampling circuit 3 being larger than that in the Unterab sampling circuit 2, and the value is in the sub-sampling circuit 2 is larger than that in the sub-sampling. 1 The output signals of the main scanning circuits 2 to 4 and the sub-scanning circuits 2 to 4 are each used as signals which determine which four picture elements of the 25 picture elements in the input range are to be selected. As an example, consider the case that a magnification factor of 2, 5 for the main scanning direction and a magnification factor of 1, 5 are provided for the sub-scanning direction. The Hauptab sampling circuit 1 by one every time to 1.600 (= 4 × 1 / 2.5) high, while the sub-sampling circuit 1 in each case counts up to 2,666 (= 4 × 1 / 1.5), wherein the integer part of the count in the stands 1 Hauptabtastschaltung and the subsampling circuit 1 are used and are used as start addresses for the area of 25 picture elements in the input-side image memory 316 . Furthermore, the decimal fraction output from the main scanning circuit 1 is used as the auxiliary coefficient data for the main scanning direction for one column of the processor matrix, namely for the four processor elements ( 1 , 1 ), ( 2 , 1 ), ( 3 , 1 ) and ( 4 , 1 ) is inserted according to FIG. 48. The decimal fraction from the subsampling circuit 1 is used as the auxiliary coefficient data value for the subsampling device for one row of the processor matrix, namely for the four processor elements ( 1 , 1 ), ( 1 , 2 ), ( 1 , 3 ) and ( 1 , 4 ) Fig. 48 used. The sizes counted by the main scanning circuits 2 , 3 and 4 differ from each other by 0.4 (= 1 / 2.5), while the sizes counted by the sub-scanning circuits 2 , 3 and 4 differ from each other by 0.666 (= 1/1 , 5) differentiate. The intermediate memories storing these counts are deleted each time with regard to their integer parts, while they add up the fractional parts. The Hauptabtastschaltungen 2 to 4 giving the integer part and the decimal fractions to the processor elements in the second to fourth column of the Prozes sormatrix, while the Unterabtastschaltungen 2 to 4, the integer part and the decimal fractions of the Prozes sorelemente in the second to fourth rows of the processor submit matrix. Each processor matrix selects four picture elements from the 25 picture element data from the input picture memory 316 depending on the integer parts of the data stored in the corresponding main-scan latches 325 and the corresponding sub-scan latches 326 , then perform the two-dimensional interpolation with an interpolation coefficient dependent on the decimal fraction and output the interpolation results to the corresponding output-side image memory 317 . The output-side image memory 317 is always addressed using a 16-pixel area of 4 × 4 pixels as a unit, with each processor unit being assigned one of the 16 pixels.

FIG. 49 shows a selection circuit, one of which is contained in each processor element, namely a circuit for selecting four picture elements from 25 picture elements. FIG. 50 shows an example of the construction of a selection circuit shown in FIG. 49 720 , which is shown consisting of main scan selectors 351 to 355 and sub-scan selectors 356 and 357 . Fig. 51 shows an example of the structure of each main scan or sub-scan selector. Each main scan or sub-scan selector can be constructed from two selectors 361 and 362 , each having four inputs and one output. Regarding the integer parts from the main scanning circuit 1 and the sub-scanning circuit 1 , the values "0" are always output to the processor elements of each individual column and each individual row. As a result, each processor element (i, j) selects an I-th, an (I + 1) -th, a J-th and an (J + 1) -th of the four input signals corresponding to an output signal (I, J) for the integer parts of a main scanning circuit i and a sub-scanning circuit j. As a result, the processor elements (i, j) as four picture elements out of the 25 picture elements form the picture elements (I, J), (I + 1, J), (I, J + 1) and (I + 1, J + 1 ) selected.

Next, in an interpolation circuit 740 for two-dimensional linear interpolation shown in Fig. 52, assume that the input values for the four picture elements V (I, J), V (I, J + 1), V (I + 1, J) and V (I + 1, J + 1) and that the interpolation coefficients for the main scanning direction and for the sub-scanning direction are α and β, respectively. These are known as decimal fractions from the corresponding Hauptab tastschaltungen 1 to 4 and applied to Unterabtastschaltungen 1 to 4. Then the calculation is (1 - β) {(1 - α) V (I, J) + αV (I + 1, J)} + β {(1 - α) V (I, J + 1)) + V (I + 1, J + 1)}, where the interpolation results are output, with 0 ≦ α and β <1.

The function of the processor unit 312 is described above. The relationship between the picture element areas of the input-side image memory 316 , the processor unit 312 and the output-side image memory 317 is shown in FIG. 53. Specifically, the number of processor elements in the processor unit 312 is equal to the number of picture elements in the output-side image memory 317 , while the number of image elements in the image area used for processing in the input-side image memory is smaller than the number of processor elements in the processor unit 312 ,

While in the prior art processing for one every single picture element output is repeated, who the in the embodiment described above Processing results for a variety of output pixels  issued in the same cycle, so a very high processing speed can be achieved.

It is also possible to use interpolation at the same time Input of contiguous, closely adjacent picture elements the input memory.

The structure and function of the processor unit 2 and 312 shown in FIG. 46 will now be described in addition with reference to FIGS . 66 to 68.

The Fig. 66 shows the structure of the input side Bildspei Chers 316 and the processor unit 312. The processor unit 312 is Fig mutandis. 66 analyzers with a set of digital difference or integrators (DDA) from Hauptabtastschaltun gen 1 to 4 for the main scanning direction, a group of both digital integrators Unterabtastschaltungen 1 to 4 for the sub-scanning direction, a group of voters for the Select four from 25 picture elements and a processor element group composed of processor elements for the respective voters of the voter group.

The Fig. 67 shows the relationships between the processor elements of the processor elements and the group of pixels in a pixel block of the output image memory 317th

Fig. 68 is a Fig. 47 supplementary representation and serves to describe the main part of a digital integrator, which is shown in Fig. 66 as main sampling circuits 1 to 4 and subsampling circuits 1 to 4 .

Referring to FIG. 68, the illustrated as Hauptabtastschaltungen 1 to 4 and 1 to 4 Unterabtastschaltungen digital integrator receives as Aufstufungswert a value that is four times the reciprocal of the magnification to be changed. In this embodiment, since the processor element group consists of 4 × 4 and 16 processor elements, respectively, the main sampling circuits 1 to 4 and the sub-sampling circuits 1 to 4 have, as step-up values, all the values which are four times the reciprocal of the magnification factor. If the processor element group is formed from m × n processor elements, a digital integrator from main scanning circuits 1 to m receives a step-up value that is m times the reciprocal of the magnification factor, while a digital integrator from sub-sampling circuits 1 to n receives a step-up value that is n times the reciprocal of the magnification factor. For example, if the magnification factor is 8 , the gradation value is 4 × 1/8 = 1/2. Accordingly, in the digital integrator for the main scanning direction, namely in the main scanning circuits 1 to 4, the adders and buffers operate in synchronism with the main scanning sync signal. In response to this synchronization signal, each processor element outputs a value which corresponds to a single picture element of the output picture. These values are output under time control by a single synchronization clock signal to the block of the image memory 317 for the output of an image from 4 × 4 or 16 picture elements. At the time of the next synchronizing clock signal, the picture element values for the adjacent block of 4 × 4 picture elements are output in the output-side picture memory 317 and written into the memory. Thereafter, the picture element values are sequentially output in the main scanning direction in units of blocks of 4 × 4 picture elements. These pixel values are output and written into the output side image memory 317 to the right edge thereof, whereupon the main scan returns to the starting point and the sub-scan proceeds to a block which is shifted by one block (with respect to the image area down) is. This is achieved in that the memory output signal in the digital integrator with the subsampling circuits 1 to 4 is increased in synchronization with the subsampling synchronizing signal by the increment value and the buffer of the digital integrator with the main sampling circuits 1 to 4 is reset by the subsampling synchronizing signal. The correspondence between the values output by the processor elements and the picture elements of the picture element block in the output-side image memory is shown in FIG. 67.

Each processor element receives an interpolation coefficient to form the correlation or correlation by using the decimal fractions of the digital main sampling integrator and the digital subsampling integrator (whereby for the processor element location (i, j) the main sampling integrator of the main sampling circuit i and the subsampling integrator of the subsampling circuit speaks j). That is, the decimal fractions themselves are used as interpolation coefficients. The integer parts output by the digital main-scan integrator and the digital sub-scan integrator (DDA) express the correspondence between the output picture elements to be written, the values of which are output by the processor elements, and the addresses of the picture elements in the input picture memory. "Adjacent to a single picture element" in the memory for the output image means a position which is adjacent by a distance which is equivalent to the reciprocal of the magnification factor in the input image memory (namely, in the case of the magnification factor 8, the position adjacent to 1/8) , This position should be referred to as the "imaginary position". As a result, interpolation is required to obtain data for this imaginary location. The integer part of the output signal of the digital integrator indicates an address in the input image memory at which an input image element closest to the imaginary location actually exists, while the decimal fraction represents a displacement from the location of the actually existing input image element to the imaginary location. As a result, the decimal fraction is used to form the interpolation coefficient. The integer part is used as an address in the input image memory for the input image data to carry out the above-described interpolation. The integer parts of the main scanning circuit 1 and the sub-scanning circuit 1 are addresses of the location in the upper left corner of the 5 × 5 pixel area that can be processed in the 16 processor elements. This is shown in Fig. 66. If the magnification factor is "1" (1: 1 scale), all 5 × 5 picture elements are used at least once in any of the 16 processor elements. Once the magnification factor is larger, only the pixels in a small area away from the upper left portion of the 5 × 5 pixel area are used. As a result, circuit at a magnification factor of about "1" by the integer parts from the main scan 1 and sub-sampling circuit 1, the 25 Bildelemen device data for the clutch at the points at the upper left nen 5 × 5 pixels in every 16 voters entered. The selector SEL are each assigned to one of the processor elements, so that a processor element PE (i, j) speaks to a selector SEL (i, j). According to the differences calculated by subtractors 710 and 712 between the integer parts of the corresponding digital integrators for the main scanning and subsampling and the integer parts from the main scanning circuit 1 and the sub-scanning circuit 1 , the corresponding processor element selects which four picture elements from the 5 × 5 or 25 picture elements are the required input picture data. This assignment is shown in Fig. 66. The processor elements of the first column always process picture elements of the first and second column of the input 5 × 5 picture element group. Similarly, the processor elements of the first line always process the picture elements of the first and second lines of the input 5 × 5 picture element group. Therefore, Fig. 66 shows that a constant is entered in the first column selector instead of the integer values from the main digital scanning integrators, and a constant is also entered in the first row selector instead of the integer values from the digital subsampling integrators becomes.

The interpolation process performed by each processor element is similar to the interpolation circuit 740 shown in FIG. 52 for two-dimensional interpolation processing and therefore need not be described again.

Image data compression

In one exemplary embodiment of the image processing device described below, the processing carried out by the processor unit 2 is an image compression. There is no particular restriction on the number k × ℓ or K × L of memory elements that form the image memory on the read side or write side.

Furthermore, with regard to the block formats k '× ℓ' and K '× L' the picture elements retrieved in the memories are not On restriction to the example described below. There are but the conditions 1 ≦ k '≦ k, 1 ≦ ℓ' ≦ ℓ, 1 ≦ K '≦ K and 1 ≦ L' ≦ L observed.

It will now scan for memory access at the The embodiment described below is explained. Out the previous statements (regarding the first case it can be seen that without limitation to the Read side or the write side then when the retrieved  Picture element format equal to the format of the respective picture memory-forming memory elements, the sampling in each of the image memories according to the one described above first follow-up query procedure can be carried out. If on the other hand in the read-side and write-side image memory to retrieve a picture element format that smaller than the format of the memories forming the memory elements, the sampling can be according to the previous block follow-up polling procedures (5th example).

A process will now be described in which an image store image data at the same time, which is right angular areas from m × n picture elements of an original Image, the image data simultaneously from a Pro processor unit made up of processor elements in a number are taken that are smaller than the block format m × n of the right square area in the image memory, then the image data as information from the respective processor elements below Exchange of information between the processor elements be processed, whereby the input image data is compressed and the results in the output image be output in a rectangular area that smaller than the block format m × n of the rectangular area in input image memory for the original image is so that the original image on the input side data is compressed. To simplify the description assume that the block format of the rectangular area in the input image memory m = n = 4 is that the number of the processor elements is "2" and that the block format of the rectangular area in the output image memory 1 × 1 = 1 is.

Fig. 54 shows the relationship between an input pixel block 561 in an input-side frame memory 560 to the original image, picture elements 561 a, a processor unit 562, processor elements 563 a and 563 b and output picture elements 564 a memory in an output-side image 564 for the output of compressed data. A control signal is input from a control unit 565 into the processor unit 562 and the input-side image memory 560 , whereby the image data from the image element block 561 from 16 associated image elements in the input-side image memory 560 are called up simultaneously and the required image data from the corresponding processor element 563 a and 563 b are recorded in the processor unit 562 . The processor unit 562 calculates typical density information 571 and detailed information 572 from the image data for the 16 image elements as shown in FIG. 55 and outputs the compressed image data as output image elements 564 a to the corresponding locations in the output-side image memory 564 .

Of the two processor elements 563 a and 563 b in the processor unit 562 , one, namely the processor element 563 a, is intended for the calculation of the typical density information 571 from the image data for the 16 picture elements, while the other, namely the processor element 563 b, is used to calculate the Detail information 572 is used, which is calculated based on image information which is binary-coded by means of a fixed threshold value which corresponds to the characteristic of the input image. The detailed information is, for example, data obtained by vector quantization of the binary-coded image information and data on the distribution of the image information. The setup and the process flow for compressing inputted original image data are summarized above. The details of the processing performed by processor elements 563 a and 563 b will now be described.

The processor element 563 a provided exclusively for calculating the typical density information 571 has, according to FIG. 56, a buffer 581 for temporarily storing the image data for the 16 image elements and an arithmetic or computing unit 582 . The processor element 563 A forms from the image data for the picture elements 16 has an average density value and outputs this value as a typical density information to the output-side frame memory 564 from. The processor element 563 b, which is used exclusively for compiling the detailed information 572 , likewise has a 16-pixel buffer 581 and a computing unit 582 according to FIG. 56. According to the properties of the input original image, the detailed information 572 , which is a block of interior pattern information obtained by binary coding the tint information for the 16 picture elements with a threshold value predetermined by a device not shown, and one of the threshold value and one contains the respective image element of the image data in the block, ascertained distribution information, together with the typical density information 571 , is output to the output-side image memory 564 .

The two processor elements 563 a and 563 b are designed to work in parallel, so that the compression is carried out at high speed.

When compressing as described above, the one aisle side image memory successively in memory block units of 4 × 4 picture elements queried. By the Repeat this process until processing is complete the last memory block of 4 × 4 picture elements in the Image storage will compress the original image of a page mized.

As described above, the fixed threshold value obtained by specifying a threshold value is used for calculating the detailed information from the compressed data. However, it can be seen that this threshold value can also be a value which corresponds to the average density output by the processor element 563 a. Furthermore, a single processor element can be inserted in the processor unit 562 .

In the embodiment described above the raw data for the entered original image during successive fetching in blocks of m × n pixels ment, namely 4 × 4 picture elements compressed. Therefore instead of fetching each picture element multiple times in the image data for m × n image to the input-side image memory elements accessed simultaneously. This makes it possible the image data under high speed compression transferability.

When the image data in block units of m × n picture elements can be encoded, a single encoding process by a single memory polling can be performed by that Format of the input memory block to the same m × n picture elements is set. This will make it quick Processing enabled and the structure of the facility ver simplified. Furthermore, in that in the processor unit Processor elements are provided in a number m '× n', which are smaller than the number m × n of picture elements in the input memory block, and that at every process sorelement the separate processing is brought about, the Cost of the processor unit can be reduced through the parallel processing the processing speed compression can be increased.

Another embodiment of a comm priming process described.  

The following describes a process in which a Image memory Image data for rectangular areas from m × n image elements of an original image retrieved at the same time the image data from a processor unit with m × n Processor elements are included, each one corresponding storage element for the respective picture elements te is assigned, the image data by means of the respective pro processor elements are compressed and the results in one Image memory can be output. In this description is for the sake of simplicity, assume that m = n = 4.

Fig. 57 shows the relationship between an input pixel block 591 in an input-side frame memory 590 for an original image pixels 591 a, a processor unit 592, processor elements 592 a and output image data 593 a in an output-side frame memory 593. According to a control signal from a control unit 594 , the image data of the picture element block 591 with 16 suitable picture elements are simultaneously retrieved from the input-side image memory 590 and recorded by the respective processor elements 592 a in the processor unit 592 . The processor unit 592 calculates the typical density information 571 and the detailed information 572 according to FIG. 55 from the image data for the 16 image elements and outputs the results to the image memory 593 on the output side.

The processor elements 592 a of the processor unit 592 are in a 1: 1 assignment to the 4 × 4 picture elements and are arranged in a grid or grid pattern in a 4 × 4 matrix of 16 elements.

The processing for image data compression is described in summary above. The details of the processing performed by processor elements 592 a will now be explained.

The processor elements 592 a in the processor unit 592 are numbered in row and column directions, so that they are shown in FIG. 58 and 59 distinguished from each other by the combination of these numbers.

The process for forming the typical density information from the image data for the 16 picture elements will now be described. It is assumed that the 16 processor elements 592 a shown in FIG. 58 have taken the corresponding image data. Each of the processor elements working in parallel ( 1 , 1 ),. , , ( 4 , 4 ) calculates 1/16 of the density data for each picture element, after which all the calculation results are added simultaneously by the processor element ( 1 , 1 ), from the density information for the 16 picture elements an average is formed and this value as the value of is given in Fig. typical density information 571 shown 55 over the typical density of the compressed data to the output-side frame memory.

The determination of the detail information 572 shown in FIG. 55 about the details in the compression data will now be described. The processor elements shown in FIG. 59 are the same as those shown in FIG. 58.

For quickly determining the pattern information of each picture element, which is obtained by binary coding of the tint information of each picture element in the 16 processor elements 592 a with the average density information given by the processor element ( 1 , 1 ) according to FIG. 58, as well as the average density information and the distribution information from each item of picture element data in the block, the 4 × 4 processor elements are divided into four blocks of 2 × 2 processor elements each, as shown by the solid lines in FIG. 59; in the four blocks of 2 × 2 processor elements, the pattern information and the distribution information are processed in parallel, after which the results as intermediate results in the four central processor elements ( 2 , 2 ), ( 2 , 3 ), ( 3 , 2 ) and ( 3 , 3 ) are saved; The processing described above is then carried out in the central block of 2 × 2 processor elements, after which the end result is formed in the processor element ( 2 , 2 ) and this value is output as detailed information 572 on the 16 image elements concerned to the output-side image memory.

By repeating the processing described above tion by successively calling up the input side Image memory in block units of 4 × 4 picture elements up to Completion of compression processing of the last 4 × 4- Blocks of picture elements of the original picture are compressed receive data that matches the original image of a Side are equivalent.

In the embodiment described above the raw data of the input original image subsequently in memory blocks of m × n picture elements, such as e.g. B. retrieved from 4 × 4 picture elements. Therefore, instead of more retrieving each pixel in the input page the image data for m × n picture elements is the same can be called up in good time. This enables a quick comm priming and transmission of image data.

When encoding the image data in block units from m × n Picture elements can be encoded by a single coding process single memory polling can be performed by that Format of the input memory block the same m × n Receives picture elements. This will result in quick processing device enables and the structure of the facility simplified. Furthermore, since the m × n processor elements in the processor unit with the same format as the input memory blocks  are designed for parallel coding the processing speed of the processor unit increases.

Image data compression and expansion

Another embodiment will now be described. at this are from an input-side image memory for a original image multiple image data items at the same time retrieved the respective rectangular areas from m × n image elements correspond, after which the image data from the processes sensor elements of the processor unit are included, the Image data are compressed and the results are consecutive following at corresponding points in the output side Image memories are output in a format m '× n' that is smaller than the block format when entering (m <m ', n <n'). In contrast, picture elements are simultaneously in one Block format m '× n' abge from the input image memory call, the image data recorded by the processor unit, executes expansion processing, and then at the same time to the image memory on the output side Image data for all image elements in the format m × n output, the is larger than the block format when entering (m <m ', n <n'). The. Memory block formats m × n and m '× n' established. Depending on the content of the processing, namely processing for compressing or expanding the format m × n on the input side and the format on the output side m '× n' or vice versa the format m '× n' and the format m × n is selected on the output side (where m <m 'and n <n' applies). In the following, the processing flow for Com priming and expanding described. To simplify assume that m = n = 4 and m '= n' = 1 and that the processor unit contains two processor elements.

First, as shown in FIG. 54, when compressing from a control unit 544 to a processor unit 541, a control signal is emitted, the input block format is set to 4 × 4 picture elements and the output block format is set to 1 picture element; then the image data for respective pixels 16 from an input-side frame memory 540 to retrieve the original image simultaneously and the required image data from each weiligen processor elements 541 a and 541 b in the processor unit 541 added. From the image data for the 16 image elements, the typical density information 571 and the detailed information 572 according to FIG. 55 are calculated by the processor unit 541 and the compressed image data are output to corresponding locations in an output-side image memory 542 .

Processing for expanding will now be described below of the compressed encoded data.

Fig. 60 shows the relationships between encoded data 540 a in the input side image memory 540 , the processor unit 541 with the processor elements 541 a and 541 b, an output image element block 543 for the output side image storage 542 and output image elements 543 a , A control signal is input from a control unit 544 into the processor unit 541 , the input-side block format is set to 4 × 4 picture elements, the coded data as shown in FIG. 55 from the input-side image memory are input into the processor unit 541 with the processor elements 541 a and 541 b, the respective processing is carried out and the reproduced image data for 16 picture elements are simultaneously output to a corresponding 4 × 4 rectangular area in the output-side image memory 542 . Each of the processor elements 541 a and 541 b of the processor unit 541 carries out processing that is opposite to that in the compression. For example, the density information for the image data of the 16 picture elements is determined from the typical density information 571 in the coded data and the distribution information in the detail information 572 . The image data for the 16 picture elements are reproduced simultaneously. Here, the plurality of processor elements 541 a and 541 b work in parallel so that the processing for the expansion can be carried out at high speed.

With this processing for expansion, the one coded data on the transmission side successively and it becomes the regarding the output image data Processing the successive data in block units made of 4 × 4 picture elements, up to none on the input side encoded data are available. That way will be out reproduced the image data for one page of encoded data Image data shaped.

According to this description, for the calculation of the detail information when compressing the data by default a fixed threshold is used. However, this threshold can also be a value that corresponds to the Through issued by another processor element section density value corresponds. Furthermore, in the processor A single processor element can be provided.

Furthermore, in the embodiment described above Example in which the input or output side block format is large, the processor elements as a grid shaped 4 × 4 matrix can be arranged. With the described The block formats 4 × 4 picture are exemplary embodiments elements and a picture element, however, these For mate can be chosen arbitrarily.

In the embodiment described above the raw data for the entered original image or the  output data reproduced successively in respective memory blocks from m × n picture elements, as in for example, 4 × 4 picture elements. Therefore, instead of retrieving each pixel multiple times in the image memory on the input side simultaneously image data for m × n Image elements are retrieved. This enables the transfer the image data under compression at high speed speed.

Furthermore, since the block formats of the frame buffer at the input side and the output side can be changed as for example from 4 × 4 picture elements and 1 picture element per 1 Picture element and 4 × 4 picture elements do not have to be separate Compressing device and an expanding device hen be so that a single facility is sufficient. In this way, the number of components required the facility is reduced to a minimum.

In addition, since the input block formats as separate Other block formats can be selected, a maskie Processing no longer apply, at which required picture data not read or not re-registered.

Since the processor elements in the processor unit also Executing processing in parallel becomes processing processing speed of the processor unit increased.

In the above-described embodiment, parallel processing for image compression and image expansion is carried out at high speed. When compressing and expanding an image, it is sufficient to assign the addresses as described above with reference to FIGS. 16 and 17.

Color processing

Image processing of a digital color image will now be described. The color information in a digital color image is expressed as a combination of, for example, red R, green G and blue B. Therefore, image memories are provided for R, G and B, each of which has a capacity to store data with a depth of 8 bits for a respective color. For rapid processing of the color information stored in the manner mentioned above, one of the type arrangement is selected such that corresponding processor elements are assigned in a 1: 1 correspondence to corresponding image memory cells for R, G and B, the processing for R, for G and B is executed in parallel and an information exchange between the respective processor elements is made possible. Figs. 61 shows the configuration of an image memory 402 for one page, and an n × n - processor unit 401, such as a 4 x 4 processor unit.

Fig. 61 illustrates only the theoretical arrangement of the basic components and shows that the processor unit 401 is connected to the image memory 402 for R, G and B. According to Fig. 61 n x n image data item for each of R, G and B are transmitted at any pixel locations in the image memory 402 to the processor unit 401, which is composed of n x n processing elements for each color, in which the data is processed at high speed and then returned to image memory 402 . The structure of the processor unit 401 for the respective color is shown in detail in FIG. 62. Each processor unit consists of n × n, such as. B. 4 × 4 processor elements, of which adjacent processor elements are connected to each other in connection, while processor elements in the same places with respect to the processor units can also come into connection with each other. The principle of operation will now be described.

color conversion

Processing for color conversion is now considered. The color conversion is a processing in which the color information is converted into another predetermined special color information on image data with color information. According to the flowchart shown in FIG. 23 and already described, the processor elements of the processor unit carry out the color conversion in parallel for 16 picture elements, the processor elements for R, G and B located in the same places in each case exchanging information.

The processing operations between a respective memory and the processor unit will now be described in detail with reference to FIGS. 61 and 62.

First, the color information is set before and after a change, and the information is stored in a storage location such as a register for storing a value. Thereafter, corresponding control signals 411 from a control unit 410 shown in FIG. 62 each corresponding image data from 4 × 4 memory elements of the image memory for the three colors R, G and B are read out simultaneously and to corresponding processor elements 417 , 416 and 415 of processor units 412 R , 412 G and 412 B for red, green and blue. Thereafter, according to the flowchart in FIG. 23, the 4 × 4 processor elements execute the processing in parallel, the processor elements for R, G and B being connected to one another at the same points, namely the processor elements 415 , 416 and 417 . When processing by the processor units is complete, the image data is returned to the image memory. Then the image data are read out from the next 4 × 4 storage elements. It is sufficient to carry out the processing described above for the image data for one page. The selected color or the selected colors can be one color value or three color values from the colors R, G and B, wherein a range can of course be determined for the color information before the change, or a plurality of color information can be selected.

color correction

Processing for color correction is now considered. The color correction is a processing in which if Image data contain a certain color information, the color information according to the characteristics of the unit for the image input or output is corrected.

This processing can generally be expressed by the following equations:

R '= α.R + β.G + γ.B

G '= α'.R + β'.G + γ'.B

B "= α" .R + β ".G + γ" .B (20)

where R, G and B are the input image data, R ', G' and B ' the output image data is and α, β,. , ., β ", γ" coefficients are.

As coefficients α, β,. , ., β ", γ" in equation (20), numerical values are used which correspond to the properties of the image input unit or image output unit. According to the flow chart in Fig. 63, the processing executed by the processing elements in the processor units in parallel for 16 picture elements, takes place an exchange of information between the corresponding picture elements of the same processor elements for R, G and B.

This processing will now be described in detail. First, as coefficients α, β,. , , in the equation (20) determines numerical values corresponding to the image input and output units, such as α = 0.8, β = 0.3 and γ = 0.2; these coefficients are stored in storage locations such as registers for holding the values. Thereafter, according to the control signals 411 output from the control unit 410 of FIG. 62, the 4 × 4 processor elements carry out the processing in the manner described below.

Upon addressing by the control signal 411 , the 4 × 4 memory elements are called up, the corresponding image data for the three colors R, G and B are simultaneously read out of the image memory by means of a device (not shown) and the image data are simultaneously transferred into the assigned processor elements transfer respective processor unit. Thereafter, according to the flowchart in FIG. 63, the 4 × 4 processor elements carry out the processing in parallel, the processor elements for R, G and B located in the same places, such as processor elements 415 , 416 and 417 , being in data communication with one another. When this processing carried out by the processor units is finished, the processed image data is returned to the image memory. It suffices to carry out the above-described processing on one page of image data.

While processing according to the prior art for a every single output pixel is repeated the processing in the described embodiment results for a variety of output pixels in the same cycle, so that a very high color image Processing speed can be achieved.

By simultaneous input of related,  closely adjacent picture elements can be the location frequency filtering can be carried out in one cycle, so that simultaneously the results of the spatial frequency filtering to a A large number of output picture elements can be output.

By simultaneously retrieving and processing a lot Number of input data is compared to the single call of the data at a particular point in time speed increased. In addition, a single Retrieval of input data through a data exchange between processing units are carried out, where the mutual connection between at the same time retrieved data is to be considered, such as spatial or spatial frequency filtering, color processing and the same.

From each m × n, e.g. B. 4 × 4 memory block will be by the entered color information (e.g. R, G and B) expressed Raw data of the original image sequentially and for the three colors R, G and B accessed simultaneously. Therefore can instead of repeatedly calling up each picture elements from the input image memory in each case the same early image data for m × n image elements for the three colors be retrieved. This enables image data transmission at high speed.

In addition, there is the processor elements in the Pro processor units not only an information connection between elements for the same color, but also between elements for different colors. Consequently the color information for the three colors R, G and B are processed simultaneously, so that processing for Color conversion, color correction and the like with high Ge speed can be executed. Furthermore, since the Prozes sensor units composed of processor elements in a number  are equal to the number m × n of picture elements in the input-side and output-side memory blocks , m × n image data can be stored simultaneously in block units can be entered and output. Furthermore, the m × n Processor elements also parallel processing for Calculations so that a satisfactorily high processing speed is reached.

Motion processing in the second embodiment

A case will now be described in which, when addresses are assigned according to FIGS. 16 and 17, an offset of the type shown in FIG. 65 is carried out.

In k × ℓ memory elements 1 b, when a single address is created, data for corresponding locations in one item are read out from each of k × ℓ subareas at a time. When all the k × ℓ data has been rearranged by the processor unit 2 and written into the same address, a single processing step for transmission between the k × ℓ areas is completed. If the processor unit 2 executes this process with regard to all addresses of the memory elements 1 b, the processing of the entire image is thus completed.

However, the processor unit 2 must return the data to the k × ℓ storage elements 1 b. In fact, however, the load on the processor unit 2 is relieved if the processor unit 2 only accepts a number of areas in a region A and outputs only the number of regions in a region B. The number of areas in area A and area B need not necessarily be the same. For example, it is possible that the area A contains 3 × 3 areas on which the processor unit 2 performs a reduction or reduction to 2/3, after which the results are transferred to area B, which consists of 2 × 2 areas ,

Therefore, in the event that reading and writing is not always required on all memory elements 1 b, it is sufficient to control the block release of all memory elements 1 b using an arrangement according to FIG. 15, namely to mask those memory elements into which no data should be written. In this case, the information relating to the longitudinal and transverse formats of areas A and B and the locations of these areas is entered as data on the aisle in two look-up tables.

An image processing device contains an image memory from a variety of memory elements and a processor unit made up of a multitude of processor elements. By appropriate design of the arrangement of the image memory from the Memory elements, the arrangement of the processor unit from the Processor elements and the connections between the Spei cherelemente and the processor elements, it is possible with simple structure to achieve fast image processing, like a density conversion, a color conversion, a masking, spatial frequency filtering, image enlargement, image downsizing, image rotation, image compression, one Image expansion and color correction. It will be one too Image processing device for color images with a lot number of image memories and a variety of processors units as well as a generally applicable, multifunctional Processing device for parallel processing of a large amount of data written at high speed.

Claims (5)

1. Image processing device for processing an image element in question using image elements adjacent to the image element in question
a processor device with a multiplicity of processor elements, each of which processes each divided area of the image obtained by two-dimensional division of an image,
wherein the plurality of processor elements access pixel data in an area overlapping in two-dimensional directions under the control of an address and memory selection to process candidate pixels in a border portion of adjacent divided areas using the pixel data that are overlapped accessed. 2. The image processing apparatus according to claim 1, wherein the Processor device a spatial filter processing of the image performs. 3. The image processing apparatus according to claim 1, wherein the Processor device a density conversion of the image performs.   4. The image processing apparatus according to claim 1, wherein the Processor device a color conversion of the image performs. 5. The image processing apparatus according to claim 1, wherein the Processor means masking the image performs.