JPS63201782A - Picture processing device - Google Patents

Abstract

PURPOSE:To quickly process picture data in parallel by simultaneously processing picture data of respective picture memories of a first picture memory group where picture data having plural picture information is stored in each picture element, by respective processor units and storing processing results in a corresponding second picture memory. CONSTITUTION:The first picture memory group which has plural first picture memories correspondingly to classifications of input picture information and a processor unit group which has plural processor units, which simultaneously process plural picture elements in picture memories, correspondingly to first picture memories are provided. A second picture memory group is provided which has plural second picture memories, which correspond to respective processor units and consist of plural memory elements which are accessed by addressing independently of another memory, correspondingly to classifications of output picture information. Thus, picture data consisting of plural sets of data is quickly processed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and particularly to an image processing device that performs high-speed processing and parallel processing of image data using an image memory control technique.

[Prior Art] Generally, when processing images at high speed, software is used as the computer processing method.
As the amount of image data increases, speeding up becomes necessary. There are two methods for speeding up processing: one is a method using sequential processing hardware called the pipeline method, and the other is a 5+1 processing method that uses multiple processors. . The former has a limit because the processing clock frequency increases as image data is processed at high speed. On the other hand, in the latter case, speedup can be increased as much as possible by increasing the number of processors placed in parallel.

In extreme terms, it is one of the technologies that is currently attracting attention because it is possible to obtain maximum speed by placing as many processors as there are pixels.

By the way, at this time, communication processing between each pixel becomes important, and it is necessary to proceed with processing while performing mutual communication. In such a parallel processing method, it is impossible to have as many processors as each pixel when handling high-resolution data. For example, when handling an image read on A4 paper at 16 pixels/mm (pet), the number of pixels is approximately 16M pixels (pl
xels), and it is impossible to have this many processors at the same time.

[Problems to be Solved by the Invention] The present invention provides an image processing device that processes multiple sets of image data in parallel at high speed.

[Means for Solving the Problem] As a means for solving this problem, the image processing device of the present invention has a plurality of image processing devices that can be accessed by specifying addresses independently from other devices. a first image memory group having a plurality of first image memories each comprising a memory element corresponding to the type of input image information; and a plurality of processors corresponding to the memory element.
a processor unit group comprising a plurality of processor units corresponding to the first image memory and which simultaneously process a plurality of pixels in the image memory; and another memory corresponding to the processor unit; and a second image memory group having a plurality of second image memories each including a plurality of memory elements that can be accessed by specifying an address independently, corresponding to the types of output image information.

In addition, a first memory element consisting of a plurality of memory elements that can be accessed by specifying an address independently of other memories.
a first image memory group having a plurality of image memories corresponding to types of input image information; and a plurality of processors corresponding to the memory elements.
a processor unit group comprising a plurality of processor units corresponding to the first image memory and which simultaneously process a plurality of pixels in the image memory; and another memory corresponding to the processor unit; a second image memory group having a plurality of second image memories each consisting of a plurality of memory elements that can be accessed by specifying an address independently of the second image memory according to the type of output image information; and control means for controlling transmission and reception of image data between a plurality of corresponding processor elements.

[Operation] In such a configuration, the image data of each image memory of the first image memory group, in which each pixel stores image data having a plurality of pieces of image information, is simultaneously processed by the respective processor units to correspond to the image data. The processing results are stored in the second image memory.

Further, the control means simultaneously performs processing related to a plurality of image data corresponding to the same pixel.

Margin below [Example] An embodiment of the present invention will be described below.

The configuration of the image processing apparatus on the Kinomi style side consists of an image memory 1 for one page, a processor unit 2, and peripheral parts 3 such as input/output devices. FIG. 1 shows the basic configuration of only the basic part, in which an image memory 1 is connected to a processor unit 2. Nxm image data at an arbitrary position on the image memory 1 is transferred to a processor unit 2 constituted by an array of nxm processor elements 2a,
After being processed at high speed, it is returned to the image memory 1 again. n
This is a so-called parallel processing architecture in which each process within the array of xm processor elements 2a is performed simultaneously. Further, other configurations are shown in FIGS. 9(a) and 9(b). In FIG. 9(a), according to the control of the control circuit 94, image data from the input side image memory is transferred to a processor unit 92 consisting of a plurality of processor elements.
A plurality of pixels are subjected to predetermined processing in parallel and stored in the output side image memory 93. On the other hand, in FIG. 9(b), an image memory 91 or 93, a processor unit 92, an input device 96, and an output device are connected by a common bus.

The image memory 1 will be explained in detail below.

Now, for simplicity, set the image size to 1024 x 102.
We proceed with an image memory having 4 pixels, each with 8 bits/pixel data. To change the image size, it is only necessary to extend the architecture of this embodiment. Further, it is assumed that the processor unit 2 is composed of a total of 16 processor elements 2a (4×4).

FIG. 2 is a diagram showing the configuration of the image memory 1.

Assuming that the image structure is made up of 1024 x 1024 pixels as shown in the figure, dividing this into 4 x 4 units results in a total of 256 x 256 pixels, 64 K (=65
536 ) blocks. Now, this is the third
As shown in the figure, it is reorganized in units of 4 x 4 pixels, and 4 x 4 pixels = 64 pixels.
(each pixel has 8 bits of data). Therefore, the memory address space is 4X4X64
Three-dimensional addressing is possible.

Assuming that one memory chip can support one 64 pixel in a 4.times.4, a memory chip is required in which each address is 8 bits deep in the 64 address space. This requires a memory chip with a capacity of 512 bits (-64 bytes), but in this embodiment, a combination of two dynamic RAMs (D-RAMs) with a capacity of 256 bits is used. That is, 6 out of 256 bits D-RAM
Two pieces of 4 x 4 bit configuration are used as 64K x 8 bits. These two memory chips will be referred to as memory element 1a from now on.

The image memory 1 is composed of 16 memory elements 1a corresponding to a 4×4 matrix. Fourth
The figure shows the configuration of such a 4×4 memory element 1a. Each memory element 1a is designated with a row address and a column address, and one pixel of 4×4 pixels is designated as 6
Image data in the address space of 4 is input/output. A row address generator 4 and a column address generator 5 provide a hairtress for each 4×4 memory element 1a. Note that memory element 1a is D-R.
If AM is used to time-share and provide row addresses and column addresses, only one address generator is required. At this time, time-division switching control of row addresses and column addresses is required.

By giving each address from such an address generator, a memory element 1 of 4×4 pixels is created.
It becomes possible to read/write a. That is, by specifying the address - times, image data for 4×4 pixels can be driven simultaneously. Therefore, as a data line,
It is assumed that an 8-bit data line comes out directly from each memory element 1a.

Now, suppose that data with a row address of A (0≦A≦255) and a column address of B (0≦B≦255) is read from the image memory 1, then the image data (A , B), 8-bit long image data of 4×4 pixels is read out.

Furthermore, simultaneous access of a plurality of pixels will be generalized and explained.

Figure 10 shows one page of the image as it is, and this image data is shown in the diagram as follows:
It is divided into blocks of one pixel and made to correspond to the kx communication memory element 1a as shown in FIG. Also, the blocks of kxKL pixels are (0,0), (0,1), (0,
2).

(0, 3)... and k as shown in Figure 12.
It corresponds to a memory unit 1 consisting of Xu memory elements 1a. FIG. 13 is a two-dimensional representation of the memory unit 1. Furthermore, since the memory size to be accessed is in block size units of kxJJ pixels, even if a block R of kx pixels at an arbitrary position is accessed, all kxu memory elements 1a will be accessed, and one memory element will be accessed. One address is accessed for each 1a.

In this way, the image data of a plurality of kXu pixels adjacent to each other at any position in the image is accessed at once, read, and then processed by the processor unit 2. The image data processed by processor unit 2 is sent back to 'xJL.
'It has a pixel block size and can be accessed and written to any location. Here, k' =, l' −
This will be explained in the future as part 4.

To provide a supplementary explanation of the above-mentioned memory access for only 'X cross' pixels, if the processing in the processor unit 2 is spatial filtering etc., the block size kXu to be accessed by the writing side is larger than the block size kXu to be accessed by the reading side. Size may be smaller. Generally speaking, the block size on the writing side is 1×
There are many processes where the value becomes 1. Also, when the processing in the processor unit 2 is image reduction processing, the block size accessed on the write side is smaller than the block size kxu accessed on the read side.

Generally, when the block size on the light side is '
The smallest integer that satisfies β or is ', l'. If the reading and writing memories are the same or have the same k×vertical memory configuration, and the above two examples are performed, the configuration size k of memory unit 1 on the writing side
We must write to 'xl' to a size smaller than Xlu. In this case, instead of accessing all kxJl memory elements 1a, the memory elements 1a that do not correspond to writing must be masked to prevent them from being accessed. However, the image memory 1, which is composed of kx text communication memory elements 1a, can access and read out data at a maximum of kXu pieces of adjacent image data at one time; The image data of ' can also be freely accessed by performing the masking described above. It is easily possible to mask and access only '×l' pieces at the same time by manipulating the chip enable of the memory element 1a.

Next, examples of memory access of a predetermined pixel at an arbitrary position will be explained in a case where the memory unit configuration is 4x4 and a case where the memory unit is kxJl, and the chip enable control for masking will also be explained. explain.

First, an example will be shown in which the block size kXJJ is 4X4.

FIG. 5 shows an enlarged view of a portion of FIG. 2.

A process will be described in which image data of an arbitrary 4×4 block S in the image memory 1 is read out, processed by the processor unit 2, and then transferred to an arbitrary 4×4 block T.

The 4x4 squares in Figures 5 and 6 are 4x4 16
This is a diagonal that separates memory elements 1a. If these 116 memory elements Ia are Aa, Ab
, ..., Ba, Bb, -Ca, -=Dc, Dd. First, when reading a 4×4 block S, among the 16 memory elements 1a, the memory
Element Dd has (row address, column address)
(N, M) is given as Memory element D
(N, N+1) for memory elements Ad, Bd, and Cd, and (N+1.M) for the remaining memory elements Ad, Bd, and Cd.
The element is given (N+1.N+1). This is the row address generator 4 mentioned above. Generated by column address generator 5. Furthermore, once the position of the end point U of the 4×4 block S is determined, divide its horizontal and vertical position addresses by 4 and find the remainder n.

It is clear that the row address and column address allocated to memory element AaNDd are uniquely determined by m. Suppose the position address of U (Y, X)
Then, Y=4N+n (n=o, 1.2.3)X-4M+m
(m=o, 1, 2.3) For example, M in address generator 4.5.

A configuration may also be considered in which information on N and information on m and n are input into a look-up table or the like, and an address given to memory element A a ND d is output. At this time, the outputs are M, N, N+1. It is clear from the above explanation that it is any one of N+1.

Also, using this property, as shown in Figure 7, input n or m into the lookup table and change C1 according to this value.
, 1 and control whether or not to increment the address N or M given to the memory elements A a - D d.

The row address generator 4 uses n and N, and the column address generator 5 uses m and M.

In this way, addresses are given to the 4×4 16 memory elements by the address generators 4 and 5 as described above, and 16 pieces of data can be obtained at the same time.

These 16 pieces of data are transferred to the 4×4 block T shown in FIG. 5 again in the processor unit 2, with some processing or no processing at all. However, 16 memory elements A a -D
Each image data read from d is not necessarily transferred to the same memory element A a -D d. The 4x4 memory block S in Figure 5 is 4x4
, the data read from memory element Aa of 4×4 memory block S must be transferred to memory element DC.

Then, the 4×4 memory blocks S, T are at their end points u, v
has arbitrary positions (Y, X), (Y', I will explain if it is possible.

As shown in Figure 5, Y = 4N+n (n=o, 1, 2.3)X = 4
M+m (m=0.1, 2.3)Y' =4P+p (
p=o, 1,2,3)X'=4Q+q (q=0.1.
2.3), then p-n=4y' +y (y'=-1,.

y=o, 1, 2.3) ...■ q-m=4x' +x (x'=-1, 0x=0.1
, 2.3) ...■ Find x and y.

First, the row array A consisting of (Aa, Ab, Ac, Ad) is rotated X times in the right direction. This is named row array A'. Similarly, row arrays B, C, and D rotated X times in the right direction are named row arrays B', C', and D'.

Next, the array (ABCD)' consisting of row arrays A', B', C', and D' is rotated downward seven times.

In the case of FIG. 5, n, m, p according to FIG.

It is clear that q is 3, 3, 2.1, so ■, ■formula%formula% obtain. Therefore, from the above explanation, we obtain the following matrix.

Rotating to the right twice, we get row array A' = (Ac, Ad, Aa, Ab) B' = (
Bc, Bd, Ba, Bb) C' = (Cc, Cd,
Ca, Cb) D' = (DC, Dd, Da, Db
) When rotated downward three times, (Be, Bd, Ba, Bb) (Cc, Cd, Ca, Cb) (DC, Dd, Da, Db) (Ac, Ad, Aa, Ab) ...■This Procession ■
Comparing this with the basic array ■ below, Aa, Ab, Ac, Ad Ba, Bb, Be, Bd Ca, Cb, Cc, Cd Da, Db, DC9Dd... - Basic array 04 Basic array ■ is simply a two-dimensional array of read data from memory elements Aa-Dd arranged from left to right and top to bottom, and matrix ■ is a two-dimensional array of read data from memory elements Aa-Dd.
This corresponds to a two-dimensional array of data to be written in Dd. That is, as an example, when looking at the array {circle around (2)}, the data read from the mesh element Aa is written to the fourth row and third column. When this is referred to the basic array (2), DC is located in the 4th row and 3rd column, so it can be seen that the read data of the memory element Aa should be written to the memory element Dc.

As a supplementary explanation, memory niremen 1-Aa on Figure 5
It is easy to notice that it is sufficient if the read data is written to the position Dc, but the displacement from the position Aa to the position Dc is equal to the displacement from the position address U to the position ■. Also, since the configuration of the memory element 1a is 4×4, the horizontal direction
The remainder when both vertical positions are divided by 4 can be considered to be the displacements x and y of the memory element. For example, if the displacements of u and v are multiples of 4, the displacements x and y will be 0, and data read from a certain memory element will be written to the same memory element after processing. .

The hardware implementation of the above processing will be briefly explained.

FIG. 8 shows that data simultaneously read out from a memory element 1o consisting of 16 4×4 memory elements 1a is processed by the processor unit 2, and the data is stored in X-displacement raw data 81 by 4 elements each. Perform rotation for X number of times. After that, rotation is performed by the number of y based on the y displacement raw data 82,
Aa~Ad, Ba-Bd, Ca~Cd, Da respectively
~Dd is configured to write to memory element 1a.

Note that the y-displacement raw data 82 has four input elements each, so the y-displacement raw data 82 is exactly the same as the X-displacement raw data 81.
Needless to say, it can be composed of It goes without saying that the raw data may have a depth of the same number of bits as the depth of the memory data, or that the same number of 1-bit depths as the depth of the memory data may be used. Furthermore, it can be easily inferred that a shift register, barrel shifter, etc. can be used for raw data.

Further - if you think about it in defeat, you can change the memory block to kx
If the size is u, the configuration of the memory unit 10 will also be kx-cross. In this case, k at any position
After the memory block S of xJJ is processed by the processor unit 2, the memory block T of the kx statement at an arbitrary position is processed by the processor unit 2.
When transferring to Y=kN+n (m=o, 1.-, k-1)
X=uM+m (m=o, 1, -, Q -1
) (N, M, P, Q are 0, 1, 2.3...) Y'=k
P+p (0.1..., k-1 for p)x'
=suQ+q (q=0. 1. ..., q-1)
However, the position address of the end point of S is (Y, X), the position address of the end point of T is (Y', , y′+y (V ′−1,0,V −0,1,2,3,...,−1)q−m−sentence x′+x (x′−−1,0,x − 0, 1, 2, 3,...
u-1)...(11) Processing may be performed using x and y such as, for example, the X displacement position data 81 and the y displacement raw data 82 as shown in FIG. In this case, the X displacement raw data 81 has human power for communication and can be shifted from 0 to sentence-1. The y displacement raw data 82 has k inputs and can be shifted from 0 to -1. Moreover, since each of the inputs of the y displacement raw data 82 has two elements, the raw data of one input element constitutes communication.

As shown in FIG. 10, the access control of memory elements for simultaneous access of blocks of ``x statements'' described above will be explained.

Let the position address of the end point i of the block k'xJ1- be (f
, g). Y when reading the memory accessed according to the above equation (10).

When assigning flg to X and writing to the memory to be accessed, assign f and g to Y' and X'.

By substituting the result into equation (11) to obtain y and x, the embodiments shown in FIGS. 7 and 8 can be applied as is to the kXU.

Also, at this time, among the memory elements of the kx statement, only the memory element of 'xJJ' is made chip-enabled. This enable chip is 'xJJ'
Once the location address of (f, g) of end point i of It is decided.

By the way, as explained above, in a memory configuration consisting of kxJJ memory elements, when simultaneously accessing 'xJJ' blocks on the read access side and simultaneously accessing k"xJJ" blocks on the write side ( However, it is possible that 0≦k''≦ and O≦dan''≦, but this is also the same as the explanation up to now. FIG. 14 shows an example of chip enable control applied to the memory elements in this case.

When the positional addresses of the end points of the block of k'xJl', k''×su°° are (y, x), (y', x'), the formula (
10), n, m, p, and q are found. These n, m, p, and q are input into the data input of the selector. Further, a read/write signal R/W for memory access is inputted as a selection control signal of the selector, and n and m are selectively output when reading, and p and q are selectively output when writing.

Similarly block sizes k', i' and k''.

The output signal is also input to the selector, and the R/W signal is input manually as a selection control signal. When reading, k'' and father' are selected and output, and when writing, k'' is output.

The cross paths are selectively output. By the way, the memory elements to be accessed are 'n' and 'm' on the read side.

It is clear that if the intersection ′, k”, dan”, p, and q on the right side are determined, they are uniquely determined, so these data output from the selector are input to the lookup table, and the values of kx and fi are respectively determined. Outputs a signal to control the memory to be accessed among the memory elements.

By the way, if the image memories 1 before and after processing by the processor unit 2 are separate memories, and their memory configurations are kxJlj and KxL, respectively, if two lookup tables are used as shown in FIG. Good things can be easily inferred. In this case lookup table 151
The lookup table 152 becomes a table with different contents.

Further, there is no problem at all even if k= and u=L. With the configuration described above, it is possible to mask some of the memory elements to be accessed without having to access all of the kxu memory elements. Therefore, the configuration of the memory element for kx days may be set to the maximum required size of kXJl.

Next, a description will be given of how to access the memory elements and process all the image data corresponding to the entire previous screen, that is, how to scan the access of all the memory data.

For example, the end point U of the block of adjacent kxu to be accessed
When Y and x are determined, the position address is Y, which is the number counted from 0 in the vertical direction, and X is the number counted from 0 in the horizontal direction. We have already explained how to access the memory. That is this X.

An example will be described in which order Y is scanned and all images are processed.

(First example) In order to access the memory element kXJl, the image data position addresses Y and X are scanned by increasing or decreasing them by integer multiples of U. For example, first, Y and X are set to O. , X is sequentially increased by sentences. After increasing X to the end point in the horizontal direction, next set X back to 0,
Increase Y by , and then increase X by dan. This is repeated sequentially to scan the entire screen or a part of the screen. This will be tentatively named the first sequential scanning method.

(Second example) Also, instead of increasing and decreasing X and Y sequentially as described above, the values of kx and Q are continuous here and there on the entire image screen.
This is tentatively named the first random scan method when the blocks of are accessed at intervals, and when the displacement in X and Y at the time of access is an integral multiple of A.

(Third example) A method of scanning by increasing/decreasing the image data position addresses Y and X by integers to access the memory element of kxu. For example, first set Y and X to O, and then sequentially set X to 1. Increase by increments. X to end point in horizontal direction
After increasing , set X to 0 again, increase Y by 1, and then increase X by 1. This is repeated sequentially to scan the entire screen or a part of the screen. This is tentatively named the second sequential scanning method. In this case, the same memory data is accessed many times.

(Fourth example) Also, instead of increasing and decreasing X and Y sequentially as described above, blocks of kXKL here and there on the entire image screen are accessed one after another, and this is executed for all X and Y. Or X of all consecutive parts of the entire screen
, executed for Y. When it is random, we tentatively name it the second random scan method.

(Fifth example) In a memory configuration having memory elements for kx statements, when the memory block to be accessed is ] ,
9. The first method is to scan the entire screen by sequentially increasing or decreasing the number by an integer multiple of ′.
It is called the blockwise sequential scan method to distinguish it from the sequential scan method.

(6th example) Also, instead of increasing and decreasing X and Y sequentially like in (5th example), you can increase or decrease
``x, Q'' blocks are accessed intermittently, and the Y
, X is a displacement that is an integer multiple of k''xJJ', this is tentatively named a blockwise random scan method.

(Seventh example) Regardless of the memory configuration of kxJJ of memory elements, a device that scans sequentially, for example, a device that scans by changing X and Y every arbitrary number d', f', is simply a sequential scan method. It is called.

(8th example) When scanning randomly in (7th example) or (4th example)
Even in this case, if memory access is not performed for all combinations of x and Y, it is simply called a random scan method.

As mentioned above, there are many scanning methods that can be considered, but in addition to these, there is also a read-side memory access, and there are two types of memory access: read-side memory access scan methods and write-side memory access scan methods. It doesn't necessarily match.

Furthermore, in this scanning method, once the read side is determined, X' and Y' to be accessed on the write side are determined by the processing content of the processor unit 2. Alternatively, the scanning method on the write side may be determined first.゛In this case, the scan on the read side is determined by the processing content.

Furthermore, the block sizes ', u= to be accessed on the read side and the write side may be different, and the sizes of the memory element configurations kxJJ may be different.

The embodiment of the present invention has the above memory configuration in a deeper direction, for example, has R, G, B, Y, M, C, etc. memories at the same time, and the processor unit 2 has a deeper memory structure as described later. An example of having a certain PE in the depth direction will be described later. In this case as well, the above-described memory access method remains the same, and the depth of the memory element only needs to be increased, for example, by three times. In other words, if the three memory elements described so far are combined into one memory element, it is clear that no additional explanation is required regarding the memory configuration and access described above.

Image processing for digital color images will be explained. The color information of a digital color image is expressed, for example, by a combination of R, G, and B, and the image memory is
This information is stored as information having a depth of 8 bits for each color. In addition, in order to process the color information held as described above at high speed, one corresponding processor element corresponds to each corresponding R, G, and B image memory cell. Processing for R and processing for G, respectively.

It is configured so that processing for B can be processed in parallel and information can be communicated between the respective processor elements. Image memory for one page at this time and nxn
The configuration of a processor unit (for example, 4×4) is shown in FIG.

Figure 18 shows the principle configuration of only the basic part.
An RlG, B processor unit is connected to the R, G, B image memory 302. R, G, and B image data of nxn each corresponding to an arbitrary pixel position on the image memory 302 is transferred to the processor unit 301 composed of nxn processor elements for each color, processed at high speed, and then processed again. The image is returned to the image memory 302. Details of the processor unit 301 for each color.

A configuration diagram is shown in FIG. 19. Each processor unit is composed of nxn (for example, 4x4) processor elements, and adjacent processor elements can communicate data with each other, and processor elements of each color are located at the same location within each processor unit. are also configured to be able to communicate with each other. The operating principle will be explained below.

Example 1 Let's consider color conversion processing. Color conversion is a process of converting, when image data has certain color information, that color information into predetermined specific other color information. In this process, for example, each processor element in the processor unit processes 16 pixels while R9G and B processor elements located at the same position mutually communicate information according to the flowchart shown in FIG. All you have to do is process it in parallel.

The processing at this time will be explained in detail.

First, specify the color information before and after the change, and register it in a place such as a register that can hold the value. Then, according to the control signal 311 output from the control unit 310 shown in FIG. - Read the corresponding image data for RlG, B, three colors simultaneously from the element, and transfer the image data to the corresponding processor element of each R, G, B processor unit. Thereafter, according to the flowchart shown in FIG. 24, the 4×4 processor elements mutually communicate in parallel with the R, G, and B processor elements located at the same position, for example, 315, 316, and 317 processor elements. Process while doing so. When the processing in the processor unit is completed, the image data is returned to the image memory. Read image data from the next 4x4 memory element. The above processing may be performed for one page of image memory. In addition, the specified color is R
, G, B, the value of one color among the three colors may be used, or the value of three colors may be used, and the color information before change may be a range specification.
Of course, there may be more than one.

Example 2> Consider the case of color correction processing. Color correction is a process in which when image data has certain color information, the color information is corrected in accordance with the characteristics of the image processing device or image output device so that the resulting image faithfully reproduces the input image.

For example, this process is as follows: R'=α・R+β・G+γ・B G'=α′・R+β′・G+γ′・B
0) (R, G, B are input image data, R', G'.

B' is output image data, α, β, . . . β″.

γ″ is a coefficient). This (10
), substitute values that match the characteristics of the image input or output device to the coefficients α, β, ... β″, γ″, and then
Each processor element in the unit processes R, G corresponding to the same pixel according to the flowchart shown in FIG.
, B can process 16 pixels in parallel while communicating information with each other.

Let's explain the process at this time in detail. First, set the coefficients α, β, etc. in equation (10) to values that match the image input/output device.
For example, α=0.8. After determining β=0.3° and γ=0.2 and registering these coefficients in a place such as a register where values can be held, the 4×4 Each of the processor elements performs the following processing.

Based on the address given by the control signal 311, a 4×4 memory element is referenced from the image memory, and the corresponding image data is transferred to R, G, B by a device (not shown).
, three colors are read out simultaneously, and the image data is simultaneously transferred to the corresponding processor elements of each R, G, and B processor unit. Thereafter, according to the flowchart shown in FIG. 21, the 4×4 processor elements are arranged in parallel, and the R, G, and B processor elements located at the same position, for example, the processor elements at 315, 316, and 317, are mutually connected. Processing is performed while communicating data, etc. When the processing in the processor unit is finished,
4×4 pieces of processed image data are returned to the image memory at the same time.

FIG. 26 shows this data exchange. The above processing may be performed for one page of image data.

As explained above, since the processing that was conventionally repeated for each output pixel is outputted for a plurality of output pixels in the same cycle, extremely high-speed processing becomes possible.

Another advantage is that spatial filter calculations can be executed in one cycle by manually processing consecutive neighboring pixels on the input side, and spatial filter calculations can be output simultaneously for multiple output pixels. be.

In addition, by accessing and processing multiple pieces of input data at the same time, processing execution speed is not only faster than accessing data one by one, but also by sending and receiving data between each PE, data can be accessed simultaneously. Calculations (spatial filter calculations, color processing, etc.) that also take into account the correlation between
It also has the advantage that it can be executed with only one input data access.

In addition, the raw data of the original image represented by the input color information (for example, R, G, B) is sequentially accessed for each mxn (for example, 4x4) memory block for three colors, R, G, and B at the same time. Each pixel in the image memory at the input end cannot be accessed multiple times, and image data of m×n pixels can be accessed for three colors at the same time, so image data can be transferred at high speed.

In addition, each processor element in the processor unit, which is the calculation section, can communicate information not only with the same color (white) but also with processor elements for different colors. It is possible to process color information simultaneously, and it is possible to perform processes such as color conversion and color correction at high speed. Furthermore, since the processor unit is composed of the same number of processor elements as the number of pixels (mxn) in the memory blocks on the input and output sides, mxn image data can be input and output simultaneously in block units, and calculations can be performed on mxn pieces. Since the processor elements operate in parallel, sufficiently fast processing speed can be achieved.

[Second Example] Second example of allocating image data to kx1 memory elements for accessing kXu data simultaneously
An example will be described.

FIG. 16 is a diagram showing a state in which the upper part of one image screen is replaced with data, and this is divided into equal parts in the horizontal direction and divided into equal parts in the vertical direction. To explain the area divided into kxA at this time, (ci, o), (o, 1),...
・(01 statement), . . . , (k1 statement), each area is allocated to each memory element as shown in FIG. For allocation, the dashed diagonal area shown in Figure 16 is allocated to 0 of each memory element.
address, then allocate the adjacent image data to address 1 of each memory element, and similarly
After all lines have been allocated, the second line is similarly allocated from left to right, and all image data is allocated. Then, for all kXU memory elements, the row address generator 4 shown in FIG.
When the addresses given by the column address generator 5 and the column address generator 5 are all the same, discrete pieces of image data can be accessed at once, as shown in the shaded area in FIG.

By adopting such a configuration, it is possible to designate a certain address, read the image memory 1, and after processing in the processor unit 2, change the address when writing to the kXu memory elements 1a. There is a possibility that data can be written without any errors. For example, as shown in FIG. 16, when the area is composed of KXL pixel data, one part of one image screen is displaced by an integral multiple of L in the horizontal direction and an integral multiple of K in the vertical direction. When performing processing such as movement or transfer, the read address and write address may be the same. For this purpose, the row address generator 4
．． The load on address control such as the column address generator 5 is extremely reduced.

This movement and transfer processing is processed by the processor unit 2. The processor unit 2 is inputted with kx, one piece of image data, and image data covering the entire screen, as shown by dashed diagonal lines in FIG. Since the displacement is an integer multiple of , k in processor unit 2 is
It is sufficient to exchange and move the x-text communication data, and sequentially process all addresses of the memory element starting from 0. As a result, processing can be performed on the entire screen.

In this embodiment, the memory configuration of kX1 is, for example, IXfl,
kxl etc., one horizontal line in one image screen,
Alternatively, by allocating one vertical line to each memory unit, processing in processor unit 2 can be performed on image 1.
It can be inferred that it can be applied to various image processing such as line histogram calculations and -dimensional Fourier transformation. Furthermore, when a plurality of pixels are accessed simultaneously, there is no limitation as to which memory element and which address the data in one screen of images is allocated to.

[Effect of the Invention J] The present invention provides an image processing device that processes image data consisting of multiple sets of data in parallel at high speed.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of the image processing device of this embodiment, Fig. 2 is a diagram showing how one screen of images corresponds to the address of a memory element, and Fig. 3 is a diagram showing a memory consisting of 4 x 4 memory elements. Figure 4 is a diagram showing the entire memory and the address generator given to it. Figure 5 is a diagram showing a part of the image. Figure 6 is a diagram showing the memory allocation for a part of the image. Figure 7 is a diagram of the memory address. A diagram showing the control circuit, FIG. 8 is a block diagram of pixel data control, FIGS. 9(a) and (b) are diagrams showing the configuration of another image processing device of this embodiment, and FIG. 10 is a single image screen. FIG. 11 is a diagram showing kXu memory elements. FIGS. 12 and 13 are diagrams showing one memory element. FIGS. 14 and 15 are diagrams showing control of memory element access. FIG. 16 is a diagram showing one image screen; FIG. 17 is a diagram showing kX data example memory elements; FIG. 18 is a diagram showing the relationship between the image memory and processor unit in this embodiment; Figure 19 is a detailed configuration diagram of the processor unit in this embodiment, Figure 20 is a flowchart of color conversion processing in this embodiment, Figure 21 is a flowchart of color correction processing in this embodiment, and Figure 22. FIG. 2 is a diagram showing data exchange during color correction. In the figure, 1...image memory, Ia, lb...memory
Element, 2... Processor unit, 2a...
・Processor element, 3... Peripheral part, 4...
Row address generator, 5... Column address generator, 91... Input side image memory, 92.
...Processor unit, 93...Output side image memory, 94...Control circuit, 95...Input device, 96...
... Output device, 301 ... Processor unit, 3
02... Image memory, 310... Control unit, 311.
...Control signal, 312...R processor unit, 313...G processor unit, 314...
- Processor units for B, 315 to 317...processor elements. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 22 Figure 20 Figure 21

Claims (8)

[Claims] (1) A first image memory having a plurality of first image memories each consisting of a plurality of memory elements that can be accessed by specifying an address independently of other memories, corresponding to the type of input image information. a plurality of processors corresponding to the memory elements;
a processor unit group comprising a plurality of processor units corresponding to the first image memory and which simultaneously process a plurality of pixels in the image memory; and another memory corresponding to the processor unit; and a second image memory group having a plurality of second image memories each consisting of a plurality of memory elements that can be accessed by independently specifying addresses, corresponding to the types of output image information. Characteristic image processing device. (2) The image processing apparatus according to claim 1, wherein the processor unit performs color correction of a color image. (3) In the first and second image memories, pixel data in adjacent predetermined areas are allocated to the same location, and pixel data corresponding to the same position on the predetermined area is allocated to the same memory element. An image processing apparatus according to claim 1, characterized in that: (4) The image processing apparatus according to claim 3, wherein the first image memory and the second image memory have different capacities. (5) A first image memory having a plurality of first image memories each consisting of a plurality of memory elements that can be accessed by specifying an address independently of other memories, corresponding to the type of input image information. a plurality of processors corresponding to the memory elements;
a processor unit group comprising a plurality of processor units corresponding to the first image memory and which simultaneously process a plurality of pixels in the image memory; and another memory corresponding to the processor unit; a second image memory group having a plurality of second image memories each consisting of a plurality of memory elements that can be accessed by specifying an address independently of the second image memory according to the type of output image information; An image processing apparatus comprising: a control means for controlling transmission and reception of image data between a plurality of corresponding processor elements. (6) The image processing apparatus according to claim 5, wherein the processor unit performs color conversion of a color image. (7) In the first and second image memories, pixel data in adjacent predetermined areas are allocated to the same location, and pixel data corresponding to the same position on the predetermined area is allocated to the same memory element. An image processing apparatus according to claim 5, characterized in that: (8) The image processing apparatus according to claim 7, wherein the first image memory and the second image memory have different capacities.