JPS63201777A - Picture processor - Google Patents

Abstract

PURPOSE:To increase the picture processing speed by simultaneously processing picture element data in adjacent prescribed areas of a first picture memory by a processor unit while transmitting and receiving picture data by a data control means and storing processing results in a corresponding second picture memory. CONSTITUTION:The first picture memory where picture element data in corresponding positions of prescribed areas are allocated on the same memory element and the data control means which controls transmission and reception of picture data between processor elements are provided. The processor unit which simultaneously processes plural picture elements in the picture memory and the second picture memory where picture element data in corresponding positions of prescribed areas are allocated on the same memory element are provided. An address control means which controls the address in accordance with relations between areas allocated in the same address of the first picture memory and those of the second picture memory. Thus, the picture processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and particularly to an image processing device that performs high-speed processing and parallel processing of image data using an image memory control technique.

[Prior Art] Generally, when processing images at high speed, software is used as the computer processing method.
As the amount of image data increases, the need for higher speeds increases. There are two methods for increasing speed: one is a pipeline method that uses sequential processing hardware, and the other is a parallel processing method that uses multiple processors. The former has a limit because the processing clock frequency increases as image data is processed at high speed. On the other hand, the latter can be increased in speed by increasing the number of processors placed in parallel. In extreme terms, it is one of the technologies that is currently attracting attention because it is possible to obtain the maximum speed by placing as many processors as there are pixels.

By the way, at this time, communication processing between each pixel becomes important, and it is necessary to proceed with processing while performing mutual communication. In such a parallel processing method, it is impossible to have as many processors as each pixel when handling high-resolution data. For example, when handling an image read on A4 paper at 16 pixels/mm (pel), the number of pixels is approximately 16M pixels (pixel).
ls), and it is impossible to have this many processors at the same time.

[Problems to be Solved by the Invention] The present invention provides an image processing device that performs high-speed parallel processing of correlated image data on image data within a predetermined area.

[Means for Solving the Problem] As a means for solving this problem, the image processing device of the present invention has a plurality of memories that can be accessed by specifying addresses independently of other memories. a first image memory consisting of elements, in which pixel data in adjacent predetermined areas are allocated to the same location, and pixel data corresponding to the same position on the predetermined area is allocated to the same memory element;・Multiple processors corresponding to elements・
a processor element that simultaneously processes a plurality of pixels in the image memory, and has data control means for controlling transmission and reception of image data between the processor elements;
It consists of a unit and a plurality of memory elements that correspond to a part of the processor element and can be accessed by specifying addresses independently of other memories, and pixel data in adjacent predetermined areas are located at the same location. pixel data corresponding to the same position on the predetermined area are allocated to the same memory element, and to the same location of the first image memory.

and address control means for controlling an address in accordance with the relationship between the area allocated to the second image memory and the area allocated to the same location of the second image memory.

[Operation] In such a configuration, pixel data in adjacent predetermined areas of the first image memory are simultaneously processed by the processor unit and the data control means while mutually transmitting and receiving image data, and the corresponding second image is processed. Store the processing results in memory.

Margin below [Example] Hereinafter, an example of the present invention will be described. The configuration of the image processing apparatus of this embodiment includes an image memory 1 for one page, a processor unit 2, and a peripheral section 3 such as input/output devices. Figure 1 shows the basic configuration of only the basic part.
A processor unit 2 is connected to the image memory 1 . Nxm image data at an arbitrary position on the image memory 1 is transferred to a processor unit 2 comprising an array of nxm processor elements 2a, processed at high speed, and then returned to the image memory 1. Each process within the array of NxM processor elements 2a is performed simultaneously, which is a so-called parallel processing architecture. Further, other configurations are shown in FIGS. 9(a) and 9(b). In FIG. 9(a), under the control of a control circuit 94, image data from an input end image memory is processed in a predetermined manner in parallel for a plurality of pixels in a processor unit 92 consisting of a plurality of processor elements, and then sent to an output side. The image is stored in the image memory 93. On the other hand, in FIG. 9(b), an image memory 91 or 93, a processor unit 92, an input device 96, and an output device are connected by a common bus.

The image memory 1 will be described in detail below.

Now, for simplicity, set the image size to 1024. x 102
We will proceed with an image memory having 4 pixels, each with 8 bits/pixel data. To change the image size, it is only necessary to extend the architecture of this embodiment. In addition, the processor unit 2 has a total of 16 processor elements 2 of 4×4.
It shall consist of a.

FIG. 2 is a diagram showing the configuration of the image memory 16.

Assuming that the image structure is made up of 1024 x 1024 pixels as shown in the figure, dividing this into 4 x 4 units results in a total of 251i x 25B, 64K (=I
i5536 ) blocks. Now, it is assumed that this is reorganized in 4×4 pixel units as shown in FIG. 3, and that there are 64 4×4 pixels (each pixel has 8-bit data). Therefore, the memory address space is 4X4X
64 three-dimensional addressing.

Assuming that one memory chip has 64 pixels in a 4.times.4 frame, a memory chip is required in which each address is 8 bits deep in the 64 address space. This requires a memory chip with a capacity of 512 bits (=64 Kbytes), but in this embodiment, two dynamic RAMs (D-RAMs) of 256 bits are used in combination. In other words, by using two 256-bit D-RAMs with a 64 x 4-bit configuration, 64KX
Used as 8 bits. These two memory chips will be referred to as memory element 1a from now on.

The image memory 1 is composed of 16 memory elements 1a corresponding to a 4×4 matrix. Fourth
The figure shows the configuration of such a 4×4 memory element 1a. Each memory element 1a is designated with a row address and a column address, and one pixel of 4×4 pixels is designated as 6
4. Output the image data of the address space. The row address generator 4 and column address generator 5 give addresses to each 4×4 memory element 1a. Note that memory element 1a is D-R.
If AM is used to time-share and provide row addresses and column addresses, only one address generator is required. At this time, time-division switching control of row addresses and column addresses is required.

By giving each address from such an address generator, a memory element 1 of 4×4 pixels is created.
It becomes possible to read/write a. That is, by specifying the address - times, image data for 4×4 pixels can be driven simultaneously. Therefore, as a data line,
It is assumed that an 8-bit data line comes out directly from each memory element 1a.

Now, suppose that data with a row address of A (0≦A≦255) and a column address of B (0≦B≦255) is read from the image memory 1, then the image data (A , B), 8-bit long image data of 4×4 pixels is read out.

Furthermore, the simultaneous access of multiple pixels is converted to -192,
explain.

Figure 10 shows one page of the image as it is, and this image data is continuously and adjacently displayed as shown in the figure.
It is divided into blocks of pixels, and as shown in FIG. 11, kXX are made to correspond to the memory elements 1a. Also, the blocks of kxu pixels are (o, o), (0, i, (o, 2)) from the end.

(0, 3)... and k as shown in Figure 12.
Memory consisting of xJ1 memory element 1a
Corresponds to unit 1. Figure 13 shows memory unit 1
It is a two-dimensional representation of Furthermore, since the memory size to be accessed is in block size units of kx, Q pixels, even if kx, Q - one pixel block R at an arbitrary position is accessed, all kx pomelo memory elements 1a will be accessed, and 1 One address is accessed for each memory element 1a.

In this way, the image data of a plurality of adjacent kxJ pixels at arbitrary positions in the image is accessed at once, and after being read, the processor unit 2 processes it. The image data processed by the processor unit 2 can be accessed and written at any position in a block size of "X pixels" again.Here, k'=, u'
-4 will be explained in the future.

To provide a supplementary explanation of the above-mentioned memory access for only the ' may become smaller.

Generally, the block size on the writing side is 'xJJ'.
is often processed as 1×1. Also, when the processing in the processor unit 2 is image reduction processing, the block size accessed on the write side is smaller than the block size kxu accessed on the read side.

= IilQ-wise block size on the write side' x, Q
' is the minimum integer that satisfies the intersection of '≧α and '≧β when the vertical and horizontal reduction rates are α and β, respectively. If the reading and writing memories are the same or have the same memory configuration of kxJl, and the above two examples are performed, the configuration size of memory unit 1 on the writing side is smaller than kx, Q. Must write to size 'xJ1'. In this case, the memory
Memory element 1a that does not correspond to writing without accessing all kxJl elements of element 1a
must be masked to prevent access. However, the image memory 1, which is composed of kx memory elements 1a, can access and read a maximum of kx, Q pieces of adjacent image data at one time; ′ x, Q
The image data of ' can also be freely accessed by performing the masking described above. Masking and accessing only 'x, Q' pieces at the same time is easily possible by manipulating the chip enable of the memory element 1a.

Next, examples of memory access of a predetermined pixel at an arbitrary position will be explained in the case where the memory unit configuration is 4×4 and kXJl, and the control of the chip enable for masking will also be explained. explain.

First, an example will be shown in which the block sizes kx and Q are 4×4.

FIG. 5 shows an enlarged view of a portion of FIG. 2.

A process will be described in which image data of an arbitrary 4×4 block S in the image memory 1 is read out, processed by the processor unit 2, and then transferred to an arbitrary 4×4 block T.

The first row of 4x4 in Figures 5 and 6 is 16 of 4x4.
This is the first point that separates the memory elements 1a. If these 16 memory elements 1a contain Aa, Ab,
..., Ba, Bb, .=Ca, -Dc, Dd. First, when reading out the block S of 4.times..times.4, (N, M) is given as (row address, column address) to memory element Dd among the 16 memory elements 1a. Memory elements Db, DC, and Dd are given (N, N+1), memory elements Ad, Bd, and Cd are given (N+1.M), and the remaining memory elements are given (N+1.M'+1). This is the row address generator 4 mentioned above. Generated by column address generator 5. Also, 4
Once the position of the end point U of the ×4 block S is determined, divide its horizontal and vertical position addresses by 4 and get the remainder n.

It is clear that the row address and column address allocated to memory elements Aa to Dd are uniquely determined by m. Suppose the position address of U (Y, X)
Then, Y=4N+n (n=o, 1,2.3)X=4M+m
(m=0.1, 2.3) For example, M in address generator 4.5.

A configuration may also be considered in which information on N and information on m and n are input into a look-up table or the like, and addresses given to memory elements Aa to Dd are output. At this time, the output is M,
N, N+1. It is clear from the above explanation that it is any one of N+1.

Also, by using this property, as shown in Fig. 7, n or m is entered manually in the lookup table, and 0.
1 and control whether or not to increment the address N or M given to the memory elements A to D d.

The row address generator 4 uses n and N, and the column address generator 5 uses m and M.

In this way, addresses are given to the 16 4×4 memory elements by the address generators 4 and 5 as described above, and 16 pieces of data can be obtained at the same time.

These 16 pieces of data are transferred to the 4×4 block T shown in FIG. 5 again in the processor unit 2, with some processing or no processing at all. However, 16 memory elements A a -D
Each of the image data read from d is not necessarily transferred to the same memory element A a -D d. The 4x4 memory block S in Figure 5 is 4x4
, the data read from memory element Aa of 4×4 memory block S must be transferred to memory element DC.

Then, the 4×4 memory blocks S, T are at their end points u, v
has arbitrary positions (Y, X), (Y', I'll explain if it's good.

As shown in Figure 5, Y = 4N+n (n=o, 1, 2.3)X = 4
M+m (m=o, 1.2.3)Y' =4P+p (
p=o, 1, 2.3) X' = 4Q+q (q=0.1
2.2.3), p-n=4y' +y (y' = -t,.

y=0+t, 2.3)...■ q-m=4x'x (x'=-1, 0x=o, 1.
2.3) ...■ Find x and y.

First, the row array A consisting of (Aa, Ab, Ac, Ad) is rotated X times in the right direction. This is named row array A'. Similarly, row arrays B, C, and D are rotated X times in the right direction, resulting in row arrays B', C', and D'8.
Name it.

Next, the array (ABCD)' consisting of row arrays A', B', C', and D' is rotated downward seven times.

In the case of FIG. 5, n, m, p according to FIG.

Since q is obviously 3, 3, 2.1, ■Formula%Formula% obtain. Therefore, from the above explanation, we obtain the following matrix.

Rotate twice to the right, row array A' = (Ac, Ad, Aa, Ab) B' = (Be, Bd, Ba, Bb
)C' = (Cc, Cd, Ca, C
b) D' = ('D C, Dd, Da,
Db) When rotated downward three times, (Be, Bd, Ba, Bb) (Cc, Cd, Ca, Cb) (DC, Dd, Da, Db) (Ac, Ad, Aa, Ab) -...■ This matrix■
Comparing this with the basic arrangement ■ below, Aa, Ab, Ac, Ad Ba, Bb, Be, Bd Ca, Cb, Cc, Cd Da, Db, DC, Dd - Basic arrangement ■ Basic arrangement The matrix ■ is simply a two-dimensional array of data to be read from memory elements Aa to Dd arranged in order from left to right and top to bottom, and the matrix ■ is a two-dimensional arrangement of data to be written to memory elements Aa to Dd in order. It corresponds to an array. That is, as an example, data read from memory element Aa is written to the fourth row and third column when looking at the array {circle around (2)}. If you refer to this basic array ■, the 4th line 3
Since DC is in the column, memory element DC
It can be seen that it is sufficient if the read data of memory element Aa is written to .

For supplementary explanation, memory niremen)-Aa on Figure 5
It is easy to notice that it is sufficient if the read data of is written to the DC position, but the displacement from this position Aa to the DC position is equal to the displacement from the position address U to V. Also, since the configuration of the memory element 1a is 4×4, the horizontal direction
The remainder when both vertical positions are divided by 4 can be considered to be the displacements x and y of the memory element. For example, if the displacements of u and v are multiples of 4, the displacements x and y will be 0, and data read from a certain memory element will be written to the same memory element after processing. It is.

The hardware implementation of the above processing will be briefly explained.

FIG. 8 shows that data simultaneously read out from memory elements 10 consisting of 16 4×4 memory elements 1a is processed by the processor unit 2, and the data is stored in X-displacement raw data 81 by 4 elements each. Perform rotation for X number of times. After that, rotation is performed by the number of y based on the y displacement raw data 82,
Aa ~ Ad, Ba-Bd, Ca ~ Cd, respectively
The configuration is such that data is written to memory elements 1a from Da to Dd.

Note that the y-displacement raw data 82 has four input elements each, so the y-displacement raw data 82 is exactly the same as the X-displacement raw data 81.
Needless to say, it can be composed of It goes without saying that the raw data may have a depth of the same number of bits as the depth of the memory data, or that the same number of 1-bit depths as the depth of the memory data may be used. Furthermore, it can be easily inferred that a shift register, barrel shifter, etc. can be used for raw data.

Furthermore, if we consider it as a film, we can make the memory block kx
, Q, the memory emunit 10
The configuration of is also kxdan. In this case, the memory block S of kx, Q located at an arbitrary position is transferred to the processor unit 2.
After processing, when transferring to kx4 memory block T at an arbitrary position, Y=kN+n (n=o, 1.-, k-1)
X=AM+m (m=o, 1.-, father-1
) (N, M, P, Q are 0, 1, 2.3...)Y'kP+p (p-value 0.1..., k-1)X
′ Tomibun Q+q (q=O,'1. ..., q-
1) However, the position address of the end point of S is (Y, X), T
The position address of the end point of (y', x')...(10) Find n, m, p, q, p-n=Ky'+y (y'-1,0,'J' O, 1, 2, 3,...
, ni-1) q-m=x'+x (X'--1, O, X -0, 1, 2, 3, ·, u-
1)...(11) Using x and y, for example, the X displacement raw data 81 and y displacement raw data 82 as shown in FIG. 8 may be used to perform the processing. In this case, the X displacement raw data 81 has a sentence example input and can be shifted from 0 to dan-1. The y displacement raw data 82 has k manual forces and can be shifted from 0 to -1. Moreover, since each input of the y-displacement raw data 82 has a communication element, the raw data of one element of human input constitutes a sentence example.

As shown in FIG. 10, memory element access control for simultaneous access of the above-mentioned blocks 'x, Q' will be explained.

Let the position address of the end point i of the block k′xJJ′ be (f
, g). Y when reading the memory accessed according to the above equation (10).

When assigning flg to X and writing to the memory to be accessed, assign f and g to Y' and X'.

By substituting the result into Equation (11) to obtain y and x, the embodiments shown in FIGS. 7 and 8 can be applied directly to kx and Q.

Also, at this time, among the memory elements kx and Q,
Chip enable only the memory element k ” l . The chip to be enabled is
Once the location address of (f, g) of end point i of 1' is determined, n, m, or p, q can be uniquely determined from equation (10), and '×fl' memory elements need to be accessed. is also uniquely determined.

By the way, as explained so far, in a memory configuration consisting of kX, Q- memory elements, 'x' blocks are accessed simultaneously on the read access side, and k'x, l' blocks are accessed on the write side at the same time. Simultaneous access may also be considered (0≦k''≦, O≦view°°≦dan), but this is also the same as the previous explanation.Chip enable control given to memory elements in this case An example of this is shown in FIG.

When the position addresses of the end points of the blocks k"xJl" and k"xdan" are (y, x), (y', x'), the formula (1
0), n, m, p, and q are found. This n, m and p
, q are entered manually into the data input of the selector. Furthermore, a read/write signal R/W for memory access is inputted as a selection control signal of the selector, and n and m are selectively output when reading, and p and q are selectively output when writing.

Similarly, block size, k=, ” and ′°.

The sentence " is also input manually to the selector, and the R/W signal is input as a selection control signal. When reading, k',, Q-"
Select output and write to °°.

dan°′ is selectively output. By the way, the memory elements to be accessed are n, m, and ' on the read side.

It is clear that once k"+U"+P+Q on the write side is determined, it is uniquely determined, so these data output from the selector are input to the lookup table, and each of the memory elements of kxJJ is accessed. Outputs signals that control the memory to be used.

By the way, if the image memories 1 before and after processing by the processor unit 2 are different memories, and their memory configurations are kxJJ and KXL, respectively, as shown in FIG.
It can be easily inferred that it is sufficient to use one lookup table. In this case, lookup table 151 and lookup table 152 are tables with different contents.

Also, there is no problem at all if k = becomes father -L. With the configuration described above, it is possible to mask some of the memory elements to be accessed without having to access all of the kx sentence example memory elements. And the mesori element configuration of kxJl requires the maximum kx, 11
You can set it to the size of .

Next, a description will be given of how to access the memory elements and process all the image data corresponding to the entire previous screen, that is, how to scan the access of all the memory data.

For example, access neighboring kx! ;The position address of the end point U of the block of L, that is, when Y is the number when counting from 0 in the vertical direction and X is the number when counting from 0 in the horizontal direction. The method of accessing the memory when Y and X are determined has already been explained. Now then, this X.

In what order do you scan Y and process all images? An example will be explained below.

(First example) This is a method of scanning the image data position addresses Y and X for accessing the memory element of kXl by increasing or decreasing them by integer multiples of l.
, set X to 0, and increase X sequentially by 1. After increasing X to the end point in the horizontal direction, set X again to O, and set Y
Increase by , and then increase X by a sentence. This is repeated sequentially to scan the entire screen or a part of the screen. This will be tentatively named the first sequential scanning method.

(Second example) Also, instead of increasing and decreasing X and Y sequentially as described above, you access consecutive kx blocks here and there on the entire image screen one by one, and when you access it, When the displacement of X and Y is an integer multiple of one sentence, this is tentatively named the first random scan method.

(Third example) A method of scanning by increasing or decreasing the image data position addresses Y and X by integers to access memory elements kx and Q. For example, first, Y and
, and sequentially increase X by 1. After increasing X to the end point in the horizontal direction, set X back to O and set Y to 1.
Then increase X by 1. This is repeated sequentially to scan the entire screen or a part of the screen. This is tentatively named the second sequential scanning method. In this case, the same memory data is accessed many times.

(Fourth Example) Also, instead of increasing and decreasing X and Y sequentially as described above, blocks of kXl here and there on the entire image screen are accessed one after another, and this is executed for all X and Y. Or X of all consecutive parts of the entire screen,
Go to Y and execute. When it is random, we tentatively name it the second random scan method.

(Fifth example) In a memory configuration with kXl memory elements, when the memory block to be accessed is 'x statement',
(1≦ ′≦, 1≦dan′≦ sentence) The first sequential method is to increase/decrease the position addresses Y and X by integer multiples of ′ and U′ and repeat this sequentially to scan the entire screen. It is called the blockwise sequential scan method to distinguish it from the scan method.

(Example ε) Also, instead of increasing and decreasing X and Y sequentially as in (Example 5), access successive blocks of 'x sentences' here and there on the entire image screen, and then Y,
When the displacement of x is an integral multiple of 'xJ1', this is tentatively named a blockwise random scan method.

(7th example) Regardless of the memory configuration of memory element kXi,
Something to scan sequentially, e.g. any number d
A method in which scanning is performed by changing X and Y every ', f' is simply called a sequential scan method.

(8th example) Even in the case of (7th example) when scanning is performed at random, or (4th example) when memory access is not performed for all combinations of X and Y, it is simply called a random scan method. do.

As mentioned above, there are many scanning methods that can be considered, but apart from these, there is also a read-side memory access for memory access, and a scan method for read-side memory access and a write-side memory access. The scanning methods do not necessarily match.

Furthermore, in this scanning method, once the read side is determined, X' and Y' to be accessed on the write side are determined by the processing content of the processor unit 2. Alternatively, the scanning method on the write side may be determined first. In this case, the scan on the read side is determined by the processing content.

Further, the block sizes ' and u' to be accessed on the read side and the write side may be different, and the size of the memory element configuration kxU may be different.

Based on the above description, an example of a scanning method will be described in the case of the embodiment described later in which an array processor unit is used as the processor unit 2 and spatial filter processing is performed.

First, in the embodiment described later, the human power m″×n″ pixel area output is k
``'X view°'' pixel area, in this case output side 1
In order to obtain output for the entire screen, the m″×n″ readout pixel area at the input end should be set horizontally at k° with respect to the entire screen.
It is good to scan by shifting the vertical force by °°' units. Also, at this time, the position of the upper left pixel in the pixel area of m''×n'', k'''
.

X'), then Y and X are each 1.

All memory addresses can be scanned by increasing/decreasing the vertical and horizontal addresses each time.

In this case, the read side memory scan corresponds to the sequential scan method, and the write side memory scan corresponds to the blockwise sequential scan method.

Also, the memory configuration itself on the write side is k ”' x Q ”
If the memory unit is made up of '' memory units, the first sequential scanning method, as described above, simultaneously accesses the image data on the image memory corresponding to the rectangular area m pixels x n pixels on the original image, and An array processor unit (hereinafter referred to as APU) consisting of mxn PEs in which one arithmetic element (hereinafter referred to as PE) corresponds to each pixel.
The following describes the process of taking in pixel data, performing spatial filter calculation processing using the API, and outputting the results.

FIG. 18 is a diagram showing the correspondence between the human power block 181 and each pixel 181a, APU 182 and PE 182a, and the output pixel block 183 and each pixel 183a corresponding to the original drawing. Here, m=n=4. Therefore, data for 16 pixels in the input memory can be simultaneously accessed and the APU
Incorporate into.

The APU is composed of 16 PEs. The APU performs spatial filter calculation on a 3 pixel x 3 pixel area, and
Output to an output side memory block consisting of 2 pixels and 4 pixels.

Here, each PE in the APU corresponds to a 4×4 pixel, and is configured in a square grid of 4×4=16 PEs. Number each row and column in order, and in combination,
As shown in FIG. 19, each PE is distinguished by expressing it as (row number, column number).

Here, the spatial fullter operation is, for example, using a coefficient matrix as shown in FIG. 20, multiplying each coefficient with each corresponding pixel, and outputting the sum to the memory corresponding to the center position. It is something. To explain using FIG. 21, (1, 1), (1, 2), (1, 3), (
2,1), (2,2), (2,3), (3,1), (3
, 2'), and (3, 3), (2, 2) performs calculations, receives data from other PEs, and performs spatial filter calculations. Similarly, (1,2
), (1,3), (1,4), (2,2), (2,
3), (2,4), (3,2), (3,3), (3
, 4), for a 3×3 area consisting of ('2.
3) performs a spatial filter operation, (2', 1), (2,
2), (2,3), (3,1), (3,2), (3
;3), (3,2) performs a spatial filter operation on a 3×3 area composed of (4,1), (4,2), and (4,3). Also, (2, 2), (2, 3), (2,
4), (3,2), (3,3), (3,4), (4,2
), (4,3), and (4,4), (3,3) performs the spatial filter calculation.

Here, perform spatial filter calculations (2, 2), (2, 3
), (3,2), (3,3) P'E is, for example, the second
A circuit as shown in FIG. 1 is provided, and the above-mentioned spatial filter operation is realized using this circuit. The circuit in FIG. 21 adds data from eight adjacent PEs to adders 221 to 227.
, add them all, multiply by 1X8 with shifter 228, and subtracter 2.
In step 29, the difference between the value taken in by P'E itself which has this circuit, which becomes the pixel of interest, and the value delayed by the delay circuit 231 is calculated, and the adder 230 calculates the difference between the difference output from the subtracter 229 and the value taken in by pE itself. A spatial filter operation is executed by calculating the sum of the signal and the signal further delayed by the delay circuit 232. As a result, the 4x4 pixel area can be manually divided into 2x
It outputs to a 2-pixel area.

In addition, in the explanation, a 4x4 pixel area is used manually, a 2x2 pixel area is used as an output, and a spatial filter is used as a 3x3 pixel area, but the invention is not limited to this. It is clear that the area and the spatial filter can be made into a pxq pixel area (where m≧+Ps and n≧fl+q). Also, the coefficients of the spatial filter are also
The present invention is not limited to the one shown in FIG. 0, and a PE equipped with a processing circuit corresponding to the coefficient matrix may be used.

As explained above, since the processing that was conventionally repeated for each output pixel is outputted for a plurality of output pixels in the same cycle, extremely high-speed processing becomes possible.

Another advantage is that spatial filter calculations can be executed in one cycle by manually processing consecutive neighboring pixels at the input end, and spatial filter calculations can be output simultaneously for multiple output pixels. be.

In addition, by accessing and processing multiple pieces of input data at the same time, processing execution speed is not only faster than accessing data one by one, but also by sending and receiving data between each PE, data can be accessed simultaneously. Calculations (spatial filter calculations, color processing, etc.) that also take into account the correlation between
It also has the advantage that it can be executed with only one input data access.

In other embodiments of the present invention to be described later, image enlargement processing is performed in the processor unit 2, but the numbers kxJJ and KXL of memory elements constituting the image memories on the read side and the write side are not limited. Furthermore, the block size of pixels accessed on the read side and the write side is not limited to 'X sentence' or K' x L'.However, due to the image enlargement process performed by the processor unit 2, the access size on the read side is When the enlarged size of 'xl' is the maximum vertical and horizontal scaling factor α and β,
It can be easily inferred that K≧α and L≧β intersection must be satisfied.

Expansion processing will be explained. As shown in FIG. 22, the processor unit 312 includes an address generation section 313 and an arithmetic circuit section 315, and operates under the control of the control circuit 311. The address generation section 313 includes the arithmetic circuit section 31
The start address of the input image memory 316 holding the input image data necessary for calculating the image data corresponding to the output image memory 317 output by each processor element in the processor element 5 is generated. The arithmetic circuit unit 315 takes in all the image data of the data area having the start address as one end of the image area.

Each processor element selects human data corresponding to the position of the output side image memory 317 where the calculation result is to be outputted from among the captured data, performs a two-dimensional interpolation calculation, and outputs the data.

This will be explained in more detail below. For convenience of explanation, it is assumed that the processor unit 312 has a configuration of 4 columns in the main scanning direction and 4 rows in the sub-scanning direction, that is, 16 processor elements. Input side image memory 316
always outputs data of 5 columns in the main scanning direction and 5 rows in the sub-scanning direction, that is, a 25 pixel area, to the processor unit at the same time. At this time, the address generation unit 313 instructs which 5×5 area data is to be output. The address generation section will be explained according to FIG. The register 321 is set in advance by the control circuit 311 to a value that is four times the reciprocal of the magnification in the main scanning direction. Further, a value that is four times the reciprocal of the magnification in the sub-scanning direction is set in advance in the register 322 by the control circuit 311. Also,
The latch 325 is cleared to τ by the operation synchronization signal in the sub-scanning direction, and the adder 3 is cleared to τ by the operation synchronization signal 327 in the main scanning direction.
Take in the output of 23. The adder 323 adds the value held in the register 321 and the value held in the latch 325 with the operation synchronization signal 327 in the main scanning direction and outputs the result. As a result, the value output by the latch 325 increases by four times the reciprocal of the magnification in the main scanning direction due to the synchronization of the operation in the main scanning direction, and is cleared to O every time the synchronization of the operation in the sub-scanning direction is entered. Register 322. Adder 324. Latch 326 also registers 321 . Adder 323. With the operation of latch 325,
If main scanning operation synchronization is replaced with sub-scanning operation synchronization and sub-scanning operation synchronization is replaced with page synchronization, the operation will be exactly the same. latch 3
The outputs of 25 and the latch 326 are used as a signal indicating a 5×5 pixel area of the input end image memory 316. The input end image memory 316 outputs data for 25 pixels in an area of 5 pixels in the main scanning direction and 5 pixels in the sub-scanning direction from the address position. Output side image memory 31
Regarding the address No. 7, the address is increased by 4 pixels in the main scanning direction of the output side image memory 317 according to the synchronization of the main scanning operation, and the address is increased by 4 pixels in the sub-scanning direction according to the synchronization of the sub-scanning operation.
This increases the address for each pixel.

Address correction section 314 in processor unit 312
is for selecting appropriate 4-pixel data from among the input 25-pixel data and providing interpolation coefficients for interpolation calculations to each of the 16 processor elements in the arithmetic circuit unit 315. generates an address correction signal.

FIG. 24 shows the configuration of the processor unit 2, and 331 is the address generation section 313 itself explained in FIG. 23. 332 is composed of a circuit similar to the circuit explained in FIG. 23, but the register 32 in the main scanning direction
1, the main 2 always has a larger value than the main 1 by the reciprocal of the magnification in the main scanning direction, the main 3 has a similarly larger value than the main 2, and the main 4 has a similarly larger value than the main 3. On the other hand, the register 322 in the sub-scanning direction stores sub-4 by the reciprocal of the magnification in the sub-scanning direction.
has a larger value than sub-3, sub-3 has a larger value than sub-2, and sub-2 has a larger value than sub-1. Also, main 2 to main 4 and sub 2 to sub 4
is used as a signal to indicate which four pixels out of the 25 pixels of the input camera should be selected. For example, if we consider the case of enlarging 2.5 times in the main scanning direction and 1.5 times in the sub-scanning direction,
The main 1 counts up by 1.600 (=4 x 1/2.5), the sub 1 counts up by 2.666 (~4 x 1/1.5), and the integer parts of the main 1 and sub 1 counters are counted up. It is used as the start address of the 25-pixel area of the input side image memory 316. Moreover, the decimal part of the output of main 1 is in one column of the processor array, that is, (1, 1) in FIG.

This data is used as interpolation coefficient data in the main scanning direction for four processor elements (PE) (2,1), (3,t), and (4,t). The fractional part of the output of sub-1 corresponds to one row of the processor array, that is, (1, 1), (1,
2), (1, 3), and (1, 4) as interpolation coefficient data in the sub-scanning direction. Main 2, main 3, main 4 are 0.40 between each value
There is a difference in the count amount by 0 (-1/2.5), and the second
, sub-3, and sub-4 have 0.666 (~1/1.
5) There is a difference in the count amount. Additionally, the integer part of the latches that store these counts is cleared each time, and the decimal part is accumulated. Main 2 to main 4 are each 2 of the processor array.
The integer part and the decimal part are output to each of the processor elements in the columns 4 to 4, and the sub-2 to sub-4 output the integer part and the decimal part to the processor elements in the 2nd to 4th rows of the processor array, respectively. Each processor array has a corresponding latch 325 in the main scanning direction and a corresponding latch 3 in the sub-scanning direction.
Using the integer part from 26, select 4 pixels from the 25 pixel data from the input end image memory 316, perform two-dimensional interpolation using the decimal part as an interpolation coefficient, and interpolate into the corresponding output side image memory 317. It outputs the calculation results. The output side image memory 317 always has 4 pixels x 4
Accessed in units of 16 pixel areas, each P
E is associated with one of the 16 pixels.

FIG. 25 shows a selection circuit that selects 4 pixels from 25 pixels that each PE has, and FIG. 26 shows an example of the configuration of the selection circuit in FIG.
51 to 355 and sub-scanning selectors 356 and 357. FIG. 27 shows an example of the configuration of each main-scanning selector and sub-scanning selector. 4-person power 1-output selector with 2 devices 361°362
This shows that it can be composed of Furthermore, the integer parts from the main 1 and sub 1 always output the value O to the PEs in one column and one row, respectively. As a result, each PE (i, j) selects the four manpower addresses, 1+1, 3rd, and J+1 for the output (I, J) of the integer part of the main 11 subj. As a result, pE(i, j) is [1, J ko, [++1. J
l, [I, Jl1], [++1. Jl
1] are selected as four pixels.

Next, in the two-dimensional linear interpolation circuit shown in FIG.
[1+1. Jl + V [++1. J+l] and the interpolation coefficients for main scanning and sub-scanning are α and β, respectively, and these are given as the corresponding fractional parts of main 1 to 4 and sub 1 to 4, and (1-β)(1-α )V[1,Jl +αV[1+1
．． Jl ) + β ((1-α) V [1,,
, +++] + α V [+41. J+I]
) is calculated and interpolated and output. (0≦α.

β1) The operation of the processor unit 312 has been explained above, but the input end image memory 316 and the processor unit 31
2 and the pixel area of the output side image memory 317 are as follows.
The relationship is as shown in Figure 9. That is, the number of processor elements of the processor unit 312 is equal to the number of pixels of the output side image memory 317, and the number of processor elements of the input side image memory 31 is equal to the number of pixels of the output side image memory 317.
The number of pixels in the image area used for the calculation in step 6 is smaller than the number of processor elements in the processor unit 312.

As explained above, according to the Kinotsu style, processing results that were conventionally repeated for each output pixel are outputted for a plurality of output pixels in the same cycle, making it possible to perform extremely high-speed processing.

Furthermore, there is an advantage that interpolation calculations can be executed by inputting consecutive neighboring pixels on the input side at once.

[Second embodiment] kxJ1 for accessing kXl data at the same time
A second example of allocating image data to memory elements will be described.

FIG. 16 is a diagram showing a state in which the upper part of one image screen has been replaced with data, and this is divided into two equal parts in the horizontal direction and divided into equal parts in the vertical direction. To explain the areas divided into kXU at this time, (0, 0), (0, 1), ... (
0, father), . . . , (k, see), each area is allocated to each memory element as shown in FIG. The allocation method is to allocate the dashed diagonal area shown in Figure 16 to address 0 of each memory element, then allocate the adjacent image data to address 1 of each memory element, and similarly, allocate the area within the area. When all the lines have been allocated, the second line is allocated from left to right in the same way, and all the image data is allocated. Then, for all kxJlj memory elements, the row address generator 4 shown in FIG.
When the addresses given by the column address generator 5 and the column address generator 5 are all the same, discrete pieces of image data can be accessed at once, as shown in the shaded area in FIG.

By adopting such a configuration, it is possible to specify a certain address, read the image memory 1, and after processing in the processor unit 2, change the address when writing to kxU memory elements 1a. There is a possibility that data can be written without any errors. For example, as shown in FIG. 16, when the area is composed of KXL pixel data, one part of one image screen is displaced by an integral multiple of L in the horizontal direction and an integral multiple of K in the vertical direction. When performing processing such as movement or transfer, the read address and write address may be the same. For this purpose, the row address generator 4
．． The load on address control such as the column address generator 5 is extremely reduced.

This movement and transfer processing is processed by the processor unit 2. As shown by dashed diagonal lines in FIG. 16, the processor unit 2 receives kXl image data, which covers the entire screen, and each piece of data is divided into horizontal and vertical directions. , so in processor unit 2 kx
, Q pieces of data may be exchanged or transferred, and processing may be executed sequentially from 0 on all addresses of the memory element. As a result, processing can be performed on the entire screen.

In this example, the mesori configuration of kxf1 is, for example, 1xJJ
, kXl, etc., and by allocating one horizontal line or one vertical line in one image screen to each memory unit, processing in the processor unit 2 can be performed by histogram calculation for one line of the image or -dimensional Fourier calculation. It can be inferred that it can be applied to various image processing such as conversion. Furthermore, when a plurality of pixels are accessed simultaneously, there is no limitation as to which memory element and which address the data in one screen of images is allocated to.

"Effects of the Invention" According to the present invention, it is possible to provide an image processing device that performs high-speed parallel processing of correlated image data within a predetermined area.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of the image processing device of this embodiment, Fig. 2 is a diagram showing how one screen of images corresponds to the address of a memory element, and Fig. 3 is a diagram showing a memory consisting of 4 x 4 memory elements. Figure 4 is a diagram showing the whole memory and the address generator given to it. Figure 5 is a diagram showing a part of the image. Figure 6 is a diagram showing the layout of a part of the image. Figure 7 is a diagram of the memory. FIG. 8 is a block diagram of pixel data control; FIGS. 9(a) and (b) are diagrams showing the configuration of another image processing device according to this embodiment; FIG. 10 is a block diagram of pixel data control; Figure 11 shows kxJJ memory elements. Figures 12 and 13 show one memory element. Figures 14 and 15 show memory element access. Fig. 16 is a diagram showing one image screen; Fig. 17 is a diagram showing kx, Q memory elements; Fig. 18 is a diagram showing the input pixel area size of the input side memory and the output side memory. Figure 19 is a diagram showing the correspondence between the output pixel area size and the array size of the block unit processor/four-core knee. A diagram showing a coefficient matrix of a spatial filter operation executed by a processor unit, FIG. 21 is a side view of the configuration of a circuit that performs a spatial filter operation, FIG. 22 is a conceptual block diagram during enlargement processing, and FIG. 23 is a diagram of a processor unit. Figure 24 is a conceptual diagram of the internal block diagram of the processor unit; Figure 25 is a conceptual diagram of the data selection circuit in each processor element; Figure 26 is the configuration of the data selection circuit. Figure 27 is a more detailed configuration diagram of the main scanning selector and sub-scanning selector in Figure 26, Figure 28 is a conceptual diagram of a two-dimensional linear interpolation circuit, and Figure 29 is a diagram showing input and output pixel area sizes. FIG. 3 is a diagram showing correspondence between array sizes of processor units. In the figure, 1...image memory, Ia, lb...memory
Element, 2... Processor unit, 2a...
・Processor element, 3... Peripheral part, 4...
Row address generator, 5... Column address generator, 91... Input side image memory, 92.
... Processor unit, 93... Output side image memory, 94... Control circuit, 95... Human power device, 96...
...Output device, 181...Manual image memory block,
181a... Input pixel, 182... Processor unit, 182a... Processor element, 18
3... Output image memory block, 183a... Output pixel, 311... flit H&D circuit, 312...
Processor unit, 313...address generation section,
314: address correction unit, 315: arithmetic circuit unit, 316: input side image memory, 317: output side image memory. Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 Figure 19 Figure 20

Claims (2)

[Claims] (1) Consisting of multiple memory elements that can be accessed by specifying addresses independently of other memory,
a first image memory in which pixel data in adjacent predetermined areas are allocated to the same location, and pixel data corresponding to the same position on the predetermined area is allocated to the same memory element; a processor unit consisting of a plurality of processor elements, having data control means for controlling transmission and reception of image data between the processor elements, and processing a plurality of pixels in the image memory at the same time; It consists of a plurality of memory elements that can be accessed by specifying addresses independently of other memories, and pixel data in adjacent predetermined areas are allocated to the same location, and pixel data on the predetermined area is a second image memory in which pixel data corresponding to the same position is allocated to the same memory element; an area allocated to the same location in the first image memory and an area allocated to the same location in the second image memory; An image processing apparatus comprising: address control means for controlling an address in accordance with a relationship with a region. (2) The image processing device according to claim 1, wherein the processor unit performs spatial filter processing on the image.