JPS60185987A - Image data compression - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for compressing image data displayed by a computer or the like.

Conventionally, since the images of computers and the like have an extremely large capacity, a storage device with an extremely large capacity has been required to record the special images on a storage device.

In order to improve this, methods have been used to focus on each scanning line of an image and convert and compress it into pixel types and continuous amounts of pixels, as shown in Figure 1 (al). Many Konopiyuta have a small number of colors, and a method of expressing neutral colors by placing different colors next to each other is widely used.For example, as shown in Figure 1 (b), red and yellow are alternated. This method has the disadvantage that it has no image compression effect at all, since it expresses an orange color by placing it in the image.

This invention was made to improve the above-mentioned situation, and its purpose is to provide an image compression method that is highly effective even for images using the intermediate color method and is suitable for actual situations. .

Examples will be described below with reference to the drawings. Figure 2 fa)
, (b) are explanatory diagrams of the embodiment. Figure 2 (al) is a case where attention is focused on one scanning line, but the pattern of yellow on red, white and green continues. The compression conversion of this is shown in Figure 2 (1). In this example, the scanning line is divided into two pixels fσ, and the pixel patterns of "red yellow" are compressed into six pixel patterns and the pixel patterns "white edge" are compressed into three pixel patterns.

FIG. 3 is a detailed circuit diagram of the embodiment. video memory A,
B and C (2a to 2c) are image memories in which images are stored, and are normally connected to an image display circuit, but are omitted in this example for the sake of explanation. There are three sets of video memory,
This is to express colors, and the type of color of a specific point on the screen is determined by the data of the same bits at the same address in the video memories A to C. For example, video memo') A-C
If 0.0.0 is read from each, it is black, Olo,
It is structured in various ways such as 1 for blue, 0.1.0 for red, ■, 0.0 for green, etc. An address signal is supplied to the video memories A to C from the video memory address counter 1, and the internal data is read out in accordance with the signal. Read image data +2a~! 2c are respectively input to parallel-serial conversion circuits A-C (3a to 3c) and serially converted. A detailed diagram of this conversion circuit is shown in FIG. Figure 4 shows the parallel-to-serial converter circuit A (3a
), the internal circuits of all three sets are the same.

This circuit stores the output 12a of the video memory A in the internal F/F (4g to 4n) when the LOAD signal 13 becomes ゛1'', and then transfers the data to the 2-bit serial signals 14a and 14b every time the clock φ1 is applied. This output is applied to the matching circuit of FIG. 3 5a, one as is and the other through F/F (4a, 4b), and a match/mismatch determination is made.-Math circuit A (5a) A detailed circuit diagram of EXCLUS I VEOR circuit 24 is shown in Figure 5.
a, 24b and the NOR circuit 25, inputs 14a and 15
Only when a, 14b and 15b both match”!
”, otherwise “0” is output. This output 16a
is input to the N A N ]) circuit in FIG. - Since the several circuits A-C (5a to 5c) are completely the same circuit, the output of the NAND circuit 9 is the input 16a, 16b, 16c.
It becomes "o" only when all are °゛1''. In other words, 14a and 15a, 14b and +5b, 14c and +5
c, 14d and 15d, 14e and +5e, 14f and 15f
It becomes "o" only when all of them are equal. This indicates that the two pixels on the left and right and the following two pixels have the same pixel pattern on the screen. If even one of these does not match, the value becomes 1'', indicating that the pixel patterns are different. WR), AND game) 10b.At this time, the pixel pattern code 20 is added to the address of the main memory 8 referenced by the memory address counter 7.
Then, the pixel pattern number data 21 given by the counter 6 is written. This situation will be explained using FIGS. 6 and 7.

Figure 6 (al indicates an example of the contents of video memo 'JA, B, C. Figure 7 is a time chart, The final contents of the main memory 8 are as shown in FIG. 6(b). In FIG. 7, φ1 is the basic write clock, and φ2 is the basic read clock. All The signal is written in synchronization with φ1 and read out in synchronization with φ2.L
The OAD signal 13 is a timing signal for a parallel-to-serial conversion circuit, and when it is " ] ", the contents of the video memory are read and a serially converted signal is output according to the IIoI+ period clock. Video memory address counter 1
(2) The clock signal φVA synchronized with the OAD signal 13 is used to output the signal. Serial converted signals (14a-f
, 15a-f) are outputted as shown in FIG. 7 and applied to minus number circuits 5a, 5b, 5c. The matching output is 16a,
16b and 16c, so the mismatch signal 17 is "]
” indicates that the pixel pattern 7 has changed. At this timing, the pixel pattern code 20 and the pixel pattern/number data 21 are written to the main memory 8, and at the same time the main memory address counter 7 is incremented by .

The preset counter 6 is preset to 0.1''. Since the preset counter 6 is normally updated according to the basic clock, it indicates the number of pixel patterns 7 when it is written into the main memory 8. .

As described above, the present invention has the advantage that it also has a compression effect on computer images using the intermediate color method.

[Brief explanation of the drawing]

FIG. 1(a) is an explanatory diagram of the conventional example, fb) is an explanatory diagram of the intermediate color method, FIGS. 2(a) and (bl are explanatory diagrams of an embodiment of the present invention, and FIG. 3 is a circuit diagram of the embodiment) 4 is a detailed circuit diagram of parallel-serial conversion circuit A (3a), FIG. 5 is a detailed circuit diagram of matching circuit A (5a), and FIG. 6 fa) is a detailed circuit diagram of video memory A, B, C (2a). , 2b, 2C), FIG. 6(b) is a diagram showing compression results according to the example, and FIG. 7 is a diagram showing a time chart according to the example. 1.°゛Video memory address counter 2...Video memory, 3...Parallel-serial conversion circuit, 4...
Flip-flop, 5...-number circuit, 6... Preset counter, 7... Main memory address counter, 8... Main memory, 9... NAND AND circuit 0... AND circuit, l 1. ...Video memory address signal, 12.Video memory output, 13..LOAD signal, 14' parallel-serial conversion circuit output, 15..
Flip-flop output, 16...-number circuit output, 17
... Mismatch signal, 18... Main memory address power counter clock (φMA), 19... Main memory address signal, 20... Pixel pattern code, 21.
... Pixel pattern number data, 22 ... Tri-state gate, 23 (7 bits, 24 = EXCLUS
I VE OR circuit, 25...NOROR Circuit diagram 1 diagram) Emphasis range diagram 1 diagram (Iei 4 diagram Serial faithful power match output 茄6 diagram (0,, >

Claims (1)

[Claims] An image data compression method characterized by converting an image displayed by a computer or the like into a coded code of a pixel pattern including a plurality of pixels and the number of the pixel patterns.