CN203722733U - Image format converter - Google Patents
Image format converter Download PDFInfo
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- CN203722733U CN203722733U CN201320875176.2U CN201320875176U CN203722733U CN 203722733 U CN203722733 U CN 203722733U CN 201320875176 U CN201320875176 U CN 201320875176U CN 203722733 U CN203722733 U CN 203722733U
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Abstract
The utility model discloses an image format converter including an ITU-R601 input interface, an FPGA module and a VGA output interface. The FPGA module includes a dynamic random access memory connected with the ITU-R601 input interface, a deinterleaver connected with the dynamic random access memory, a resolution interpolation sub module connected with the deinterleaver, a color space converting sub module connected with the resolution interpolation sub module, a digital analog converter connected with the color space converting sub module and a VGA time sequence controller connected with the digital analog converter. The VGA output interface is connected with the VGA time sequence controller. By adopting the image format converter, image format conversion can be realized for ITU-R601 standard image input and VGA image output.
Description
Technical field
The utility model relates to format converter technical field, more particularly, relates to a kind of image format conversion device.
Background technology
At present, picture format is of a great variety on the market, for different application demands, need to make different image format conversion, and wherein, some image format conversion, have corresponding chip to complete conversion, and several chips of some needs join together to solve image format conversion.
Yet, some image format conversion cannot find corresponding chip to solve format conversion problem, for example, the image that does not at present also have chip can realize ITU-R601 standard converts VGA (Video Graphics Array to, Video Graphics Array) image that display shows, therefore, a kind of image input that can support ITU-R601 standard, the image format conversion device of VGA image output becomes needs.
Utility model content
The purpose of this utility model is to provide a kind of image format conversion device, and it can support the image input of ITU-R601 standard, the image format conversion of VGA image output.
For achieving the above object, the utility model provides following technical scheme:
An image format conversion device, comprising:
ITU-R601 input interface, FPGA module and VGA output interface; Wherein,
Described FPGA module comprises: the dynamic random access memory being connected with described ITU-R601 input interface, the deinterleaver being connected with described dynamic random access memory, the resolution interpolation submodule being connected with described deinterleaver, the color space conversion submodule being connected with described resolution interpolation submodule, with the digital to analog converter that described color space conversion submodule is connected, the VGA time schedule controller being connected with described digital to analog converter; Wherein, described color space is changed submodule into RTL;
Described VGA output interface is connected with described VGA time schedule controller.
Above-mentioned image format conversion device, preferred, also comprise:
ITU-R656 input interface, ITU-R1120 input interface and video synchronous separator; Wherein,
Described ITU-R656 input interface is connected with the input of described video synchronous separator respectively with described ITU-R1120 input interface;
The output of described video synchronous separator is connected with described dynamic random access memory.
Above-mentioned image format conversion device, preferred, also comprise:
YPbPr output interface;
Described YPbPr output interface is connected with described digital to analog converter.
Above-mentioned image format conversion device, preferred, described deinterleaver is grouping deinterleaver or RANDOM SOLUTION interleaver.
Above-mentioned image format conversion device, preferred, described dynamic random access memory is Double Data Rate synchronous DRAM.
Known by above scheme, a kind of image format conversion device that the application provides, described ITU-R601 input interface inputs to the dynamic random access memory in FPGA module by the picture signal of ITU-R601 form, deinterleaver is reading images signal from described dynamic random access memory, carry out exporting resolution interpolation submodule to after deinterleaving, resolution interpolation submodule carries out exporting color space conversion submodule to after interpolation processing to the picture signal of described deinterleaver output and carries out color space conversion, from the picture signal of described color space conversion submodule output, after digital to analog converter conversion, export VGA display controller to, VGA display controller control chart image signal is exported from described VGA output interface, realized the image input of ITU-R601 standard, the image format conversion of VGA image output.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of a kind of image format conversion device that Fig. 1 provides for the embodiment of the present application;
The structural representation of the another kind of image format conversion device that Fig. 2 provides for the embodiment of the present application;
The structural representation of another image format conversion device that Fig. 3 provides for the embodiment of the present application;
The structural representation of another image format conversion device that Fig. 4 provides for the embodiment of the present application;
The structural representation of another image format conversion device that Fig. 5 has implemented to provide for the application.
Term " first " in specification and claims and above-mentioned accompanying drawing, " second ", " the 3rd " " 4th " etc. (if existence) are for distinguishing similar part, and needn't be for describing specific order or precedence.The data that should be appreciated that such use suitably can exchanged in situation, so that the application's described herein embodiment can be with the order enforcement except here illustrated.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
Refer to Fig. 1, the structural representation of a kind of image format conversion device that Fig. 1 provides for the embodiment of the present application, comprising:
ITU-R601 input interface 11, FPGA module 12 and VGA output interface 13; Wherein,
Described FPGA (Field Programmable Gate Array, field programmable gate array) module 12 comprises: the dynamic random access memory 121 being connected with described ITU-R601 input interface, the deinterleaver 122 being connected with described dynamic random access memory 121, the resolution interpolation submodule 123 being connected with described deinterleaver 122, the color space conversion submodule 124 being connected with described resolution interpolation submodule 123, the digital to analog converter 125 being connected with described color space conversion submodule 124, the VGA time schedule controller 126 being connected with described digital to analog converter 125,
Described VGA output interface 13 is connected with described VGA time schedule controller 126.
Wherein, described dynamic random access memory 121 can be Double Data Rate synchronous DRAM (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM).
Described deinterleaver 122 can be grouping deinterleaver or RANDOM SOLUTION interleaver.
When the view data of ITU-R601 standard is inputted from ITU-R601 input interface 11, row field information in the view data of ITU-R601 standard is directly as the enable signal of dynamic random access memory 121, and the valid data in the view data of ITU-R601 standard enter dynamic random access memory 121 and carry out buffer memory.Deinterleaver 122 is reads image data from described dynamic random access memory 121, then carries out deinterleaving, and the CbYCrY view data of 4:2:2 form is converted to the YCbCr view data of 4:4:4 form, resolution interpolation submodule 123 corresponding resolution when the resolution of the YCbCr view data of 4:4:4 form being interpolated to VGA and showing according to the resolution of the image of ITU-R601 standard, color space conversion submodule 124 converts YCbCr image data format to rgb image data form, concrete, the register stage RTL circuit that can generate by hardware description language (being again RTL) is realized YCbCr image data format to the conversion of rgb image data form, digital to analog converter 125 converts digital rgb image data format to analog rgb image data format, concrete, can produce analog-to-digital conversion control chip logic by hardware description language and realize digital rgb image data format to the conversion of analog rgb image data format.Described VGA time schedule controller 126 control described analog rgb view data according to pre-set VGA sequential by VGA output interface, be transferred to VGA display and show.
A kind of image format conversion device that the application provides, ITU-R601 input interface inputs to the dynamic random access memory in FPGA module by the picture signal of ITU-R601 form, deinterleaver is reading images signal from described dynamic random access memory, carry out exporting resolution interpolation submodule to after deinterleaving, resolution interpolation submodule carries out exporting color space conversion submodule to after interpolation processing to the picture signal of described deinterleaver output and carries out color space conversion, from the picture signal of described color space conversion submodule output, after digital to analog converter conversion, export VGA display controller to, VGA display controller control chart image signal is exported from described VGA output interface, realized the image input of ITU-R601 standard, the image format conversion of VGA image output.
On basis embodiment illustrated in fig. 1, the structural representation of the another kind of image format conversion device that the embodiment of the present application provides as shown in Figure 2, can also comprise:
ITU-R656 input interface 21, ITU-R1120 input interface 22 and video synchronous separator 23;
Wherein, ITU-R656 input interface 21 is connected with the input of described video synchronous separator respectively with ITU-R1120 input interface 22;
The output of described video synchronous separator 23 is connected with described dynamic random access memory 121.
When the image data stream of ITU-R656 standard passes through ITU-R656 input interface 21 input video sync separator 23, video synchronous separator 23 is carried out separated by the row field information in the image data stream of ITU-R656 standard with valid data, wherein, the output port of the row field information of separating is connected with the write operation Enable Pin of described dynamic random access memory 121, and the row field information of separating enables control signal as the write operation of dynamic random access memory 121; And the output port of the effective information of separating is connected with the input of writing of described dynamic random access memory 121, the effective information of separating is stored in dynamic random access memory 121.
In like manner, when the image data stream of ITU-R1120 standard passes through ITU-R1120 input interface 22 input video sync separator 23, video synchronous separator 23 is carried out separated by the row field information in the image data stream of ITU-R1120 standard with valid data, wherein, the output port of the row field information of separating is connected with the write operation Enable Pin of described dynamic random access memory 121, and the row field information of separating enables control signal as the write operation of dynamic random access memory 121; And the output port of the effective information of separating is connected with the input of writing of described dynamic random access memory 121, the effective information of separating is stored in dynamic random access memory 121.
Preferably, described video synchronous separator 23 can be the Video Sync Separator Chip such as EL1883 chip, GS1881 chip, GS4881 chip or GS4981 chip.
The image format conversion device that the embodiment of the present application provides, can realize the image input of ITU-R601 standard, the image format conversion of VGA image output, can also realize the image input of ITU-R656 standard, the image format conversion of VGA image output, also can realize the image input of ITU-R1120 standard, the image format conversion of VGA image output.
On Fig. 1 or basis embodiment illustrated in fig. 2, the structural representation of another image format conversion device that the application has implemented to provide as shown in Figure 3, can also comprise:
Bayer input interface 31;
Accordingly, described FPGA module 12 can also comprise:
The color interpolation submodule 127 being connected with described Bayer input interface 31;
The selection circuit 128 being connected with described color interpolation submodule 127, described deinterleaver 122 and described resolution interpolation submodule 123 respectively; Preferably, the register stage RTL circuit that described selection circuit 128 can generate by hardware description language is realized the function of described selection circuit.
After Bayer view data is by 31 inputs of Bayer input interface, 127 pairs of Bayer images of color interpolation submodule carry out color interpolation processing, Bayer view data is converted to YUV view data, YUV view data is by selecting circuit 128 to enter resolution interpolation submodule 123, resolution interpolation submodule 123 corresponding resolution when the resolution of YUV view data being interpolated to VGA and showing according to the resolution of YUV view data, color space conversion submodule 124 converts the YUV image data format after resolution interpolation to rgb image data form, digital to analog converter 125 converts digital rgb image data format to analog rgb image data format, VGA time schedule controller 126 control described analog rgb view data according to pre-set VGA sequential by VGA output interface, be transferred to VGA display and show.
The image format conversion device that the embodiment of the present application provides, can also realize the input of Bayer image, the image format conversion of VGA image output.
On basis embodiment illustrated in fig. 3, the structural representation of another image format conversion device that the embodiment of the present application provides as shown in Figure 4, can also comprise:
YUV input interface 41;
Described YUV input interface 41 is connected with described selection circuit 128.
After YUV view data is by 41 inputs of YUV input interface, by selecting circuit 128 to enter resolution interpolation submodule 123, corresponding resolution when the resolution of YUV view data being interpolated to VGA and showing according to the resolution of YUV view data, color space conversion submodule 124 converts the YUV image data format after resolution interpolation to rgb image data form, digital to analog converter 125 converts digital rgb image data format to analog rgb image data format, VGA time schedule controller 126 control described analog rgb view data according to pre-set VGA sequential by VGA output interface, be transferred to VGA display and show.
The image format conversion device that the embodiment of the present application provides, can also realize the input of YUV image, the image format conversion of VGA image output.
Above-described embodiment, preferred, the structural representation of another image format conversion device that the embodiment of the present application provides as shown in Figure 5, can also comprise:
YPbPr output interface 51;
Described YPbPr output interface 51 be connected with described digital to analog converter 125.
In the embodiment of the present application, the analog picture signal being converted to through digital to analog converter 125 exports YPbPr display to through YPbPr output interface 51 and shows.
A kind of image format conversion device that the embodiment of the present application provides, can realize the image format conversion that multiple format input and multi-format are exported.
Above-mentioned explanation to the disclosed embodiments, makes professional and technical personnel in the field can realize or use the utility model.To the multiple modification of these embodiment, will be apparent for those skilled in the art, General Principle as defined herein can, in the situation that not departing from spirit or scope of the present utility model, realize in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (5)
1. an image format conversion device, is characterized in that, comprising:
ITU-R601 input interface, FPGA module and VGA output interface; Wherein,
Described FPGA module comprises: the dynamic random access memory being connected with described ITU-R601 input interface, the deinterleaver being connected with described dynamic random access memory, the resolution interpolation submodule being connected with described deinterleaver, the color space conversion submodule being connected with described resolution interpolation submodule, with the digital to analog converter that described color space conversion submodule is connected, the VGA time schedule controller being connected with described digital to analog converter; Wherein, described color space is changed submodule into RTL;
Described VGA output interface is connected with described VGA time schedule controller.
2. image format conversion device according to claim 1, is characterized in that, also comprises:
ITU-R656 input interface, ITU-R1120 input interface and video synchronous separator; Wherein,
Described ITU-R656 input interface is connected with the input of described video synchronous separator respectively with described ITU-R1120 input interface;
The output of described video synchronous separator is connected with described dynamic random access memory.
3. image format conversion device according to claim 1, is characterized in that, also comprises:
YPbPr output interface;
Described YPbPr output interface is connected with described digital to analog converter.
4. image format conversion device according to claim 1, is characterized in that, described deinterleaver is grouping deinterleaver or RANDOM SOLUTION interleaver.
5. image format conversion device according to claim 1, is characterized in that, described dynamic random access memory is Double Data Rate synchronous DRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320875176.2U CN203722733U (en) | 2013-11-29 | 2013-11-29 | Image format converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320875176.2U CN203722733U (en) | 2013-11-29 | 2013-11-29 | Image format converter |
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| CN203722733U true CN203722733U (en) | 2014-07-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110837719A (en) * | 2019-11-15 | 2020-02-25 | 广州健飞通信有限公司 | Data reference module integration system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110837719A (en) * | 2019-11-15 | 2020-02-25 | 广州健飞通信有限公司 | Data reference module integration system |
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Address after: 4 / F, building 1, No.14 Jiuxianqiao Road, Chaoyang District, Beijing 100020 Patentee after: Beijing Jingwei Hengrun Technology Co.,Ltd. Address before: 100101 Beijing city Chaoyang District Anxiang Beili 11 B block 8 layer Patentee before: Beijing Jingwei HiRain Technologies Co.,Ltd. |
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Granted publication date: 20140716 |
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