JP2917732B2 - Compressed image memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus for compressing and expanding image data, and more particularly to an image compression and expansion apparatus in which the length of encoded data is fixed.

[0002]

2. Description of the Related Art Hitherto, a method of editing encoded image data has been proposed.
No. 0914. FIG. 2 is a functional block diagram of the method disclosed in Japanese Patent Application Laid-Open No. 3-110914. The image memory compresses image data of one screen in a fixed length in block units and is controlled by one control signal. 1
By storing the image data in a bank of image memories and reading and decoding the code data in block units, the image can be edited at the time of decoding.

[0003]

Since the conventional image compression method is configured as described above, when the encoding process and the decoding process of the original image data are simultaneously performed at a high speed,
Access arbitration processing for storing the encoded image data in the image memory and reading the encoded data from the image memory is necessary, making it difficult to continuously realize high-speed processing in real time. There is a problem that it becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to continuously encode and decode image data of a plurality of screens without requiring access arbitration processing of an image memory. With the goal. It is another object of the present invention to perform high-speed storage and reading in an image memory.

[0005]

In order to achieve the above object, an image memory according to the present invention has a structure corresponding to a fixed-length coded data structure, and the image memory stores one color or one screen. A plurality of banks are configured so that the image data storage control unit and the image data read control unit can arbitrarily select one or more banks. If a plurality of banks are selected simultaneously, they can be treated as continuous banks. I do.
Further, the data width when a plurality of banks are selected at the same time is configured to be multiple times. The data line width at this time is configured to be smaller than the bit width of the encoded data.

[0006]

According to the present invention, an image memory capable of efficiently storing fixed-length coded data of an original image and an image memory capable of efficiently reading fixed-length coded data are independently provided as banks. Therefore, high-speed processing can be realized at the same time by performing encoding and decoding in different banks. Further, storage and reading of the encoded data in the image memory can be realized at high speed.

[0007]

[Embodiment 1] FIG. 1 is a block diagram showing the configuration of a compressed image memory control circuit according to the present invention. In this figure, 1 is an image control block, 2 is an encoder for encoding original image data, 3 is a decoder for decoding encoded data, 4a,
4b is a selector for selecting whether to store the encoded data from the encoder 2 in the memory or to send the encoded data from the memory to the decoder 3, and 5 is a 2M × 8 16M DRAM 5
a first bank of encoded data storage memory composed of three stones a to 5c, 6 is a 2M × 8 16M DRAM 6a to 6c
A second bank of encoded data storage memory 7 composed of three stones is an encoder 2, a decoder 3, selectors 4a and 4
b, a control unit that controls the first bank 5 and the second bank 6.

Here, an example is shown in which the original image handles image data corresponding to a capacity of 16 Mbytes per one color of A4 size. The original image data is divided into 4 × 4 16-byte blocks, and one block of image data includes a reference level for designating a representative gradation level representing the gradation level of each pixel in the block, and a block. The fixed length encoding is performed on the difference value indicating the distribution range of the representative gradation in the three-dimensional data and the resolution component indicating the value of the representative gradation of each pixel in the block. Is 6 bytes (48 bits), image memory is A4 per bank
It is composed of two banks 5 and 6 each having a capacity capable of storing one color size. The input / output data width to the image memory per bank is 24 bits, and one bank of image memory is 2M × 8.
The operation will be described based on an example in which the encoding process and the decoding process for one color of the original image data are performed at the same time in the case of three 16M DRAMs.

First, when the A4 size original image data is stored in the first bank 5, the original image data is encoded into 48-bit data by the encoder 2 in units of 4 × 4 blocks. The encoded data is selected by the selector 4a by the control unit 7 and the write signal is supplied to the DRAMs 5a, 5b and 5c each having a data width of 8 bits, and the encoded data is operated twice as a total of 24 bits. Stores 48-bit data.

Next, when reading and decoding A4 size encoded data stored in the first bank 5 and storing the next A4 size original image data in the second bank 6 are performed simultaneously, the encoder The 48-bit coded data coded by the control unit 7 is transmitted from the control unit 7 to the encoder 4 by the selector 4b.
Output side, each having a data width of 8 bits
A write signal is given to AMs 6a, 6b and 6c for a total of 2
48-bit data is stored as 4-bit data in two operations.

At the same time as the operation of storing the encoded data in the second bank 6, the encoded data stored in the first bank 5 is read and decoded. In this operation, the controller 4 selects the read side to the decoder 3 by the selector 4a, and
The coded data of 48 bits per block stored for the AMs 5a, 5b, and 5c are read as 24-bit data by two read operations. Second bank 6
Read and decode the encoded data from the first bank 5
Similarly, the encoding and storage of the next image data to the storage device are performed. The control unit 7 controls the encoder 2 and the decoder 3 not to access the same bank at the same time.

When encoding A3 size image data and storing it in the image memory, the control unit 7 selects both the selector 4a and the selector 4b on the output side of the encoder 2 and the first bank. 5 and DR of both banks 6
A write signal is given to the AM to perform a write process. When reading and decoding encoded data of A3 size stored in the first bank 5 and the second bank 6, the control unit 7 selects both the selector 4 a and the selector 4 b on the read side to the decoder 3. Then, a read operation is performed from both the DRAMs of the first bank 5 and the second bank 6. When handling these A3 size image data, writing from the encoder 2 and reading to the decoder 3 are performed exclusively by the control unit 7 for both banks.

When an image of A3 size is handled, the storage and readout of the coded data for both banks is performed by first selecting the first bank 5 by the control unit 7 and then continuing the second bank 6 after a series of processing is completed. By choice, 2
One bank may be treated as one continuous area, or the first bank 5 and the second bank 6 may be simultaneously selected by the control unit 7 and used as a data line having twice the width of a 24-bit data line. It may be treated as one area having a data width of 48 bits. For example, in the case of storing encoded data, the control unit 7 assigns the upper 24 bits to the first bank 5 and the lower 2 bits to the encoded data of 48 bits per block.
Four bits are stored in the second bank 6 in one write operation.

Embodiment 2 FIG. In the above-described first embodiment, an example in which the image memory is configured by two banks has been described. However, the image memory may be divided into more banks according to the size of encoded data per block. Further, even when two banks are simultaneously selected and the data line width for storing and reading encoded data is doubled and used, the effect can be obtained by dividing into two or more banks. Practically, it is efficient to use two banks.

Embodiment 3 FIG. In the above-described first embodiment, an example is described in which the encoded data of one block of image data is 6 bytes. However, if the size of the encoded data is a fixed length, the block size and the size of the encoded data may be any.

Embodiment 4 FIG. In the first embodiment, when an A4 size image is accessed for each bank, 4
The 8-bit coded data is transferred by a 24-bit data line to 2 bits.
Although an example in which the access is divided into multiple times has been described, a configuration that can be accessed once with a 48-bit width may be used, or a configuration that can be accessed three or more times may be used.

Embodiment 5 FIG. In the above-described first embodiment, the example in which the image memory corresponds to one color has been described.
The processing may be performed for a screen, or the image memories of a plurality of colors may be controlled simultaneously in parallel.

[0018]

As described above, in an image compression / decompression processing apparatus which encodes original image data to a fixed length, temporarily stores the image data in an image memory, and performs editing while reading and decoding the encoded image data, the image data is processed in accordance with the encoded data structure. By taking exclusive image memory configuration and bank configuration and controlling encoding and decoding exclusively for the same bank in the image memory, high-speed simultaneous encoding and decoding without complicated memory control Can be performed. In addition, the image memory configuration and the bank configuration corresponding to the coded data structure are taken, and by controlling a plurality of banks in parallel, the data width of the image memory can be expanded, and the number of accesses to the image memory can be reduced to achieve high-speed processing. It can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a compressed image memory control circuit showing one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional compressed image memory control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image control block 2 Encoder 3 Decoder 4a-4b Selector 5 Encoded data storage memory first bank 5a-5c Encoded data storage DRAM 6 Encoded data storage second bank 6a-6c Code Data storage DRAM 7 control unit

Continued on the front page (72) Inventor Hiroaki Furuta 3-1-1, Chuo, Itami, Mitsubishi Electric Semiconductor Software Corporation (72) Inventor Eisaku Tomita 3-1-1, Chuo, Itami, Mitsubishi Electric Semi-Conductor In Software Co., Ltd. (72) Inventor Masaru Onishi 2-14-40 Ofuna, Kamakura City Mitsubishi Electric Corporation Living System Laboratory (56) References JP-A-1-314070 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H04N 1/21 H04N 1/41-1/419 G06T 1/60

Claims (2)

(57) [Claims] 1. A reference level for dividing original image data into small area blocks, and specifying a representative gray level representing the gray level of each pixel in the block, and a representative gray level in the block. Is fixed-length-encoded into three-component data of a difference value indicating a distribution range of (i) and a resolution component indicating which value of the representative gray level of each pixel in the block.
In an image compression / decompression processing apparatus that stores and reads and decodes component data (hereinafter referred to as encoded data) in an image memory, the image memory stores an area capable of storing image data of one color or one screen by N (N Is an integer equal to or greater than 2) and each area is configured as N independent banks. When N banks are selected, the N banks are defined as a continuous bank of N banks. Means for controlling the number of banks independently when each bank is selected; means for selecting at least one bank when the encoded data is stored in the image memory; Means for selecting at least one or more banks when reading encoded data from the image memory; storing the encoded data in the image memory; Readout of the encoded data, compressed image memory control apparatus characterized by having a means for selecting exclusively to the same bank. 2. A reference level for dividing the original image data into small area blocks and designating a representative gradation level representing the gradation level of each pixel in the block, and a representative gradation in the block. Is fixed-length-encoded into three-component data of a difference value indicating a distribution range of (i) and a resolution component indicating which value of the representative gray level of each pixel in the block.
In an image compression / decompression processing device for storing and reading and decoding component data (hereinafter referred to as encoded data) in an image memory, storing encoded data in the image memory or reading the encoded data from the image memory Is N of the total number of bits of the encoded data per block.
(N is an integer of 2 or more) a data width of 1 /
Means for dividing the image memory into N areas in which image data for one color or one screen can be stored, wherein each area is constituted as N independent banks; Means that N banks can be controlled as a continuous bank when each bank is selected, and N banks can be controlled independently when each bank is selected, and when the encoded data is stored in the image memory. Is at least 1
Means for selecting one or more banks; means for selecting at least one or more banks when reading the encoded data from the image memory; storing the encoded data in the image memory; Means for exclusively selecting the same bank for reading the encoded data from the memory.