JP3005385B2 - Huffman decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Huffman decoding circuit for decoding a Huffman code coded by a Huffman coding method.

[0002]

2. Description of the Related Art Image data contains a very large amount of information. Therefore, it is not practical to process the image data as it is in terms of memory capacity and communication speed. Therefore, image data compression technology becomes important.

[0003] J is one of the international standards for image data compression.
PEG (Joint Photographic Ex)
part group). DCT (Discrete Cosine Transform) for lossy coding and DP in two-dimensional space
A lossless encoding system that performs CM (Differential PCM) is employed. Hereinafter, DCT image data compression will be described.

FIG. 3 is a block diagram showing a basic configuration of a system for executing the DCT method.

On the encoding side, a DCT device 100 performs DCT transform on input original image data, and outputs DCT coefficients. The quantizer 200 includes a quantization table 400
, A quantization process is performed on the DCT coefficient, and a quantized DCT coefficient (hereinafter, referred to as a quantized DCT coefficient) is output. The entropy encoder 300 performs entropy encoding on the quantized DCT coefficients with reference to the encoding table 500, and outputs compressed data. Huffman coding is used as the entropy coding.

On the decoding side, the entropy decoder 600
Performs entropy decoding on the compressed data with reference to the encoding table 500, and outputs quantized DCT coefficients. The inverse quantizer 700 performs an inverse quantization process on the quantized DCT coefficient with reference to the quantization table 400,
Output the T coefficient. The inverse DCT device 800 performs an inverse DCT transform on the DCT coefficient and outputs reproduced image data.

As shown in FIG. 4, each compressed data (code data) is composed of a variable length Huffman code and variable length additional bits. The code length of the Huffman code and the code length of the additional bit differ depending on each compressed data.

FIG. 5 is a block diagram showing a configuration of a main part of a conventional Huffman decoding circuit. Huffman table 1
Consists of a memory circuit having a storage capacity of 2 ^m words. Here, m represents the maximum code length of the Huffman code. As the memory circuit, a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like is used.

Address input terminal A of Huffman table 1
D is supplied with the first m bits of the compressed data as an address signal. Each address in the Huffman table 1 stores decoded data corresponding to the Huffman code represented by that address.

For example, assuming that the maximum code length m of the Huffman code is 16, a 16-bit length Huffman code "1111" is used.
The decoded data corresponding to 111111110101 ″ is
It is stored at the address “1111111111110101”. 15-bit length Huffman code "1111111"
The decoded data corresponding to “11000010” is stored in two addresses “1111111111000010X”, where X represents 0 and 1. The decoded data corresponding to the 2-bit length Huffman code “01” is 2
¹⁴ addresses "01XXXXXXXXXXXXXXXXXX"
Is stored in

As described above, since 16-bit compressed data corresponding to the maximum code length is given to the Huffman table 1 as an address signal, decoded data corresponding to a Huffman code shorter than the maximum code length includes a plurality of addresses. Must be stored in

For example, when the compressed data includes a 2-bit Huffman code "01", the Huffman table 1 is provided with 16-bit compressed data "01 ..." as an address signal. As a result, the decoded data stored at the address “01...” Is read out, and the data output terminal D
Output from O. In this manner, the Huffman code included in the compressed data is decoded.

[0013]

As described above, in the conventional Huffman decoding circuit, the maximum code length m of a Huffman code is m.
Is given to the Huffman table 1 as an address signal, and the memory capacity of the memory circuit constituting the Huffman table 1 requires 2 ^m words. In this case, decoded data corresponding to a Huffman code shorter than the maximum code length m is stored at a plurality of addresses. When the maximum code length is 16 bits, the storage capacity of the memory circuit requires 2 ¹⁶ = 64K words.

As described above, in the conventional Huffman decoding circuit, it is necessary to write extra decoded data to a much larger number of addresses than the number of Huffman codes, and a large-capacity memory circuit is required. As a result, the circuit size of the Huffman decoding circuit increases.

An object of the present invention is to provide a Huffman decoding circuit having a small circuit size.

[0016]

(1) First invention A Huffman decoding circuit according to a first invention is a Huffman decoding circuit for decoding a Huffman code having an arbitrary code length. A length detecting unit, a storing unit, and a selecting unit are provided.

The code length detecting means receives the code data including the Huffman code to be decoded, and detects the code length of the Huffman code to be decoded. The storage means includes a plurality of blocks to which any one of the code lengths of the plurality of Huffman codes is assigned. Each of the plurality of blocks stores decoded data corresponding to the Huffman code having the assigned code length, and receives a predetermined bit of the code data as an address signal.

The selecting means selects one of the plurality of blocks based on the code length detected by the code length detecting means, and outputs decoded data read from the selected block.

(2) Second invention In the Huffman decoding circuit according to the second invention, the storage means includes first to n-th blocks. Each of the plurality of blocks has a storage capacity of 2 ^C words. C represents an integer satisfying the relationship of 2 ^C-1 <A ≦ 2 ^C. A represents the total number of a plurality of Huffman codes. N satisfies the following relationship: n = B−C + 1. B represents the maximum code length of a plurality of Huffman codes.

The first block is assigned a code length of C bits or less, and the ith block is assigned a code length of (C + i-1) bits. i represents an integer from 2 to n.

The first block receives the first to C-th bits of the code data as an address signal. The ith block is from the ith bit of the code data to the (C + i-1) th bit.
Receive the bit as an address signal.

(3) Third invention In the Huffman decoding circuit according to the third invention, the plurality of blocks include the first to n-th blocks. The first block has a storage capacity of 2 ^C words. C represents an integer satisfying the relationship of 2 ^C-1 <A ≦ 2 ^C. A represents the total number of a plurality of Huffman codes. N satisfies the following relationship: n = B−C + 1. B represents the maximum code length of a plurality of Huffman codes. The ith block has a storage capacity of ^2K words. I represents an integer from 2 to n. Wherein K represents an integer satisfying the relationship ^{2 K-1 <A / (} i-1) ≦ 2 K. A / (i-1) represents an integer obtained by truncating the decimal part.

The first block is assigned a code length of C bits or less. The code lengths of the Huffman codes are assigned to the second to n-th blocks based on the number of Huffman codes having the same code length.

The first block receives bits 1 to C of the code data as an address signal.

This Huffman decoding circuit includes bit selection means for selecting K bits of code data based on the code length detected by the code length detection means and providing the selected bit to the second to nth blocks as an address signal. In addition.

[0026]

(1) First invention In the Huffman decoding circuit according to the first invention, the code length of the Huffman code to be decoded is detected by the code length detecting means. In each block of the storage means, an address is specified based on a predetermined bit of the code data, and the corresponding decoded data is read. Then, one of the blocks of the storage unit is selected by the selection unit based on the detected code length, and the decoded data read from the block is output.

Each block of the storage means only needs to store the decoded data corresponding to the Huffman code of the assigned code length, so that the storage capacity of each block is reduced.

(2) Second invention In the Huffman decoding circuit according to the second invention, the storage means includes n blocks, and each block has a storage capacity of 2 ^C words.

The first block is assigned a code length of C bits or less. Since the number of Huffman codes having a code length of not more than C bits is 2 ^C or less, decoded data corresponding to all Huffman codes having a code length of not more than C bits can be stored in the first block.

On the other hand, a code length exceeding C bits is assigned to one block. Since the storage capacity 2 ^{C of} each block is equal to or greater than the total number A of Huffman codes, even if all Huffman codes have the same code length, decoded data corresponding to all Huffman codes is stored in the corresponding block. be able to.

Since the total number A of the Huffman codes is 2 ^C or less, the values of the lower C bits are always different for Huffman codes having the same code length. Therefore, the first
Is given as an address signal from the first bit to the C-th bit of the code data to the block, and from the ith bit to the (C + i-1) th of the code data as the address signal to the i-th block. Can be specified.

(3) Third invention In the Huffman decoding circuit according to the third invention, the storage means includes n blocks, and the first block has a storage capacity of 2 ^C words.

The first block is assigned a code length of C bits or less. Since the number of Huffman codes having a code length of not more than C bits is 2 ^C or less, decoded data corresponding to all Huffman codes having a code length of not more than C bits can be stored in the first block.

Huffman codes exceeding C bits are grouped by the same code length. The ith block is 2
^It has a storage capacity of ^K words.

The second block has a storage capacity of 2 ^K words which satisfies the relationship of 2 ^{K -1} <A ≦ 2 ^K. The code length of the group including the largest number of Huffman codes is assigned to the second block. Thereby, even if the code lengths of all Huffman codes are concentrated on one code length, the decoded data corresponding to all Huffman codes is
Block.

The third block is 2 ^K-1 <A / 2 ≦ 2 ^K
Has a storage capacity of ^2K words that satisfies the relationship Third
Are assigned the code length of the group including the second largest number of Huffman codes. Thereby, when the code lengths of all the Huffman codes are dispersed into two code lengths, the decoded data corresponding to all the Huffman codes can be stored in the second and third blocks.

The fourth block is 2 ^K-1 <A / 3 ≦ 2 ^K
Has a storage capacity of ^2K words that satisfies the relationship 4th
Are assigned a code length of a group including the third largest number of Huffman codes. Thereby, when the code lengths of all the Huffman codes are dispersed into three code lengths, the decoded data corresponding to all the Huffman codes can be stored in the second to fourth blocks.

Similarly, the ith block is 2 ^K-1 <
Having a storage capacity of 2 ^K words satisfying the relation of A / (i-1) ≦ 2 K. The code length of the group including the (i-1) -th largest number of Huffman codes is assigned to the i-th block. Thereby, when the code lengths of all the Huffman codes are dispersed into (i-1) code lengths, the decoded data corresponding to all the Huffman codes are converted to the second to i-th codes.
Block.

Therefore, by selecting the K bits of the code data based on the detected code length and applying the selected bit to the i-th block as an address signal, the corresponding decoded data in the i-th block is specified. Can be.

[0040]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a Huffman decoding circuit according to a first embodiment of the present invention.

This Huffman decoding circuit includes a code length detection circuit 1, a memory circuit 2, and a data selector 3.

The code length detection circuit 1 includes nine comparators 11, 12,..., 19 each having 8 to 16 bits and a priority encoder 10. 8-bit comparator 11
One input terminal is provided with first to eighth bits D0 to D7 of the compressed data, and the other input terminal is provided with a maximum code value M8 of an 8-bit length Huffman code. One input terminal of the 9-bit comparator 12 is supplied with first to ninth bits D0 to D8 of the compressed data, and the other input terminal is supplied with a maximum code value M9 of a 9-bit length Huffman code. Similarly, the 16-bit comparator 19
The first to sixteenth bits D0 to D15 of the compressed data are provided to one input terminal of the
The maximum code value M16 of the bit length Huffman code is given.

Each comparator compares the compressed data supplied to one input terminal with the maximum code value supplied to the other input terminal, and when the value of the compressed data is larger than the maximum code value, outputs "H". And outputs "L" otherwise. The priority encoder 10 includes comparators 11 to 1
9 generates a block selection signal BS in response to the output signal.

If the output signals of the comparators 11 to 19 are "L", the block selection signal BS indicates "1". Comparator 1
If the output signal of "1" is "H" and the output signals of the other comparators 12 to 19 are "L", the block selection signal BS indicates "2". If the output signals of the comparators 11 and 12 are “H” and the output signals of the other comparators 13 to 19 are “L”, the block selection signal BS indicates “3”. Similarly, if the output signals of the comparators 11 to 18 are “H” and the output signal of the comparator 19 is “L”, the block selection signal BS indicates “9”.

The memory circuit 2 has nine blocks BL1, B
L2,..., BL9. Each of the blocks BL1 to BL9 is composed of a 256 word RAM (random access memory).

The block BL1 receives the first to eighth bits D0 to D7 of the compressed data as an address signal. The block BL2 is supplied with second to ninth bits D1 to D8 of the compressed data as an address signal. Similarly, the ninth to sixteenth bits D8 to D15 of the compressed data are supplied to the block BL9 as an address signal.

The block BL1 stores decoded data corresponding to a Huffman code having a code length of 1 to 8 bits. The block BL2 stores decoded data corresponding to a Huffman code having a code length of 9 bits. Similarly, in the block BL9, decoded data corresponding to a Huffman code having a code length of 16 bits is stored. Each decoded data is stored at an address indicated by a corresponding Huffman code.

The data selector 3 selects and outputs one of the decoded data read from the blocks BL1 to BL9 in response to the block selection signal BS generated from the priority encoder 10.

When the block selection signal BS is "1", the data selector 3 selects and outputs the decoded data read from the block BL1. Block selection signal B
When S is "2", the data selector 3
The decoded data read from L2 is selected and output.
Similarly, when the block selection signal BS is “9”, the data selector 3 selects and outputs the decoded data read from the block BL9.

AC in the JPEG baseline method
The total number of Huffman codes is 162, and the total number of AC Huffman codes in the JPEG extension method is 226. Here, considering the extension method, the total number of AC Huffman codes A
Is 226, and the maximum code length B of the Huffman code is 16. Since 2 ⁷ <A ≦ 2 ⁸ , C = 8. Therefore, in this embodiment, the number n of blocks in the memory circuit 2 is n = B−C + 1 = 16−8 + 1 = 9. The storage capacity of each block is 2 ^C = 2 ⁸ = 256 words.

Since the storage capacity of each block is larger than the total number of Huffman codes, no matter how the code length of the Huffman code is distributed, decoded data corresponding to all Huffman codes is stored in the corresponding block in the memory circuit 2. Can be stored.

Since the maximum value of the number of Huffman codes of each code length is 2 ⁸ (= 256) or less, the lower 8 bits of Huffman codes having the same code length do not have the same value. Therefore, the corresponding decoded data can be specified from the code length of the Huffman code included in the compressed data and the value of the lower 8 bits of the Huffman code.

Next, an example of the operation of the Huffman decoding circuit of FIG. 1 will be described. Here, it is assumed that the compressed data includes a 9-bit length Huffman code “111110110”. That is, the first to ninth bits of the compressed data are “111110110”. Also, the maximum code value of the 8-bit length Huffman code is “11111010”,
The maximum code value of the 9-bit length Huffman code is “11111”.
1010. The maximum code value of the 10-bit length Huffman code is "11111111010".

In this case, since the first to eighth bits D0 to D7 of the compressed data are larger than the maximum code value M8 of the 8-bit Huffman code, the output signal of the 8-bit comparator 11 becomes "H". Meanwhile, the first to ninth compressed data
The values of bits D0 to D8 are smaller than the maximum code value M9 of the 9-bit Huffman code. Therefore, the output signal of the 9-bit comparator 12 becomes "L". Similarly, the values of the first to tenth bits D0 to D9 of the compressed data are smaller than the maximum code value M10 of the 10-bit Huffman code. Therefore, the output signal of the 10-bit comparator 13 also becomes “L”.

As a result, it is detected that the code length of the Huffman code included in the compressed data is 9 bits. In this case, the priority encoder 10 sets the block selection signal BS to “2”.

Data selector 3 selects output data of block BL2 in response to the block selection signal BS. The block BL2 is supplied with the second to ninth bits D1 to D8 of the compressed data, that is, the lower 8 bits of the 9-bit length Huffman code as an address signal.
As a result, decoded data corresponding to the 9-bit length Huffman code “111110110” is read from the block BL2 and output via the data selector 3.

In the Huffman decoding circuit of the above embodiment, the storage capacity of the memory circuit 2 is 2304 words, which is about 1/28 of 64K words in the conventional Huffman decoding circuit.

FIG. 2 is a block diagram showing the configuration of the Huffman decoding circuit according to the second embodiment.

This Huffman decoding circuit includes a code length detection circuit 1, a memory circuit 2, a register 4, a selector 5, and a data selector 6. The configuration and operation of the code length detection circuit 1 are the same as the configuration and operation of the code length detection circuit 1 shown in FIG.

The register 4 receives the block selection signal BS generated from the priority encoder 10 as an address signal, and outputs a data selection signal DS. The data selection signal DS is a signal for selecting data corresponding to the code length of the Huffman code from the output data of the memory circuit 2.

The selector 5 has eight input terminals S1 to S8. The second to ninth compressed data are input to the input terminal S1.
Bits D1 to D8 are provided. The input terminal S2 is supplied with the third to tenth bits D2 to D9 of the compressed data. Similarly, the ninth to sixteenth bits D8 to D15 (8-bit data) of the compressed data are input to the input terminal S8.
Is given.

The selector 5 selects and outputs one of the data supplied to the eight input terminals S1 to S8 in response to the block selection signal BS generated by the priority encoder 10.

When the block selection signal BS is "1", the selector 5 does not output any data. When the block selection signal BS is "2", the selector 5 selects and outputs the data of the input terminal S1. Block selection signal B
When S is "3", the selector 5 selects and outputs the data of the input terminal S2. Similarly, when the block selection signal BS is "9", the selector 5 selects and outputs the data of the input terminal S8.

The memory circuit 2 has nine blocks BK1, B
K2,..., BK9. Blocks BK1 and BK2 are 2
It consists of a 56 word RAM. Block BK3, BK4
Consists of a 128 word RAM. Block BK5, B
K6 and BK7 are composed of 64 words of RAM. Block B
K8 and BK9 are composed of 32 words of RAM.

The block BK1 is assigned a code length of 1 to 8 bits. Huffman codes having a code length of 9 to 16 bits are classified into eight groups for each code length. The code length of the group including the largest number of Huffman codes is assigned to the block BK2. The code length of the group including the second largest number of Huffman codes is assigned to the block BK3. Hereinafter, block B
Code lengths are sequentially assigned to K4 to BK9 in an order including a large number of Huffman codes.

Each block stores decoded data corresponding to the Huffman code of the assigned code length. Each decoded data is stored at an address indicated by a corresponding Huffman code.

The block BK1 is supplied with the first to eighth bits D0 to D7 of the compressed data as an address signal. To the blocks BK2 to BK9, data of the bit number of the address of the corresponding block from the least significant bit of the output data (8-bit data) of the selector 5 is given as an address signal.

Data selector 6 responds to data selection signal DS output from register 4 to block BK1.
BK9, and selects and outputs one of the decoded data.

Here, considering the JPEG extension method,
The total number A of AC Huffman codes is 226, and the maximum code length B of Huffman codes is 16. Since 2 ⁷ <A ≦ 2 ⁸ , C = 8. Therefore, in this embodiment, the number n of blocks of the memory circuit 2 is n = B−C + 1 = 16
−8 + 1 = 9. The storage capacity of the block BK1 is 2 ^C = 2 ⁸ = 256 words.

For the block BK2, 2 ⁷ <A ≦ 2
^Since it is ⁸ , the storage capacity is 2 ⁸ = 256 words.
For the block BK3, since 2 ⁶ <A / 2 ≦ 2 ⁷ , the storage capacity is 2 ⁷ = 128 words. For the block BK4, since 2 ⁶ <A / 3 ≦ 2 ⁷ , the storage capacity is 2 ⁷ = 128 words. As for the block BK5, since 2 ⁵ <A / 4 ≦ 2 ⁶ , the storage capacity is 2 ⁶ = 64 words.

For the block BK6, 2 ⁵ <A / 5
Since ≦ 2 ⁶ , the storage capacity is 2 ⁶ = 64 words. As for the block BK7, since ²⁵ <A / 6 ≦ 2 ⁶ , the storage capacity is 2 ⁶ = 64 words. For the block BK8, since 2 ⁴ <A / 7 ≦ ²⁵ ,
The storage capacity is 2 ⁵ = 32 words. As for the block BK9, since 2 ⁴ <A / 8 ≦ 2 ⁵ , the storage capacity is 2 ⁵ = 32 words.

Also in this embodiment, no matter how the code length of the Huffman code is distributed, decoded data corresponding to all Huffman codes can be stored in corresponding blocks in the memory circuit 2.

Further, the corresponding decoded data can be specified from the code length of the Huffman code included in the compressed data and the value of the lower 8 bits of the Huffman code.

Next, an example of the operation of the Huffman decoding circuit of FIG. 2 will be described. For example, the number of Huffman codes having a code length of 16 bits is the largest, the number of Huffman codes having a code length of 9 bits is the second largest, and the number of Huffman codes having a code length of 10 bits is the third largest. Shall be.

In this case, the block BK2 is assigned a code length of 16 bits, the block BK3 is assigned a code length of 9 bits, and the block BK4 is assigned a code length of 10 bits.

When the given compressed data includes a Huffman code of 8 bits or less, the block selection signal BS indicates "1". In this case, the selector 5 does not supply output data. In addition, the data selector 6 selects the block BK1
And selects and outputs the decrypted data read from.

When the given compressed data includes a 9-bit Huffman code, the block selection signal BS indicates "2". As a result, the selector 5 sets the input terminal S
1 is selected and output. At this time,
The data selector 6 selects and outputs the decoded data read from the block BK3.

When the given compressed data includes a 16-bit Huffman code, the block selection signal BS indicates “9”. As a result, the selector 5 sets the input terminal S
8 is selected and output. At this time,
The data selector 6 selects and outputs the decoded data read from the block BK2.

In the Huffman decoding circuit of the above embodiment, the storage capacity of the memory circuit 2 is 1024 words, which is 1/64 of 64K bits in the conventional Huffman decoding circuit.
Becomes

When the first embodiment is compared with the second embodiment, the storage capacity of the memory circuit 2 is smaller in the second embodiment, and the processing speed is faster in the first embodiment. .

[0081]

As described above, according to the present invention, each block of the storage means is assigned one of the code lengths of the Huffman code, and only the decoded data corresponding to the Huffman code of the assigned code length is stored. Since the data is stored, the storage capacity and the circuit scale of the storage unit are reduced. Therefore,
A Huffman decoding circuit having a small circuit scale is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a Huffman decoding circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a Huffman decoding circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a basic configuration of a DCT-based image data compression system.

FIG. 4 is a diagram showing a configuration of compressed data.

FIG. 5 is a block diagram showing a configuration of a main part of a conventional Huffman decoding circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Code length detection circuit 2 Memory circuit 3, 6 Data selector 4 Register 5 Selector 10 Priority encoder 11-19 Comparator BL1-BL9, BK1-BK9 block In each figure, the same code shows the same or equivalent part.

Claims (3)

(57) [Claims] 1. A Huffman decoding circuit for decoding a Huffman code having an arbitrary code length, comprising: receiving code data including a Huffman code to be decoded;
A code length detection unit that detects a code length of the Huffman code to be decoded, and a storage unit that includes a plurality of blocks to which any one of the plurality of Huffman codes is assigned, and the plurality of blocks. Each stores decoded data corresponding to the Huffman code of the assigned code length, and receives a predetermined bit of the code data as an address signal, based on the code length detected by the code length detection means, A Huffman decoding circuit, further comprising a selection unit that selects one of the plurality of blocks and outputs decoded data read from the selected block. 2. The storage means includes first to n-th blocks, each of the plurality of blocks has a storage capacity of 2 ^C words, and C is 2 ^C-1 <A ≦ 2 ^C A represents an integer satisfying the relationship, A represents the total number of the plurality of Huffman codes, n represents a relationship of n = B−C + 1, and B represents a maximum code length of the plurality of Huffman codes. The first block is assigned a code length of C bits or less, the i-th block is assigned a code length of (C + i-1) bits, and i represents an integer from 2 to n. One block receives the first to C-th bits of the code data as an address signal, and the i-th block receives the (C + i −)-th bit from the i-th bit of the code data.
The Huffman decoding circuit according to claim 1, wherein 1) receiving the bit as an address signal. 3. The plurality of blocks include first to n-th blocks, wherein the first block has a storage capacity of 2 ^C words, and C has the following condition: 2 ^C-1 <A ≦ 2 ^C Represents an integer satisfying the relationship, A represents the total number of the plurality of Huffman codes, n represents a relationship of n = B−C + 1, and B represents a maximum code length of the plurality of Huffman codes. , The i-th block has a storage capacity of 2 ^K words, wherein i represents an integer from 2 to n;
Represents an integer that satisfies the relationship of 2 ^{K -1} <A / (i-1) ≤ 2 ^K , A / (i-1) represents an integer truncated to a decimal point, and the first block has C A code length equal to or less than a bit is allocated, and a code length of a Huffman code is allocated to each of the second to n-th blocks based on the number of Huffman codes having the same code length. The first to C-th bits of the data are received as an address signal, and the K bits of the code data are selected based on the code length detected by the code length detection means, and are selected for the second to n-th blocks. 2. The Huffman decoding circuit according to claim 1, further comprising bit selection means for giving as an address signal.