JP3291070B2 - Data transposition equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transposition apparatus provided in an image processing apparatus such as a facsimile apparatus and used for two-dimensional orthogonal transformation of color image data.

2. Description of the Related Art In an image processing apparatus, image data read by an image scanner is converted into encoded data by an encoding process and then stored in a storage unit. The encoding of the image data is performed as follows. First, the image data is divided into processing blocks composed of an N × N pixel matrix. Next, a two-dimensional orthogonal transform process such as a discrete cosine transform is performed for each image data in each of the divided processing blocks. Next, the coefficient data obtained by the two-dimensional orthogonal transformation process is quantized using a predetermined threshold value. Next, the quantized coefficient data is encoded with reference to the Huffman encoding table. Here, the two-dimensional orthogonal transform is N ×
By performing one-dimensional orthogonal transformation (discrete cosine transformation) in the column direction (or row direction) on the image data divided into the N pixel matrix, and then performing one-dimensional orthogonal transformation (discrete cosine transformation) in the row direction (or column direction). Be executed.

[0003] The process of decoding code data into image data is executed as follows. First, code data is decoded by Huffman decoding to obtain quantized coefficient data. Next, the obtained quantized coefficient data is inversely quantized into coefficient data. Next, the coefficient data is divided into processing blocks each composed of an N × N pixel matrix. A two-dimensional orthogonal transformation process such as an inverse discrete cosine transform is performed on the divided coefficient data. The image data for each processing block obtained by the two-dimensional orthogonal transformation is converted into continuous image data, and is output to, for example, a display. here,
In the two-dimensional orthogonal transformation, the coefficient data divided into an N × N pixel matrix is subjected to a one-dimensional orthogonal transformation (an inverse discrete cosine transformation) in a column direction (or a row direction), and then to a one-dimensional transformation in a row direction (or a column direction). This is performed by performing an orthogonal transform (inverse discrete cosine transform).

As described above, in the two-dimensional orthogonal transformation, after the input image data or coefficient data composed of an N × N pixel matrix is one-dimensionally orthogonally transformed in the column direction (or the row direction), the two-dimensional orthogonal transformation is performed. Direction) by performing one-dimensional orthogonal transformation. In order to execute the above processing, for example, data dn obtained by one-dimensional orthogonal transformation of an 8 × 8 pixel matrix as shown in FIG. 2 is stored in a memory as d0, d1, d2, d3,.
After temporarily storing data in the row direction as d4,..., data from the memory is stored in the column direction as d0, d8, d16, d24, d32,.
(Japanese Unexamined Patent Publication No. 4-531).

[0005]

However, in the above device,
Writing / reading of data composed of an 8 × 8 pixel matrix is executed in units of data of one pixel for one cycle of the reference clock signal. Therefore, the speed of the data transposition process is low.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data transposing apparatus capable of efficiently and quickly transposing data.

[0007]

According to a first aspect of the present invention, there is provided a data transposition apparatus, comprising: an input terminal to which data constituting the N × N pixel matrix is sequentially input as serial data; The serial data
A first parallel data consisting of data for a plurality of adjacent pixels
A serial / parallel conversion means for converting data into data, and a plurality of memory areas each having a matrix-shaped address array and equally dividing and storing the data constituting the N × N pixel matrix. The data forming the first parallel data is written to an address specified by an address signal sequentially input from the storage device, and the storage means reads data from the similarly specified address, and forms the storage means. Control means for switching each memory area so that data can be written and data can be read at a predetermined timing; and address generating means which operates in units of one cycle of a reference clock signal and generates address signals used for writing and reading data in each memory area. And the reference clock signal 1
For each cycle, the data for a plurality of pixels constituting the first parallel data is written in each of the writable memory areas in one of the row direction and the column direction. While outputting an address signal Ai, j designating the address of the i-th row and the j-th column in each memory area, a plurality of pixels constituting the second parallel data written in each of the memory areas per one cycle of the reference clock signal. Is read from each readable memory area in a direction orthogonal to the direction in which each piece of data constituting the first parallel data is written.
Address generating means for outputting an address signal Aj, i designating an address in a row i column, an address decoder for outputting the address signals Ai, j and Aj, i generated by the address generating means to each of the memory areas, Parallel serial conversion means for converting the second parallel data consisting of data for a plurality of pixels read from each memory area into serial data and outputting the serial data. It is.

According to a second aspect of the present invention, there is provided a data transposition apparatus.
An input terminal to which data constituting the N × N pixel matrix is sequentially input as serial data, and serial data input to the input terminal into first parallel data composed of data of two adjacent pixels. First, second, third, and fourth serial / parallel conversion means for converting, and a matrix-shaped address array, each of which equally divides and stores data constituting the N × N pixel matrix.
In each memory, data constituting the first parallel data is written to an address specified by an address signal sequentially input from the outside, and data is read from the similarly specified address. Means for enabling the first and third memory sets and the second and fourth memory sets to be alternately writable at a predetermined timing, while the first and second memory sets and third and Control means for enabling the fourth memory set to be alternately read at a predetermined timing; and address generating means for operating in units of one cycle of the reference clock signal and generating address signals used for data writing and reading of each memory. The data of two pixels constituting the first parallel data is written in each cycle of the reference clock signal. Each of the first and third sets of memories and the second and fourth sets of memories is sequentially written in one of a row direction and a column direction. While outputting an address signal Ai, j designating the address of the i-th row and the j-th column in the memory, the data of two pixels constituting the second parallel data written in each memory per one cycle of the reference clock signal is: From the set of the first and second memories and the set of the third and fourth memories, which are readable, respectively, in the direction orthogonal to the direction in which each data constituting the first parallel data is written. Address generating means for outputting an address signal Aj, i for designating the address of the j-th row and the i-th column in each of the memories and the first parallel data; At the time of writing each data, the address signal Ai, j generated by the address generating means for one cycle of the reference clock signal is transferred to the set of the first and third memories and the set of the second and fourth memories. , While the second
When reading each data constituting the parallel data, the address signal Aj, i generated by the address generating means per one cycle of the reference clock signal.
An address decoder for sequentially outputting to the first and second memory sets and the third and fourth memory sets,
The second parallel data consisting of data for two pixels read from one of the first and second memory sets and the third and fourth memory sets is converted into serial data and output. And a parallel-to-serial converter.

According to a third aspect of the present invention, there is provided a data transposition apparatus.
An input terminal to which data constituting the N × N pixel matrix is sequentially input as serial data, and serial data input to the input terminal into first parallel data composed of data of two adjacent pixels. A serial / parallel conversion means for converting, and a plurality of memory areas each having a matrix-shaped address array and equally dividing and storing the data constituting the N × N pixel matrix, are sequentially stored in each recording means from the outside. First storage means for writing data constituting the first parallel data at an address specified by an input address signal, and reading data from the similarly specified address; and a matrix-like address array With
It comprises a plurality of memory areas for equally dividing and storing data constituting the N × N pixel matrix, and in each recording means, configures the first parallel data at an address specified by an address signal sequentially input from the outside. And the second storage means from which data is written and the data is read from the similarly designated address, and one of the first and second storage means is made writable, while the other is made readable. And an address generating means which operates in units of one cycle of the reference clock signal and generates address signals used for writing and reading data in the memory area constituting each of the storage means,
For one cycle of the reference clock signal, two pixels of data constituting the first parallel data are stored in the row direction and the column, respectively, in one of the memory areas of the first and second storage means. At the same time as outputting an address signal Ai, j designating the address of the i-th row and the j-th column in each memory area so as to be sequentially written in one of the directions, the other one of the first and second storage means is , J rows in each memory area such that data for two pixels constituting the second parallel data is read from the storage means in a direction orthogonal to the direction in which the first parallel data is written. address generating means for outputting an address signal Aj, i designating the address of the i-th column, and an address signal Ai, j output from the address generating means, The address signal Aj, i output from the address generation means can be read out by the control means at the same time as the data is output to each one of the first and second storage means made writable by the means. An address decoder for outputting to the other of the first and second storage means and data for two pixels read from each memory area of one of the first and second storage means. Parallel-to-serial conversion means for converting the second parallel data into serial data and outputting the serial data.

According to a fourth aspect of the present invention, there is provided a data transposing apparatus.
An input terminal to which data forming the N × N pixel matrix is sequentially input as serial data, and serial data input to the input terminal into first parallel data composed of data of two adjacent pixels. A serial-parallel conversion means for converting, and a plurality of memory areas each of which has a plurality of addresses arranged in a matrix and stores the data constituting the N × N pixel matrix in equal parts. Data is written to an address specified by an address signal sequentially input from the outside, and storage means for reading data from the similarly specified address. Generating an address signal used for writing and reading data in each memory area constituting the means; Address generating means for writing two pixels of data constituting the first parallel data sequentially into one of a row direction and a column direction in a writable memory area; Outputs an address signal Ai, j designating the address of the i-th row and the j-th column in the memory area. On the other hand, the data of two pixels constituting the second parallel data written in each of the memory areas are respectively And outputting an address signal Aj, i designating the address of the j-th row and the i-th column in each of the memory areas so as to be read from the readable memory area in a direction orthogonal to the direction in which the first parallel data is written. Address generating means for outputting the address signals Ai, j and Aj, i generated by the address generating means to the memory area. First, each memory area of the storage means is made writable, and data for an N × N pixel matrix is stored, and then each memory area of the storage means is written in one cycle of the reference clock signal. Read / write control means for reading out one piece of data from each memory area of the storage means and then writing new data to the same address as when the data was read out; and each memory area of the storage means And parallel-to-serial conversion means for converting the second parallel data composed of the data for two pixels read from the second into serial data and outputting the serial data.

[0011]

When data of an N × N pixel matrix is input to an input terminal of the data transposition device according to claim 1, the serial / parallel conversion means converts the input data to a plurality of pixels. Data is converted to first parallel data. The control means makes each memory area of the storage means writable. Accordingly, the address decoder outputs the address signal A output from the address generation means.
i and j are output to the storage means. First parallel data is written to each memory area of the storage means at an address specified by the address signal Ai, j. After the data of the N × N pixel matrix is stored in the storage unit, the control unit makes each memory area of the storage unit readable. Accordingly, the address decoder outputs the address signal Aj, i output from the address generation means to the storage means. From each memory area of the storage means, an address signal A
The second parallel data stored at the address specified by j and i is read. The parallel-to-serial conversion means is configured to read the second data read from each memory area of the storage means.
Converts parallel data to serial data and outputs.

When data of an N × N pixel matrix is input to an input terminal of the data transposition device according to the second aspect, the serial / parallel conversion means converts the input data from data of two pixels. Into the first parallel data. The control means enables the first and third memory areas and the second and fourth memory areas to be written at a predetermined timing. When the first and third memory areas are writable by the control means, the address decoder alternately outputs the address signals Ai, j output from the address generation means to the first and third memory areas. I do. Further, when the second and fourth memory areas are set to be writable by the control means, the address decoder
Address signal Ai, j output from address generation means
Are alternately output to the second and fourth memory areas. First to first
In the fourth memory area, the parallel data is written to the address specified by the address signal Ai, j output from the address generation means. N in the first to fourth memory areas
After the data for the × N pixel matrix is stored, the control unit makes the first and second memory areas and the third and fourth memory areas readable at a predetermined timing. When the first and second memory areas are readable by the control means, the address decoder alternately outputs the address signals Aj, i output from the address generation means to the first and second memory areas. . When the third memory area and the fourth memory area are readable by the control means, the address decoder alternately transfers the address signals Aj, i output by the address generation means to the third and fourth memory areas. Output. The first to fourth memory areas are:
Address signals Aj,
The data for two pixels stored at the address specified by i is read as second parallel data. The parallel-serial conversion means converts the second parallel data into serial data and outputs the serial data.

When serial data of an N × N pixel matrix is input to the input terminal of the data transposition device according to the third aspect, the serial / parallel conversion means converts the input serial data into two pixels. Is converted into first parallel data composed of minute data. The control means includes:
Is writable, and the second storage means is readable. Accordingly, the address decoder outputs the address signal A output from the address generation means.
i, j is output to the first storage means, and the address signal Aj, i is output to the second storage means. The first storage means stores the first parallel data at an address specified by the address signal Ai, j. Since no data is stored in the second storage means, the address signal A
Nothing is read for the inputs of j and i. After the data of the N × N pixel matrix is stored in the first storage unit,
The control unit makes the first storage unit readable and the second storage unit writable. Accordingly, the address decoder outputs the address signal Aj, i output from the address generation means to the first storage means, and outputs the address signal Aj, i output from the address generation means.
i and j are output to the second storage means. The first storage unit reads out data of two pixels stored at an address specified by the address signal Aj, i as second parallel data. The second storage writes the first parallel data to an address specified by the input address signal Ai, j. The second parallel data read from the first storage is converted into serial data by the parallel-serial converter and output.

When data of an N × N pixel matrix is input to the terminal of the data transposition device according to the fourth aspect, the serial / parallel conversion means converts the input data to data of two pixels. Convert to 1 parallel data. The control means makes each memory area of the storage means writable. Accordingly, the address decoder outputs the address signal Ai, j output from the address generation means to each memory area of the storage means. Each memory area stores the first parallel data at an address specified by the address signal Ai, j. Once the storage means is N ×
After the data for the N pixel matrix is stored, the control means makes each memory area of the storage means readable / writable during one cycle of the reference clock signal. The address decoder outputs an address signal Aj, i output from the address generation means to each memory area of the storage means. When the control means allows the storage means to write data, the address signals Aj, Aj,
The second parallel data composed of the data for two pixels stored at the address specified by i is read. When each memory area of the storage means is writable by the control means, new first parallel data is written into each memory area at an address specified by the address signal Aj, i from which the data has been read. . The parallel-serial conversion means converts the second parallel data read from each memory area into serial data and outputs the serial data.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transposition apparatus according to the present invention has a plurality of registers at a data input terminal, converts serial data input to the terminal into parallel data composed of data of a plurality of predetermined pixels, The parallel data is stored in a memory in one cycle of a clock signal. As a result, data is transposed at several times the speed of one cycle of the reference clock signal as compared with the conventional device. First
The data transposition apparatus of the embodiment has two registers at the input terminal, and writes parallel data composed of data for two pixels to the memory in one cycle of the reference clock signal. After data is written to the memory, the reference clock signal 1
Data for two pixels is transposed and output in a cycle. In a modification of the first embodiment, data stored in the row direction is transposed and read in the column direction, and new data is sequentially stored at the address from which the data was read. This completes the reading of all the data stored in the row direction and the writing of new data in the memory in the column direction. In reading the next data, the data stored in the column direction is read from the row direction, and another new data is sequentially stored at the address from which the data was read. Thus, data for two pixels can be written and transposed data can be read in one cycle of the reference clock signal. Further, the data transposition device of the second embodiment has two registers at the input terminal, a memory having twice the capacity of the data to be transposed, and stores the data in one memory when writing the data to the other memory. The read data is read. As a result, data for two pixels can be written and transposed data can be read in one cycle of the reference clock signal as compared with the conventional example. Hereinafter, the data transposition apparatus of the present invention will be described.

(1) First Embodiment FIG. 1 is a diagram showing a configuration of a data transposition apparatus 100 according to the present invention. The data transposition device 100 includes registers 101 and 102 for outputting serially input data as parallel data composed of data for two pixels, and N × N registers.
When image data of an N pixel matrix is input, (N
.Times.N) / 4 register files 103 to 106 for storing data for 4 pixels, and an address generator for generating one N / 2-bit address signal in one cycle of the reference clock signal and outputting it to the address decoder 107. 108 and the register files 103 to 106 include the address generator 10
8 comprises an address decoder 107 for outputting an address signal inputted from the register file 8, a register 110 and a multiplexer 111 for converting parallel data outputted from each of the register files 103 to 106 into serial data, and a read / write control unit 109. Is done. In the present embodiment, image data composed of an 8 × 8 pixel matrix is used. Therefore, the register files 103 to 106
Are used which can store data for 16 pixels each.

The data transposing apparatus 100 stores serial data of an 8 × 8 pixel matrix arranged in a row direction as shown in FIG. 2 in d0, d1, d2, d3..., Dn,.
They are input in the order of d63. Here, the value of n of the data dn indicates a data number. The data input to the device 100 is stored in registers 101 and 102 at <d0, d1>, <d
2, d3>,... Are converted into parallel data composed of data for two pixels. Next, in order to change the data array from the row direction to the column direction, a process of writing the parallel data into the register files 103 to 106 is executed. First, a control signal is output from the read / write control unit 109 to each of the register files 103 to 106 so that the register files 103 to 106 are set in a writable state. The register files 103 to 106 in a writable state include 4-bit address signals Ai,
The data dn is stored at the address specified by j (see FIG. 3).

A 4-bit address signal output from the address decoder 107 to the register files 103 to 106 is generated by an address generator 108. FIG.
3 is a configuration diagram of the address generator 108. The address generator 108 has two 2-bit counters 150 and 15
1 and the 4-bit address signals Ai, j and Aj, i are configured by combining the 2-bit signals i and j output from each counter using the switching gate 152. The reference clock signal is input to the 2-bit counters 150 and 151. The address generator 108 outputs one address signal in one cycle of the input reference clock signal. The counter 150 outputs a 2-bit address signal j (a2, a3). The counter 151 outputs a 2-bit address signal i.
(A0, a1) is output. Address generator 108
Constitutes 4-bit address signals Ai, j and Aj, i by combining the 2-bit address signals i and j. By switching the switching gate 152 shown in FIG. 5, the 4-bit address signal output from the address generator 108 is Ai, j = (a0, a1, a2, a
3) and Aj, i = (a2, a3, a0, a1). The relationship between these two address signals corresponds to the one obtained by exchanging the row address and the column address in the register files 103 to 106. For example, when the address signal i (a0, a1) is (1, 1) and the address signal j (a2, a3) is (0, 0), the address generator 108 switches Ai, j = (1100) address signal and Aj, i =
An address signal (0011) is output. As can be understood from FIG. 3, the addresses (0011) and (1100) correspond to the addresses in which the row / column addresses are interchanged. When writing data, the address generator 108 generates an address signal Ai, j = (a0, a1, a2, a
3) is output. When data is read, an address signal Aj, i = (a2, a3, a0, a1) is output.

Specifically, first, the address decoder 10
7 outputs four address signals Ai, j = (0000) to (0011) to the register files 103 and 105. The register files 103 and 105 that have received the address signal Ai, j store the <d0, d1>, <d2, d
3>, <d4, d5>, and <d6, d7>. Therefore, register files 103 and 105
The received data is stored in the column direction as shown in FIG. Next, the address decoder 107 outputs the four address signals Ai,
j = (0000) to (0011) are output. Register files 104 and 1 receiving address signal Ai, j
06 is <d8, d9>, <d10, d11>, <d8, d9> from the registers 101 and 102 at the corresponding address position.
d12, d13> and <d14, d15>. Therefore, register files 104 and 106
The received data is stored in the column direction as shown in FIG. The address decoder 107 has a register 1
Each time four (8 pixels) parallel data is output from the registers 01 and 102, the register files 103 and 10 are output.
5, and the address signals Ai, j = (0100) to (0111) and Ai, j = (1
000)-(1011) and Ai, j = (1100)-
(1111) is output.

When 16 data are stored in each of the register files 103 to 106 as shown in FIG. 4, the read / write control unit 109 next sends a control signal to the register files 103 to 106. Is output to make it readable. In the register files 103 to 106 which can be read, the address decoder 1
The data of the address corresponding to the address signal output from 07 is output to the next register 110. The address value output from the address decoder 107 is generated by an address generator 108. As described above, when reading data, the address generator 108
An address signal Aj, i = (a2, a3, a0, a1) is output. When the register files 103 to 106 are in a readable state, first, the address decoder 107
The four address signals Aj, i = (0000), (010
0), (1000), and (1100) are output to the register files 103 and 104. In response to the input of the four address signals Aj, i, register files 103 and 10
From four, four (eight pixels) parallel data <d
0, d8>, <d16, d24>, <d32, d40
>, <D48, d56> are read out to the register 110. The address decoder 107 stores the register file 10
4 parallel data from 3 and 104 (8 pixels)
After the output, the four address signals Aj, i = (0000), (010) are stored in the register files 105 and 106.
0), (1000), and (1100) are output. On the other hand, from the register files 105 and 106, four (for eight pixels) parallel data <d1, d9>, <d
17, d25>, <d33, d41>, <d49, d5
7> is read out to the register 110. Thereafter, the address decoder 107 stores the register files 103 and 1
05, and the address signals Aj, i = (0001), (0101), (100
1) and (1101) are output in the above procedure. Further, the address decoder 107 stores the register files 103 and 1
05 and four address signals Aj, i = (0010), (0110), (1
010) and (1110) are output in the above procedure. Furthermore,
The address decoder 107 sends the address signals Aj, i = (0011), (0111), (10) to the register files 103 and 105 and the register files 104 and 106.
11) and (1111) are output in the above procedure.

Each parallel data output to the register file 110 is converted into serial data by the multiplexer MUX 111 and output. By executing the above processing, as shown in FIG. 6, data in which the rows and columns of the input data are replaced is output. As described above, the data transposition apparatus 100 can process two data in one cycle of the reference clock signal, so that the processing speed can be doubled as compared with the related art.

In the above embodiment, the data dn is once stored in all the register files 103 to 106, and then the data dn is read by exchanging the row address and the column address. However, the data transposition method is not limited to this. Not done. This is because the gist of the present invention is to provide a plurality of registers at the data input terminal, convert input serial data into predetermined parallel data, and increase the number of data processed in one cycle of the reference clock signal.

(2) Modification of First Embodiment As a method of transposing data, the following method can be considered in addition to the method described in the first embodiment. In the data transposition apparatus 100 shown in the first embodiment, after the data input to the input terminal is converted into parallel data composed of data of two pixels, the data stored in the address (0000) of the register file 103 d0 is read, and new data d is stored in the address (0000).
0 'is stored. The data d8 stored at the address (0000) of the register file 104 is read, and new data d1 'is stored at the address (0000).
Is stored. Next, the data d16 stored at the address (0100) of the register file 103 is read, and new data d2 ′ is stored at the address (0100). Address of register file 104 (010
0), read out the data d24 stored in
The new data d10 'is stored at the address (0100). The above processing is performed by register files 103 and 10
After executing for each of the eight pixels of data of 4,
The same process is performed on the data of eight pixels in the register files 105 and 106. By repeating this, new data dn 'is stored in the register files 103 to 106 in the row direction as shown in FIG.

Next, when reading data, the data for each of the four pixels in the register files 103 and 105 are written in the column direction in the order of <d0 ', d8'>, <d16 ', d24'>,
<D32 ', d40'> and <d48 ', d56'> are read, and new data <d0 ", d1">, <d
2 ", d3">, <d4 ", d5">, <d6 ", d
7 ″> in the column direction, and then register file 104
And 106 in the column direction by <d1 ′, d9 ′>, <
d17 ′, d25 ′>, <d33 ′, d41>, <d4
9, d57> and new data <d
8 ", d9">, <d10 ", d11">, <d1
2 ", d13">, <d14 ", d15"> are written in the column direction. By repeating this process, each data dn ″ is stored in the register files 103 to 106 in the same arrangement as that shown for dn ′ in FIG.

By performing the above-described processing, data for two pixels can be written to and read from the memory in one cycle of the reference clock signal, and the data can be transposed at four times the speed of the related art.

(3) Second Embodiment FIG. 8 shows a data transposing apparatus 20 according to a second embodiment of the present invention.
Indicates 0. The data transposition apparatus 200 is a data transposition apparatus 1
00 has four register files 103 to 10
A total of eight register files, twice as large, are provided. The data transposition apparatus 200 stores the register file 203
During the period in which the data is written to the remaining register files 207 to 210, the data stored in the remaining register files 207 to 210 are subjected to row / column conversion and output. The data transposition apparatus 200 includes registers 201 and 202 for converting serially input data into parallel data composed of data for two pixels, and (N × N) when image data of an N × N pixel matrix is input. 8) register files 203 to 210 for storing data of / 4 pixels
An address generator 212 that generates an N / 2-bit address signal and outputs it to the address decoder 211, and an address decoder 211 that outputs an address signal input from the address generator 212 to the register files 203 to 210. The read / write controller 213 includes a register 214 and a multiplexer 215 for converting parallel data output from the register files 203 to 210 into serial data. In the second embodiment, image data composed of an 8 × 8 pixel matrix is used as in the first embodiment. Therefore, the register files 203 to 210 are each capable of storing data for 16 pixels.

[0027] As shown in FIG.
Has twice as many register files as the data transposition apparatus 100. In the data transposition apparatus 100 shown in the first embodiment, two data are stored in each register file in one cycle of the reference clock signal. After storing all the data, the data transposition apparatus 100 outputs the data subjected to row / column conversion in one cycle of the reference clock signal as serial data. On the other hand, in the data transposition apparatus 200, data is stored in the register files 203 to 206 in the column direction in the same manner as in the first embodiment, in synchronization with the rising timing of the reference clock signal.
The data stored in the register files 207 to 210 is read in the row direction in synchronization with the falling timing of the reference clock signal. Also, register files 203 to 20
6, when all the data stored in the register files 207 to 210 are output, the data is stored in the register files 207 to 210 in the column direction, and the register files 203 to 20 are stored.
6 is read out in the row direction and output. By performing the above processing, four times as much data can be transposed as in the prior art during one cycle of the reference clock signal.

[0028]

The data transposition apparatus of the present invention has a plurality of registers at the data input terminal, converts input serial data into parallel data,
In the cycle, the parallel data is written to a memory (register file). For this reason, the speed of the data transposition process can be improved several times as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transposition apparatus 100 of the present invention.

FIG. 2 is a diagram showing an array of data dn composed of an 8 × 8 pixel matrix input to a data transposition apparatus.

FIG. 3 shows register files 103 to 106 and 203
Address of ~ 210

4 is a diagram showing data dn stored in register files 103 to 106 provided in the data transposing apparatus 100. FIG.

FIG. 5 is a diagram showing a configuration of an address generator 108.

FIG. 6 shows 8 × 8 output from data transposition apparatus 100
FIG. 3 is a diagram showing an array of data dn formed of a pixel matrix.

FIG. 7 is a diagram showing data dn ′ stored in register files 103 to 106 according to a modification of the first embodiment of the present invention.

FIG. 8 is a configuration diagram of a data transposition apparatus 200 of the present invention.

[Description of References] 101, 102, 110, 201, 202, 214 ... Registers 103 to 106, 203 to 210 ... Register files 107 and 211 ... Address decoders 108 and 212 ... Address generators 109 and 213 ... Read / write control unit 111, 215: multiplexer 150, 151: 2-bit counter 152: switching gate

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-6-70305 (JP, A) JP-A-62-267168 (JP, A) JP-A-2-26476 (JP, A) JP-A-2- 26477 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 1/41-1/419 G06F 17/14 G06T 1/20 H04N 7/30

Claims (4)

(57) [Claims] 1. A data transposition device for replacing a row and a column of data forming an N × N pixel matrix, comprising: an input terminal to which data forming the N × N pixel matrix is sequentially input as serial data; Serial-parallel conversion means for converting serial data input to the terminal into first parallel data composed of data of a plurality of adjacent pixels; and a matrix-like address arrangement.
A plurality of memory areas for equally dividing and storing data forming the N pixel matrix, and in each memory area, data forming the first parallel data at an address specified by an address signal sequentially input from the outside. Is written, and data is read from an address designated in the same manner. A control means for switching each memory area constituting the storage means to be writable and readable at a predetermined timing; and a reference clock. Address generating means for operating in units of one signal cycle to generate address signals used for writing and reading data in each memory area, wherein a plurality of pixels constituting the first parallel data are provided for one cycle of a reference clock signal Each writable memory Relative frequency, as written in one of the row direction and the column direction, the address signal A to the address of row i and column j in the above memory area
i and j are output, and the second parallel data written in each of the above memory areas is output for each cycle of the reference clock signal.
The data for a plurality of pixels that make up the data
An address for designating an address on the j-th row and the i-th column in each of the memory areas so that each of the data constituting the first parallel data is read out from each of the readable memory areas in a direction orthogonal to a writing direction. Signal A
address generating means for outputting j and i, and an address signal A generated by the address generating means.
an address decoder for outputting i, j and Aj, i to each of the memory areas; and converting the second parallel data consisting of data for a plurality of pixels read from each of the memory areas into serial data. A data transposition device, comprising: a parallel-serial converter for outputting. 2. A data transposition apparatus for replacing a row and a column of data of an N × N pixel matrix, comprising: an input terminal to which data constituting the N × N pixel matrix is sequentially input as serial data; Serial-parallel conversion means for converting input serial data into first parallel data composed of data of two adjacent pixels;
It comprises first, second, third and fourth memories for equally dividing and storing the data constituting the N pixel matrix, and in each memory, the first to second addresses are designated by address signals sequentially input from the outside. A storage unit into which data constituting one parallel data is written and from which data is read out from an address designated in the same manner; and a set of the first and third memories, and a set of the second and fourth memories. Control means for enabling the first and second memories and the third and fourth memories to be alternately readable at a predetermined timing, and a reference clock signal 1 Address generating means which operates in a cycle unit and generates an address signal used for writing and reading data in and from each of the memories. The data of two pixels constituting the first parallel data can be written to either one of the first and third memory sets and the second and fourth memory sets where the data can be written. , An address signal A for designating the address of the i-th row and the j-th column in each of the memories so as to be sequentially written in one of the row and column directions
While outputting i and j, the first and second data which can be read out for two pixels constituting the second parallel data written in each memory per reference clock signal cycle, respectively. J in each of the memories so that each of the data constituting the first parallel data is sequentially read out from the set of memories and the set of the third and fourth memories in a direction orthogonal to the direction in which the data is written.
Address generating means for outputting an address signal Aj, i for designating an address in a row i column; and when writing each data constituting the first parallel data, the address generating means generates one cycle of a reference clock signal by the address generating means. Address signal A
i, j are sequentially output to the first and third sets of memories and the second and fourth sets of memories, while the reference clock signal is used for reading each data constituting the second parallel data. The address signal Aj, i generated by the address generation means for one cycle of
The first and second memory sets and the third and fourth sets
And an address decoder for sequentially outputting the data to two or more memory sets, and a second pixel consisting of two pixels of data read from one of the first and second memory sets and the third and fourth memory sets. And a parallel-serial conversion means for converting parallel data into serial data and outputting the converted data. 3. A data transposition device for replacing a row and a column of data of an N × N pixel matrix, wherein: an input terminal to which data constituting the N × N pixel matrix is sequentially input as serial data; Serial-parallel conversion means for converting input serial data into first parallel data composed of data of two adjacent pixels;
It comprises a plurality of memory areas for equally dividing and storing data forming the N pixel matrix. In each memory area, the data forming the first parallel data is stored at an address specified by an address signal sequentially input from the outside. A first storage unit in which data is written and data is read from an address designated in the same manner;
It comprises a plurality of memory areas for equally dividing and storing data forming the N pixel matrix. In each memory area, the data forming the first parallel data is stored at an address specified by an address signal sequentially input from the outside. A second storage unit in which data is written and data is read from an address designated in the same manner; and a control in which one of the first and second storage units is made writable and the other is made readable. Means for generating address signals used for writing and reading data in a memory area constituting each of the storage means, the address generating means operating in units of one cycle of the reference clock signal. Data of two pixels constituting one parallel data is stored in the first and second storages, respectively. Against one respective memory area of the stage, as sequentially written in one of the row and column directions, i and the row j in the memory area
At the same time as outputting an address signal Ai, j for designating a column address, the data of two pixels constituting the second parallel data are stored in the other of the first and second storage means. Address generating means for outputting an address signal Aj, i designating an address of a j-th row and an i-th column in each memory area so that the first parallel data is read from the memory area in a direction orthogonal to a direction in which the first parallel data is written; Address signal A output from the address generating means
i and j are output to each one of the first and second storage areas which are made writable by the control means, and at the same time, the address signal Aj, i output from the address generation means is output. An address decoder for outputting to the other of the first and second storage means readable by the control means; and an address decoder read from each memory area of one of the first and second storage means. A data transposition apparatus, comprising: a parallel-serial conversion means for converting second parallel data composed of data for two pixels into serial data and outputting the serial data. 4. A data transposition device for replacing a row and a column of data of an N × N pixel matrix, wherein: an input terminal to which data constituting the N × N pixel matrix is sequentially input as serial data; A serial-to-parallel conversion means for converting input serial data into first parallel data consisting of data of two adjacent pixels, and a plurality of addresses each arranged in a matrix; Is composed of a plurality of memory areas for equally dividing and storing the data constituting the memory. In each memory area, data is written to an address specified by an address signal sequentially inputted from the outside, and data is similarly specified. Memory means for reading data from an address, and operating in units of one cycle of a reference clock signal. Address generating means for generating an address signal used for writing and reading data in each memory area constituting the memory means, wherein the data for two pixels constituting the first parallel data is a writable memory. An address signal Ai, j designating the address of the i-th row and the j-th column in the memory area so as to be sequentially written to the area in one of the row direction and the column direction. So that the data of two pixels constituting the second parallel data written in the first parallel data are read from the readable memory area in a direction orthogonal to the direction in which the first parallel data is written. Address generating means for outputting an address signal Aj, i designating the address of row j and column i in each memory area; Address signals A generated by the less generation means
an address decoder for outputting i, j and Aj, i to the memory area; and firstly, to make each memory area of the storage means writable, and to store data of an N × N pixel matrix.
In one cycle of the reference clock signal, each memory area of the storage means is made writable / readable, and one data is read from each memory area of the storage means, and then the same address as when the data is read is read out. Control means for writing new data; parallel-serial conversion means for converting second parallel data composed of data for two pixels read from each memory area of the storage means into serial data and outputting the serial data; A data transposition device, comprising: