JPS63229574A - Rotary image memory - Google Patents

Abstract

PURPOSE:To obtain a rotary image memory which can reduce the packing area of a memory circuit without deteriorating an output video rate, by processing simultaneously (n) pieces of planes out of (n<2>) pieces of planes in a reading mode. CONSTITUTION:In case 16 picture elements on the 6th row of each group array of an original image are read out of a memory circuit 14 in a rotary state 0 deg., an address 5H (H: hexa) is applied to an address converting circuit 15 and an address to be applied to each memory is set at 2H to be applied to the circuit 14 as well as original image memories M1-M8 respectively. In this case, 32 picture elements equivalent to 4 planes of a 0 deg. rotary mode can be read out of the circuit 1 at one time. The picture elements of the 6th row are stored in blocks 3 and 4, i.e., planes 4 and 3 and therefore planes 4 and 3 are validated out of 4 planes. Then desired data is converted into (8+8)-bit parallel signals by data rearranging circuits 12 and 13. These parallel signals are turned again into 16-bit data combined alternately for each bit. This data is converted into serial signals by a P/S converter 16 and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data storage device that can read rotated data at high speed, and is applied as a frame memory for image processing devices, document creation devices, document file devices, etc. can.

Conventional technology Prepare 2m11fa of memory with a capacity of IXN bits that can be independently assigned addresses, and store the original image in a size of 2m x 2m1.
Pixels are treated as one unit, and within this unit, 2m pixels can be accessed at once from both the row and column directions. )
An image storage device for rotation and reduction that rearranges data within a pixel and stores it every 2'' pixels has been proposed (
For example, Japanese Unexamined Patent Publication No. 60-19254).

As an example, the above method will be explained using a case where the original image is divided into 8×8 pixels as one unit. 11th
The figure shows a state in which each of the 8×8 pixels in one unit is numbered.

In order to be able to read out 8 pixels at a time from both the row and column directions of an image divided in this way, we have prepared 8 types of data sorting rules for the original data array as shown in Figure 2. Then, based on this sorting rule, the 8 pixels in the row direction within the unit are sorted, and as shown in Write to memories M1 to M8.

After writing in this manner, if, for example, the written state is to be read without rotation based on the written state, an address may be given in the same manner as when writing, and the read data may be rearranged according to PO to P7.

Also, for example, give input address: 1 (hexadecimal),
1.0.3.2.5.
4.7.6 (hexadecimal) and give it as an address, and then write the second
By applying the rearrangement rule Pl in the figure, it is possible to read out an image rotated 90 degrees to the left with respect to the input source image, and 8 pixels in the second column in the unit, in one access.

FIG. 13 shows the transition of data from read data to rearrangement P1 until valid data is finally obtained. Furthermore, for rotation by 90 degrees to the right, other data rearrangement for the same data string (for example, Pl instead of Pl)
This is possible by performing 6). As described above, eight pixels can be read out in one access from both the row direction and the column direction, regardless of the degree of rotation. According to the conventional method of rearranging data in this way and storing the data in a storage device composed of memory elements to which addresses are independently given, one word of pixels in a mode such as rotation can be obtained in one access. Although it has these advantages, it also has the following problems.

Problems to be Solved by the Invention Important points that must be taken into consideration when considering the configuration of a rotating image storage circuit include: ■ Output video rate to the display device; ■ Word configuration of existing memory elements; ■ These include the total capacity of input image information, (1) constraints on the structure of the prior art, and (2) mounting area. -As an example, the total capacity of the input image is 4M
Consider the case where a rotational image storage circuit is configured to store the bits. Assume now that the optimum word width of the memory circuit determined from the output video rate and the cycle time of the existing memory element is 32 bits. If an image storage circuit is configured by selecting from existing memory elements to satisfy the total capacity of the input image, for example, 64 word memory elements for 1 bit x 64, 1 bit x 25
For example, 16 word memory elements for 64 bits, 16 word memory elements for 4 bits x 64, etc. are considered. In terms of mounting area, 1 bit x 256 words, or 4 bits x 64
It is preferable to configure the memory device with 16 word memory elements.

However, in the case of 16 word memory elements for 1 bit x 256, the number of pixels that can be read in one access is 166.
There are pixels and the optimal word width cannot be met. In addition, in the case of 16 4-bit x 64 word memory elements, the number of pixels that can be read in one access is 64 pixels, but if one bit is extracted from each chip to form one plane, this Since the same address is given to the four bits in the plane direction, this method cannot be adopted because of the limitation that each bit constituting a word in the prior art must be given an address independently. In the end, due to the above-mentioned circumstances, we had to select 64 memory elements of 1 bit x 64 K words and configure them into 32 bits x 2 layers (128 words), resulting in 4 bits x 64. Word memory element 16
This has the disadvantage that the mounting area is increased compared to the case of one piece.

The present invention has been made in view of this point, and even if the number of storage elements is reduced and the word width of the storage circuit is reduced, the word width of the storage system as a whole does not decrease, that is, the output video rate is reduced. An object of the present invention is to provide a rotational image storage device that can reduce the mounting area of a storage circuit.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides 2m memories consisting of 2 sections each having a capacity of N hits that can be given the same address. The square area of n×n pixels of the original image is divided into one group and the group 2 m×2.
In pieces are combined into one unit, and one bit is extracted from each group of n x n bits of this unit and assigned to each of the n planes.The total image data of 2m1 x 2m1 bits is set as one block, and each pixel in this block is The data is rearranged so that 2'' pixels can be read out at a time from both the row and column directions, and an address conversion circuit generates an independent address corresponding to each memory.

Operation In the present invention, with the above configuration, by processing n planes out of n2 planes simultaneously during reading, the word width of the entire storage system is increased by n times the word width of the storage circuit. The number of memory elements used is reduced compared to the case where the word width of the entire memory device system is obtained by expanding and using memory elements with a 1-bit×N configuration.

Embodiment FIG. 1 is a block diagram showing an embodiment of the rotation/reduction image storage device of the present invention. In this embodiment, in order to simplify the explanation, m = 3 and n = 2, that is, one block of the original image has 8 x 8 pixels, and the number of planes of the memory element used is 4. In Fig. 1, 11 is a serial/parallel conversion circuit (S/P), 12 and 13 are input/output words @8-bit data sorting circuits, and 14 is made up of four planes each having a size of 1xN bits. 15 is an address conversion circuit, and 16 is a parallel/serial conversion circuit (P/Serial conversion circuit).
S).

Now, 2×2 pixels are one group, 8×8 pixels are one group.
one unit. FIGS. 4a to 4d show a state in which one unit is taken out as a part of the original image and each pixel within the unit is assigned a pixel number. The original image is serially input line by line to the storage device shown in this embodiment. In FIG. 1, an original image input serially is first converted into a 16-bit parallel signal by a serial/parallel conversion circuit 11. This 16-bit parallel signal is
8 bits +
Each is sent as an 8-bit parallel signal to the data sorting circuits 12 and 13, and the data is sorted PO to P7 according to the position in the image, and 1 bit for each, a total of 2 bits, is sequentially divided into each group. Assign to Within each group, bit allocation to each plane is reversed depending on whether the 16 bits are present in even-numbered rows or odd-numbered rows in the image. For example, block 1.2
．． 3.4 is stored as plane 1, 2.4°3, and so on. (This may be replaced when sending the 8-bit + 8-bit parallel signal to the data sorting circuit 12.13.) In this way, each pixel in Figure 4 a to d is assigned to each plane of each memory. The memorized state is shown in Figure 6 a to d.
Shown below. FIG. 5 is a diagram showing the arrangement of FIGS. 6a-d.

Next, the case of reading an image from the memory circuit 14 will be explained. For example, at a rotation state of 0 degrees, Figures 3 and 4 a
1. Let us consider the case where 16 pixels in the 6th row of the image in FIG. 4 are read out. Address: 5 (hexadecimal) is given to the address conversion circuit 15 in FIG. In this display mode, the address conversion circuit 15 assigns an address of 2 (hexadecimal) to each memory, and the memory circuit 14 and FIG.
d to each of Ml-M8. At this time, a total of 32 pixels for 4 pixels can be read out at once from the memory circuit 14, as shown in FIG. The pixels in the 6th row are in block 3.
4, that is, plane 4.3, out of these four planes, plane 4 and plane 3 are made valid, and the data rearrangement circuit 12-3 is stored as shown in FIG.
At step 113, the data rearrangement rule P2 shown in FIG. 2 is applied to convert it into a desired 8+8 bit parallel signal, and the data is returned to 16-bit data in which bits are alternately combined by performing the reverse operation of writing. The parallel/serial conversion circuit 16 converts the signal into a serial signal and outputs the signal. Similarly, when reading odd-numbered rows, plane 112 is made valid among the four planes, and when reading even-numbered rows, plane 4.3 is made valid.

Next, reading from the column direction, for example, a case of rotation by 90 degrees to the left will be described. For example, consider reading out the 10th column of the image in FIG. Address: 9 (1/6 decimal) is given to the address conversion circuit 15 in FIG. In this display mode, the address conversion circuit 15 stores 4.5.6.7.0.1.2.3 (hexadecimal ) and give it. At this time, a total of 32 pixels corresponding to 4 pixels can be read out at once from the memory circuit 14, as shown in FIG.

The 10th column of group 1 is block 2 and block 4.
, and is stored in plane 2.3. Therefore, out of these four planes, plane 2 and plane 3 are made valid, and the data rearrangement circuit 12.13 performs P4 as shown in Figure 10, converts it to the desired 8+8 bit parallel signal, and writes it. In the reverse order, data from plane 2 and data from plane 4 are alternately combined to form 16-bit data, which is then converted into a serial signal by a parallel/serial conversion circuit 16 and output. In this way, in the case of an even numbered column in one unit, plane 2.4 out of 4 planes is valid,
In the case of odd-numbered columns, reading in the column direction can be performed by validating plane 1.3 and converting the data arrangement.

In this way, even if the word width of the memory circuit is 8 bits, the word width of the entire memory device system must be doubled to 16 bits, that is, the mounting area must be doubled (the word width must be doubled). can be expanded to

In addition, as the actual configuration described in the conventional example, the total storage capacity is 4
M bits, the word width of the entire storage system is 3
Even in the case of 2 bits, according to this method, 4 bits x
Even if the word width of the memory circuit is reduced by using 16 64-word memory elements, the word width of the entire memory device system can be reduced to 32 bits, significantly reducing the mounting area of the memory circuit. can do.

In this embodiment, sections to which the same address can be given are described as I×n (one-dimensional), but the n×n sections have a two-dimensional configuration, and the memory element has a three-dimensional structure including the depth direction. It may be a configuration. In addition, although the present embodiment has been described with n=2, n=4.8...
But it doesn't matter.

Effects of the Invention As described above, according to the present invention, by using a memory element having generally n2 sections, the word width of the processing of the entire storage system is maintained and the minimum The mounting area of the memory circuit can be reduced to 1/n, which is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing eight types of data sorting rules PO-P7, and FIG.
The figure is a layout diagram of Figures 4a-d, and Figures 4a-d are part 1 unit of the original image taken out and 7. During. Each piece 2. -ヮ. , □II-1i-IJ, Fig. 5 (Yo 5. Memories, arrangement diagram of each plane in the '- path, Fig. 6 a - d shows the image data of Fig. 4 a - d in eight pieces M1 to M8. Figure 7 is an explanatory diagram showing an example of reading from each plane in the O anti-rotation mode.
The figure is a transition diagram showing the process of data sorting in the O anti-rotation mode, Figure 9 is an explanatory diagram of an example of reading from each plane in the 90 degree rotation mode, and Figure 10 is the process of data sorting in the 90 degree rotation mode. Transition diagram showing the first
Figure 1 is a state diagram in which one unit of a part of the original image is extracted and each 8x8 pixel in each unit is numbered. Figure 12 is a state diagram in which the image data in Figure 11 is divided into eight pixels M1 to M8. FIG. 13 is a state diagram illustrating reading and rearranging of data in a conventional 90 degree rotation mode. 11... Serial/parallel conversion circuit (S/P),
12.13... Data sorting circuit, 14...
Memory circuit, 15...Address conversion circuit, 16...
・Parallel/serial conversion circuit (P/S). Name of agent: Patent attorney Toshio Nakao 1 person Figure 1 Figure 2 Figure 3 Figure 1 Unit Figure 4 a Figure 4 Figure 4 C Figure 4 d Figure 5) d Pillow 1 person To) Mi Mountain 1h [lh Error Figure 11

Claims (1)

[Claims] It has n^2 sections with a capacity of N bits (n is a power of 2), and the same address can be given between these sections, that is, the data access unit for one address is n^2 bits. It uses 2^m memories (m is a natural number), and configures the 2^m memories so that addresses are given independently; The data of these 2^m memories are grouped into one plane for each section, and the total word width is n^2 with a word width of 2^m pixels.
The data access unit consisting of planes is n^2×
2^m storage means and a square area of n×n pixels of the original image as one unit (group), and the group 2^m
A square area composed of ×2^m pixels (that is, (n × 2^m) × (n × 2^m) pixels) is taken as one unit, and one bit is extracted from each group n × n bits of this unit, and n ^Total of 2^m allocated to each of the two planes
Data sorting, where 2^m bits of image data is regarded as one block, and each pixel in this block is rearranged so that 2^m pixels can be read out at once from both the row and column directions. and an address converting means for converting a given address into a predetermined address to be given to each of the 2^m memories according to the rotation state, allocating the original image to the blocks, and converting the original image into the blocks. The data rearranging means rearranges data in units of 2^m pixels in the row direction (or column direction), and the output is sequentially stored in the storage means using the address given by the address conversion means, and when read out. In order to do this, n planes out of the n^2 planes that can be read at a time are processed in parallel, and the word width of processing is expanded by n times for reading in the row direction and in the column direction. A rotational image storage device characterized by: