JP2001308721A - Product code encoder and decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a product code encoder and a decoder which can more decrease the number of memory access clocks for performing treatment of encoding and decoding of a product code at the time of using a memory with large bus width which is incorporated in an LSI. SOLUTION: A sink block outputted from a data compression circuit 113 is sequentially written in a memory 11 and outside code parity is added to a stored data matrix by an outside code encoding circuit 114. An inner code encoding circuit 115 reads the sink block sequentially from the memory 11 and adds inner code parity to it to output. A memory control circuit 12 is arranged so that the longitudinal direction of the data matrix is the column direction of the memory 11 when the bus width of L byte of the memory 11 is (2×A) bytes or more with respect to an A byte of the access unit of the outside code encoding circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a product code encoding apparatus and a decoding apparatus for encoding and decoding an error correction code constituting a product code.

[0002]

2. Description of the Related Art In recent years, in consumer video cameras, digital VTRs called DV formats have greatly increased their market share. In the DV format, a product code is used as an error correction code. Encoding and decoding of product codes in the DV format require several megabits of memory.

FIG. 11 is a diagram showing the structure of a product code of video data in the DV format. In FIG. 11, 1
The sync block is composed of 77 bytes, and one data matrix is composed of 138 sync blocks. One codeword of the product code is one byte, and an outer code parity is generated by 11 bytes in the vertical direction of the data matrix.
Eight bytes of the inner code parity are generated in the horizontal direction (sync block direction) of the data matrix.

[0004] As a conventional product code encoding apparatus and decoding apparatus in the DV format, for example, Japanese Patent Application Laid-Open No. Hei 8-2
No. 73347, "Data temporary storage device" and the like. Hereinafter, a conventional product code encoding apparatus in the DV format will be described.

FIG. 12 is a block diagram showing a conventional product code encoder. The memory 111 is, for example, a general-purpose synchronous DRAM external to an LSI, and has a data bus width of 16 bits (= 2 bytes). Most of the memory external to the LSI has a bus width of about 16 bits due to restrictions on the number of pins. Memory control circuit 112
Accesses the memory 111 according to an instruction from each circuit, and reads and writes data from and to the memory 111. The data compression circuit 113 performs a compression process on the video data to form a sync block (horizontal data of the data matrix), and outputs the sync block to the memory control circuit 112 together with a sync block number corresponding to the sync block on a one-to-one basis. The outer code encoding circuit 114 instructs the memory control circuit 112 to read data from the memory 111 in the order of the outer code sequence (vertical of the data matrix), and generates and outputs an outer code parity for the read data. , And instruct the memory control circuit 112 to write back to the memory 111. The outer code encoding circuit 114 processes two outer code sequences at a time. The inner code encoding circuit 115 outputs the sync block number corresponding to the sync block one-to-one to the memory control circuit 112, inputs the sync block corresponding to the sync block number, and generates the inner code parity for the sync block. Generate, add to sync block and output.

FIG. 13 is a diagram showing a mapping method of the memory 111 in the conventional product code encoder for ten sync blocks. Sync blocks are mapped in the memory 111 in the row direction, and the memory 111 has one address and two bytes.
The bytes (one sync block at the time when the inner code parity is not added is 77 bytes) are stored in 39 consecutive column addresses of the same row address. With this mapping, sync block access can be performed at high speed using page mode access of the DRAM. On the other hand, the access of the outer code encoding is to access consecutive row addresses of the same column address one by one, which is a random access.

FIG. 14 is a timing chart showing write access from the data compression circuit 113 to the memory 111 in the conventional product code encoder. CLK is a clock for operating the synchronous DRAM, RAS is a row address strobe, CAS is a column address strobe, ADRS
Represents an address, WE represents a write enable, and DATA represents access data. At the rise of CLK, RA
When S = 0, CAS = 1, and WE = 1, the row address of ADRS is activated. RAS = 0, CAS =
When 1, WE = 0, the row address of ADRS is precharged. AD when RAS = 1, CAS = 0, WE = 0
Write the data of DATA to the column address of RS. RA
When S = 1, CAS = 0, and WE = 1, data of DATA is read from the column address of ADRS. Write access of one sync block utilizes page mode access, and it takes 41 clocks from row active to precharge to write data to consecutive 39 column addresses of the same row address. Therefore, when writing one data matrix (138 sync blocks),
41 × 138 = 5658 clocks are required.

FIG. 15 is a timing chart showing access between the outer code encoder 114 and the memory 111 in the conventional product code encoder. Access to the outer code sequence is random access, and one data access requires three clocks from row active to precharge. In other words, the access of the outer code sequence is 138 when reading data.
Times, the outer code parity is written 11 times,
3 × 138 + 3 × 11 = 447 clocks are required. In this example, since the memory 111 has 2 bytes per address,
Two outer code sequences are accessed at a time, and one data matrix (77 outer code sequences) is accessed.
47 × 39 = 17433 clocks are required.

FIG. 16 is a timing chart showing read access from the memory 111 to the inner code encoder 115 in the conventional product encoder. Read access of one sync block utilizes page mode access, and it takes 41 clocks from row active to precharge to read data from consecutive 39 column addresses of the same row address. Therefore, to read one data matrix (149 sync blocks because the outer code parity is added), 41 × 149 = 6109
Requires a clock. By the above processing, the sync blocks output from the data compression circuit 113 are sequentially written into the memory 111, and the outer code encoding circuit 114 adds an outer code parity to the stored data matrix, and The encoding circuit 115 is a memory 111
, The sync blocks are sequentially read out, the inner code parity is added and the sync blocks are output. Access to the memory 111 of one data matrix of video data is 5658 + 17433 +
6109 = 29200 clocks are required. The product code decoding device has substantially the same configuration as the product code coding device of FIG. 11, and the memory access of one data matrix of video data is approximately 300
Requires 00 clocks.

[0010]

However, the conventional configuration shown in FIG. 12 has the following problems. recent years,
With the miniaturization of LSI, several megabits of synchronous D
It is becoming possible to incorporate a RAM in an LSI. L
Synchronous DRAM built into SI uses LS
Since the connection is made inside I, the bus width can be increased, and the bus width is usually about 128 bits. A larger bus width naturally has the advantage of a higher data transfer rate. When the transfer rate is increased, the number of memory access clocks is reduced, so that processing that has been performed by a plurality of memories can be integrated into one memory, and a great merit is generated in mounting area and cost.

However, in order to reduce the memory access clock by making good use of the bus width, it is necessary to devise a method of mapping data to the memory. In the mapping similar to that of the conventional product code encoder shown in FIG. 12, that is, in the method of mapping the sync blocks in the row direction of the memory, for example, the bus width of the memory is 128 bits (= 1 bit).
(6 bytes), 77 bytes of one sync block are stored in five consecutive column addresses of the same row address.
The write access of one sync block from the data compression circuit 113 to the memory requires seven clocks from row active to precharge to write data to consecutive five column addresses of the same row address using page mode access. Therefore, one data matrix (1
7 × 138 = 9 to write 38 sync blocks)
It requires 66 clocks. The access of the outer code sequence between the outer code encoding circuit 114 and the memory is random access, and one address access requires three clocks from row active to precharge. That is, the outer code sequence is accessed 138 times for reading data and 11 times for writing outer code parity, so that 3 × 138 + 3 × 1
1 = 447 clocks are required. Outer code encoding circuit 114
If the outer code sequence that can be processed at a time is a two outer code sequence, the same access to the memory must be performed again when processing the next two outer code sequences.
Accessing one data matrix (77 outer code sequence) requires 447 × 39 = 17433 clocks. In the read access of one sync block from the memory to the inner code encoding circuit 115, page mode access is used to read data from consecutive five column addresses of the same row address.
Requires a clock. Therefore, it takes 7 × 149 = 11043 clocks to read one data matrix (149 sync blocks because the outer code parity is added). As a result, the access of the memory of one data matrix of the video data is 966 + 17433 + 104.
3 = 19442 clocks are required.

As described above, compared to the case where an external synchronous DRAM having a bus width of 16 bits is used, the bus width is one bit smaller.
In the case of using a 28-bit LSI built-in synchronous DRAM, writing from the data compression circuit 113 to the memory is from 5658 clocks to 966 clocks, and reading from the memory to the inner encoding circuit 115 is from 6109 clocks to 1043 clocks. Although the number of clocks has decreased, the total number of clocks has been reduced by about 33% from 29200 clocks to 19422 clocks because the access between the outer code encoding circuit 114 and the memory has not decreased at all. In this case, it cannot be said that the fact that the bus width has become 128 bits can be effectively used, and it is still difficult to integrate the processing performed by a plurality of memories into one memory.

The present invention has been made to solve the above-described problem. When a memory having a large bus width is used, the number of memory access clocks for encoding and decoding a product code can be reduced. It is an object of the present invention to provide a product code encoding device and a decoding device that can be executed.

[0014]

In order to achieve the above object, a product code encoding apparatus according to the present invention compresses input digital data and generates a J × K sync block consisting of K sync blocks in J byte units. A data compression means for outputting as a K-byte data matrix, a memory having a two-dimensional matrix address space and allowing page mode access in units of L bytes in the same row address direction, and a memory read out of the memory in the order of the outer code sequence Outer code encoding means for generating and outputting an outer code parity for the data, and inner code encoding means for generating and outputting an inner code parity for each sync block read from the memory in sync block units, A memory control means for controlling writing and reading of data to and from the memory, wherein the memory control means includes a data matrix of J × K bytes. When writing to memory
A byte sync block continues in the column direction [(J /
L) +1] is sequentially written in the row direction and the column direction in the order of the sync block in the L-byte unit to obtain (N × L)
The data is input as a data matrix of × [{(J × K) / (N × L)} + 1] bytes.

Thus, the product code encoding apparatus of the present invention can reduce the number of memory access clocks for encoding the product code when using a memory having a large bus width. The reason is as follows.

First, consider the case where the horizontal direction of the data matrix is arranged in the page mode access direction of the memory.
The number of clocks required for the write access from the data input means to the memory is J / L + 2 clocks including one row (J byte) of the data matrix and including row active and precharge. (J / L + 2) × K clocks for writing. Since the access between the outer code encoding means and the memory is random access and the number of required clocks is 3 clocks for one data including row active and precharge, the access of the outer code sequence is 3 × Q clock ( Q is the total number of sync blocks including the outer code parity, and the outer code encoding means sends A (A =
2) Since data is accessed one byte at a time, one data matrix is accessed by 3 × Q × (J / A) clocks. The number of clocks required for read access from the memory to the inner code encoding means is (J / L) +2 clocks for one row of the data matrix, including row active and precharge. Is read, (J / L + 2) × Q clocks. As a result, access to the memory of one data matrix requires 2 JQ / L + 4Q + 3JQ / A clocks, assuming that K can be approximated to Q.

Next, when the vertical direction of the data matrix is arranged in the page mode access direction of the memory (J × K →
K × J). The number of clocks required for write access from the data input means to the memory is 3 clocks including row active and precharge for one address, so that 3 × J / L clocks for one row of the data matrix. Therefore, 3 × (J / L) × K clocks are required to write one data matrix. Since the number of clocks required for access between the outer code encoding means and the memory is J / L + 2 clocks including row active and precharge in one page mode, the access of the outer code sequence is (J / L + 2) × Q / (J / L) clocks, and the outer code encoding means accesses the memory A bytes at a time, so that one data matrix access is (J / L + 2) × Q / (J / L) × J / A clock. The number of clocks required for read access from the memory to the inner code encoding means is 3 clocks including row active and precharge for one address, so that 3 × J / L clocks for one row of the data matrix. Therefore, 3 × (J / L) × Q clocks are required to read one data matrix. As a result, access to the memory of one data matrix requires 6 JQ / L + JQ / A + 2LQ / A clocks, assuming that K can be approximated to Q.

Therefore, the condition that the number of access clocks is smaller when the vertical direction of the data matrix is arranged in the page mode access direction of the memory than when the horizontal direction of the data matrix is arranged in the page mode access direction of the memory is as follows. 2JQ / L + 4Q + 3JQ / A ≧ 6JQ / L + JQ / A
+ 2LQ / A, and solving this equation gives (L-2A) (L−J) ≦ 0. Usually, J is larger than 2A,
As a result, L ≧ 2A is obtained. For example, when outer coding is performed in two sequences, A is 2 and if L is 4 or more,
The required number of clocks can be reduced.

In order to achieve the above object, a product code decoding apparatus according to the present invention has a two-dimensional matrix address space, and is capable of performing page mode access in L-byte units in the same row address direction. And memory control means for controlling writing and reading of data to and from the memory, and inputting M bytes of data with an (MJ) byte inner code added to a J byte sync block to perform inner code decoding processing Inner code decoding means to be executed, and N data sync blocks composed of K data sync blocks and (NK) outer code sync blocks.
Outer code decoding means for sequentially inputting the sync blocks as outer code sequences, performing outer code decoding processing and outputting corrected data, and data for reading and outputting corrected data from the memory in sync block units Output means, and the memory control means concatenates J-byte sync blocks output from the inner code decoding means in the column direction [(J /
K) +1] An operation of writing data in L-byte units in the row is sequentially performed in the row direction and the column direction in the order of the sync block, and (N × L) ×
It is characterized in that it is stored in a memory as a data matrix of [{(J × K) / (N × L)} + 1] bytes. In this specification, the symbol [] indicates that if the quotient of the division has a numerical value below the decimal point, it is rounded up. For example, [(J / L) +1] means that if J / L is not divisible, it is rounded up. Also, [｛(J × K) / (N × L)｝ + 1]
Then, if JK / NL is not divisible, it means to round up.

Thus, the product code decoding device of the present invention can reduce the number of memory access clocks for decoding the product code when using a memory having a large bus width. The reason is as follows.

First, consider the case where the horizontal direction of the data matrix is arranged in the page mode access direction of the memory.
The number of clocks required for write access from the inner code decoding means to the memory is J / L + 2 clocks for one row of the data matrix, including row active and precharge. Then, (J / L + 2) × Q clock is obtained. The number of clocks required for access between the outer code decoding means and the memory is 3 clocks for one data, including row active and precharge. Therefore, the access of the outer code sequence is 3 × Q clocks, Assuming that the decoding means accesses the memory A bytes at a time, the access of one data matrix is 3 × Q × J / A clock. The number of clocks required for the read access from the memory to the data output means is J / L + 2 clocks for one row of the data matrix, including row active and precharge. Therefore, to read one data matrix, (J / L + 2) × K clocks. If there are B data output means, (J / L + 2) × K × B clocks. As a result, access to the memory of one data matrix requires (B + 1) JQ / L + 2 (B + 1) Q + 3JQ / A clocks, assuming that K can be approximated to Q.

Next, consider the case where the vertical direction of the data matrix is arranged in the page mode access direction of the memory.
The number of clocks required for write access from the inner code decoding means to the memory is 3 clocks including row active and precharge for one address, and therefore 3 × J / L clocks for one row of the data matrix. Therefore, to write one data matrix, 3 × (J / L) × Q clocks are required. The number of clocks required for access between the outer code decoding means and the memory is J / L + 2 clocks including row active and precharge in one page mode. L + 2) × Q / (J / L) clocks, and the outer code decoding means accesses the memory A bytes at a time, so one data matrix access is (J / L + 2) × Q / (J / L) × J / A clock. The number of clocks required for a read access from the memory to the data output means is 3 clocks including row active and precharge for one address, and therefore 3 × J / L clocks for one row of the data matrix. Therefore, 3 × (J / L) × K clocks are required to read one data matrix. If there are B data output means, then 3 × (J / L) × K × B clocks. As a result, access to the memory of one data matrix requires 3 (B + 1) JQ / L + JQ / A + 2LQ / A clocks, assuming that K can be approximated to Q.

Therefore, the condition that the number of access clocks is smaller when the vertical direction of the data matrix is arranged in the page mode access direction of the memory than when the horizontal direction of the data matrix is arranged in the page mode access direction of the memory is as follows. (B + 1) JQ / L + 2 (B + 1) Q + 3 JQ / A ≧ 3
(B + 1) JQ / L + JQ / A + 2LQ / A By solving this equation, (LA (B + 1)) (LJ) ≦ 0 is obtained. Normally, J is larger than A (B + 1), so if L ≧ A (B + 1), the number of clocks can be reduced.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. <Embodiment 1> FIG. 1 is a block diagram showing the configuration of a product code encoder according to Embodiment 1. Memory 11
Is, for example, a synchronous DRAM built in an LSI, and the bus width of the data bus is 128 bits (= 16 bytes). Many memories built in LSI have a large bus width in order to increase the data transfer rate. The memory control circuit 12 accesses the memory 11 according to instructions from each circuit, and reads and writes data from and to the memory 11. The data compression circuit 113 performs a compression process on the video data to form a sync block (horizontal data of the data matrix), and outputs the sync block number to the memory control circuit 12 together with a sync block number corresponding to the sync block on a one-to-one basis. The outer code encoding circuit 114 stores the data in the memory 11 in the order of the outer code sequence (vertical of the data matrix).
And instructs the memory control circuit 12 to generate and output an outer code parity for the read data and write it back to the memory 11. The outer code encoding circuit 114 processes two outer code sequences at a time. The inner code encoding circuit 115
A sync block number corresponding to each sync block is output to the memory control circuit 12, a sync block corresponding to the sync block number is input, an inner code parity is generated for the sync block, and the parity is added to the sync block. Output. The configuration of the product code to be encoded is the same as that of the conventional example, and as shown in FIG.
Each data matrix is composed of 138 sync blocks. One codeword of the product code is 1 byte, 11 bytes of outer code parity are generated in the vertical direction of the data matrix, and 8 bytes of inner code parity are generated in the horizontal direction (sync block direction) of the data matrix. Therefore, when applied to claims 1 and 4, A = 2, J = 77, K = 138, L = 16,
M = 85, N = 149, and L [= 16] ≧ 2 × A
Since [= 4], the vertical direction of the data matrix is arranged in the page mode access direction of the memory 11.

FIG. 2 is a diagram showing the mapping of the memory 11 in the product code encoder according to the first embodiment of the present invention, corresponding to the conventional mapping shown in FIG. In the memory 11, sync blocks are mapped in the column direction (random access direction). Since the memory 11 has one address of 16 bytes, one sync block of 77 bytes is stored in five consecutive addresses of the same column address. By this mapping, the sync block access is to access consecutive row addresses of the same column address one by one, which is a random access. On the other hand, since the vertical direction of the data matrix is mapped to five consecutive column addresses of the same row address, the page mode access of the DRAM can be used for the access of the outer code encoding.

FIG. 3 is a flowchart of the mapping executed by the memory control circuit 12, and shows the mapping for ten sync blocks for simplicity. here,
The sync block number is S (n, j) (n = 1, 2, j =
1 to 5), and i indicates the number of the address of the sync block. In step S101, n, j,
Initialize i to 1 respectively. In step S102, the i-th (i = i) of the sync block S (n, j) = S (1,1)
The data at the address 1) is written into the memory at the address (0,0). In step S103, i is incremented, and the data at the second address is written to the address (1, 0) of the memory. This write operation is repeated until i = 5, and the data write of the sync block 1 is completed. That is, when i = 5 in step S104, j is incremented in step S105, and the next sync block [S (1,2)]
= 2], the data is written in step S10.
In step 7, i is set to 1 again, and the process returns to step S102 to sequentially write the data of the sync block 2 from the memory addresses (0, 1) to (4, 1). In this way, when writing to the sync block 5 is completed (S106),
In step S108, n is incremented, and the second-stage sync blocks S (2,1) (= 6) to S (2,5)
To write data up to (= 10), j = 1 is set in step S110, and the process returns to step S102. If n = 3 is confirmed in step S109, the writing of all sync blocks is completed.

FIG. 4 is a timing chart showing write access from the data compression circuit 113 to the memory 11 in the product code encoder according to the first embodiment of the present invention. CLK is a clock for operating the synchronous DRAM, RAS is a row address strobe, CAS is a column address strobe, ADRS is an address, WE is a write enable, and D is a write enable.
ATA represents access data. When RAS = 0, CAS = 1, and WE = 1 at the rise of CLK, AD
The row address of RS is set to the active state. RAS =
When 0, CAS = 1 and WE = 0, the row address of ADRS is precharged. RAS = 1, CAS = 0, WE =
When 0, DATA data is written to the column address of ADRS. AD when RAS = 1, CAS = 0, WE = 1
DATA data is read from the column address of RS. Write access of one sync block is random access, and access of one address requires three clocks from row active to precharge. Since access to one sync block involves writing of five addresses,
3 × 5 = 15 clocks are required. Therefore, it takes 15 × 138 = 2070 clocks to write one data matrix (138 sync blocks).

FIG. 5 is a timing chart showing access between the outer code encoder 114 and the memory 11 in the product code encoder according to the first embodiment of the present invention. The access of the outer code sequence uses page mode access of five addresses, and it takes seven clocks from row active to precharge to access consecutive five column addresses of the same row address. Outer code sequence access is 1 when data is read
Since there are 38 addresses and 11 addresses for writing outer code parity, a total of 149 addresses, 30 consecutive 5-column address accesses require 30 times, that is, 7 × 30 = 210 clocks. Since the outer code sequence that can be processed by the outer code encoding circuit 114 at a time is a two outer code sequence, the same access to the memory must be performed again when processing the next two outer code sequences. To access one data matrix (77 outer code sequence)
39 = 8190 clocks are required.

FIG. 6 is a timing chart showing a read access from the memory 11 to the inner code encoder 115 in the product code encoder of the first embodiment of the present invention. Read access of one sync block is random access, and access of one address requires three clocks from row active to precharge. Since access to one sync block involves reading five addresses, 3 × 5 = 1
Requires 5 clocks. Therefore, to read one data matrix (149 sync blocks), 15 ×
149 = 2235 clocks are required. By the above-described processing, the sync blocks output from the data compression circuit 113 are sequentially written to the memory 11, and the outer code encoding circuit 114 adds an outer code parity to the stored data matrix. Encoding circuit 115
Sequentially read out the sync blocks from the memory 11, add the inner code parity, and output them. Access to the memory 11 of one data matrix of video data is 2070 + 8
190 + 2235 = 12495 clocks are required. This number of clocks is reduced by about 57% from 29200 clocks when an external synchronous DRAM having a bus width of 16 bits is used in the conventional product code encoder, and 128 bits in the conventional product code encoder. This is about 36% lower than 19422 clocks when using the LSI built-in synchronous DRAM. As a result, the product code encoding device of the present invention can reduce the number of memory access clocks for performing the process of product code encoding when a memory having a large bus width is used. It is also possible to integrate the processing performed in step 1 into one memory.

<Embodiment 2> FIG. 7 is a block diagram showing a configuration of a product code decoding apparatus according to Embodiments 5 and 8. Since the memory 11 and the memory control circuit 12 have the same configuration as that shown in FIG. 1 in the first embodiment, detailed description is omitted here. The inner code decoding circuit 65 outputs a 77-byte sync block obtained by performing inner code error correction processing on the input sync block to the memory control circuit 12 together with a sync block number corresponding to each sync block on a one-to-one basis. I do. The outer code decoding circuit 64 instructs the memory control circuit 12 to read data from the memory 11 in the order of the outer code sequence, performs outer code error correction processing on the read data, and, when there is an error, , And instructs the memory control circuit 12 to write the correct data back to the memory 11. The outer code decoding circuit 64 processes two outer code sequences at a time.
The data decompression circuit 63 outputs a sync block number corresponding to the sync block one-to-one to the memory control circuit 12, inputs a sync block corresponding to the sync block number, performs decompression processing on the sync block, and outputs video data. Output. The configuration of the product code to be decoded is the same as that of the conventional example, and as shown in FIG.
Each data matrix is composed of 138 sync blocks. One code word of the product code is 1 byte, 11 bytes of outer code parity are generated in the vertical direction of the data matrix, and inner code parity is horizontal direction of the data matrix (sync block direction).
8 bytes are generated. Therefore, when applied to claims 5 and 8, A = 2, B = 1, J = 77, K =
138, L = 16, M = 85, N = 149, and L
Since [= 16] ≧ A × (B + 1) [= 4], the vertical direction of the data matrix is arranged in the column direction of the memory 11.

That is, the mapping of the memory 11 in the product code decoding apparatus according to the second embodiment of the present invention is the same as that shown in FIG. 2 in the first embodiment. In the memory 11, sync blocks are mapped in the column direction. Since the memory 11 has one address of 16 bytes, 77 bytes of one sync block are stored in five consecutive addresses of the same column address. By this mapping, the sync block access is to access consecutive row addresses of the same column address one by one, which is a random access. On the other hand, since the vertical direction of the data matrix is mapped to five consecutive column addresses of the same row address, the page mode access of the DRAM can be used for the outer code decoding access.

FIG. 8 is a timing chart showing write access from the inner code decoding circuit 65 to the memory 11 in the product code decoding apparatus according to the second embodiment of the present invention. Write access of one sync block is random access, and access of one address requires three clocks from row active to precharge. Since access to one sync block involves writing of 5 addresses, 3 × 5 = 15
Requires a clock. Therefore, to write one data matrix (149 sync blocks), 15 × 1
49 = 2235 clocks are required.

FIG. 9 is a timing chart showing access between the outer code decoding circuit 64 and the memory 11 in the product code decoding apparatus according to the second embodiment of the present invention. The access of the outer code sequence uses page mode access of five addresses, and it takes seven clocks from row active to precharge to access consecutive five column addresses of the same row address. Access to outer code sequence is 14
Since there are 9 addresses, 30 consecutive 5-column address accesses require 30 clocks, that is, 7 × 30 = 210 clocks.
When there is no error, the access to the outer code sequence is completed. Since the outer code sequence that can be processed by the outer code decoding circuit 64 at a time is two outer code sequences, the same access to the memory must be performed again when processing the next two outer code sequences. 210 × 39 = 819 to access one data matrix (77 outer code sequence)
Requires 0 clocks.

FIG. 10 is a timing chart showing read access from the memory 11 to the data decompression circuit 63 in the product code decoding apparatus according to the second embodiment of the present invention. Read access of one sync block is random access, and access of one address requires three clocks from row active to precharge. Since access to one sync block involves reading of 5 addresses, 3 × 5 = 15
Requires a clock. Therefore, to read one data matrix (138 sync blocks), 15 × 1
38 = 2070 clocks are required. With the above-described processing, the sync blocks output from the inner code decoding circuit 65 are sequentially written into the memory 11, and the stored data matrix is subjected to outer code error correction processing by the outer code decoding circuit 64. The data decompression circuit 63 sequentially reads out the sync blocks from the memory 11, performs decompression processing, and outputs the data as video data. Access to the memory 11 of one data matrix of video data is 2235 + 8
190 + 2070 = 12495 clocks are required. This number of clocks is reduced by about 57% from 29200 clocks when an external synchronous DRAM having a bus width of 16 bits is used in the conventional product code decoding apparatus, and is 128 bits in the conventional product code decoding apparatus. This is about 36% lower than 19422 clocks when using the LSI built-in synchronous DRAM. Accordingly, the product code decoding apparatus of the present invention can reduce the number of memory access clocks for performing the process of decoding a product code when using a memory having a large bus width, and can reduce the number of memory access times. It is also possible to integrate the processing performed in step 1 into one memory.

[0035]

According to the product code encoding apparatus of the present invention, the bus width L of the memory is determined by the access unit A of the outer code encoding means.
If the number of bytes is (2 × A) bytes or more, the vertical direction of the data matrix is arranged in the page mode access direction of the memory. As a result, when a memory having a large bus width is used, the number of memory access clocks for encoding the product code can be further reduced. Further, in the product code decoding apparatus of the present invention, the bus width L bytes of the memory is (A × (B)
+1)) If the number of bytes is equal to or more than one, the vertical direction of the data matrix is arranged in the page mode access direction of the memory. As a result, when a memory having a large bus width is used, the number of memory access clocks for decoding the product code can be further reduced. As a result,
In the product code encoding apparatus and the decoding apparatus according to the present invention, processing that has been performed by a plurality of memories can be integrated into a single memory, and a great merit arises in mounting area and cost.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a product code encoding device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating a memory mapping in the product code encoding apparatus according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating a method of mapping a data matrix to a memory in the product code encoding device according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing write access from a data compression circuit to a memory in the product code encoding device according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing access between the outer code encoder and the memory in the product code encoder according to the first embodiment of the present invention.

FIG. 6 is a timing chart showing read access from a memory to an inner code encoding circuit in the product code encoding device according to the first embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a product code decoding device according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing write access from the inner code decoding circuit to the memory in the product code decoding device according to the second embodiment of the present invention.

FIG. 9 is a timing chart showing access between an outer code decoding circuit and a memory in the product code decoding device according to the second embodiment of the present invention.

FIG. 10 is a timing chart showing read access from a memory to a data decompression circuit in the product code decoding device according to the second embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration of a product code of video data in a DV format.

FIG. 12 is a block diagram showing a conventional product code encoder.

FIG. 13 is a diagram showing memory mapping in a conventional product code encoding device.

FIG. 14 is a timing chart showing write access from a data compression circuit to a memory in a conventional product code encoder.

FIG. 15 is a timing chart showing access between an outer code encoder and a memory in a conventional product code encoder.

FIG. 16 is a timing chart showing read access from a memory to an inner code encoding circuit in a conventional product code encoding device.

[Explanation of symbols]

 Reference Signs List 11 memory 12 memory control circuit 63 data decompression circuit 64 outer code decoding circuit 65 inner code decoding circuit 113 data compression circuit 114 outer code coding circuit 115 inner code coding circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 536 G11B 20/18 536A 544 544A 572 572B 572G F term (Reference) 5B001 AA13 AB02 AC03 AD03 5B018 GA02 HA16 RA02 RA11 5B060 GA11 5J065 AA01 AB01 AC03 AD01 AE06 AH06 AH17 AH21

Claims (8)

[Claims] An input digital data is compressed, and J × K composed of K sync blocks in J byte units is provided.
A data compression means for outputting as a byte data matrix, a memory having a two-dimensional matrix address space and capable of accessing a page mode in units of L bytes in the same row address direction, and a memory read out of the memory in an outer code sequence order Outer code encoding means for generating and outputting outer code parity for data; inner code encoding means for generating and outputting inner code parity for each sync block read from the memory in sync block units; And a memory control means for controlling the writing and reading of data to the memory. The memory control means connects a J-byte sync block in the column direction when writing the J × K-byte data matrix into the memory. / L) +1] is sequentially performed in the row direction and the column direction in the order of the sync block in units of L bytes. , (N × L) × [{(J × K) / (N
× L) {+1} byte data matrix. 2. The product code according to claim 1, wherein the memory control circuit accesses consecutive N column addresses of the same row address by a page mode access when encoding the outer code. Encoding device. 3. The memory control circuit according to claim 2, wherein at the time of inner code encoding, data of [(J / L) +1] rows that are continuous in the same column direction are read out by random access. 3. The product code encoder according to 1 or 2. 4. When the outer code encoding means accesses the memory in units of A bytes, the L is (2 ×
A) The product code encoder according to claim 1, 2 or 3, which is equal to or greater than A). 5. A memory having a two-dimensional matrix address space and capable of accessing a page mode in units of L bytes in the same row address direction, memory control means for controlling writing and reading of data to and from the memory, and J bytes Inner code decoding means for inputting M bytes of data with an (MJ) byte inner code added to the sync block and executing inner code decoding processing; K data sync blocks; Outer code decoding means for sequentially inputting N sync blocks consisting of K) outer code sync blocks in the form of an outer code sequence, performing outer code decoding processing, and outputting corrected data; Data output means for reading and outputting from the memory in block units, wherein the memory control means is a J-byte sync block output from the inner code decoding means. Continuous in the column direction [(J
/ K) +1] An operation of writing in L-byte units in a row is sequentially performed in the row direction and the column direction in the order of the sync block (N × L)
A product code decoding device characterized in that the product matrix is stored in a memory as a data matrix of × [{(J × K) / (N × L)} + 1] bytes. 6. The product code according to claim 5, wherein said memory control circuit accesses consecutive N column addresses of the same row address by page mode access when decoding the outer code. Decryption device. 7. The memory control circuit according to claim 1, wherein at the time of inner code decoding, data of [(J / K) +1] rows continuous in the same column direction is read out by random access. 7. The product code decoding device according to 5 or 6. 8. When the outer code decoding means accesses the memory A bytes at a time and has B data output means, the L is {A × (B × 1)} or more.
The product code decoding device according to claim 5, 6 or 7.