JP2838964B2 - Variable length coding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length coding circuit, and more particularly to a variable length coding circuit used in a digital image data compression coding apparatus.

[0002]

2. Description of the Related Art Generally, the amount of image data is extremely large, and it is common practice to reduce the amount of data by compressing the data during storage and transmission. One such data compression method is the International Telegraph and Telephone Consultative Committee (CCI).
TT) Research Committee SGXV (Transmission System and Equipment)
Recommendation (draft) No. H. 26
There is the No. 1 video coding system (hereinafter, H261 system).
In the H261 system, an input image signal is divided into two-dimensional blocks of 8 × 8 pixels, orthogonal transform and quantization are performed by discrete cosine transform, and then variable length coding is performed by using a well-known Huffman code. In the Huffman code, a code word is determined by a run signal (6 bits) which is a continuous zero coefficient value and a level signal (8 bits) which is a non-zero value. As a result, a variable length codeword of 2 bits to 14 bits or a fixed length codeword of 20 bits is obtained.

FIG. 3 is a block diagram showing an example of a conventional variable length coding circuit for obtaining the variable code length word. Referring to FIG. 3, the conventional variable length coding circuit includes 8 bits of a level signal L and a run signal R. And a ROM 3A storing a code conversion table having an address value of a total of 14 bits including a 6-bit code, and a variable-length code word C of a maximum of 14 bits by accessing the ROM 3A with a level signal L and a run signal R. A 4-bit code length B indicating the code length of the long code word C is supplied as output data.

As described above, if the maximum code length of the variable length code word C is 14 bits and the code length B is 4 bits,
The required memory capacity of the ROM 3A is 16K words × 18 bits.

On the other hand, referring to Table 1 showing a list of variable length codewords corresponding to the transform coefficients of the H261 system, the first block of the block end code EOB, the run signal (0) and the level signal (0) in the table is shown. Since the code word overlaps with other coefficients, if it is deleted from the code conversion table, the number of words of the variable length code word C to be stored in the ROM 21 is 63 words. The number of words 63 is extremely smaller than the required memory capacity of 16K words of the ROM 3A.

[0006]

[Table 1]

In recent years, there has been a tendency to reduce the size of an image data compression encoding device by developing a dedicated LSI for each required function. The circuit scale of this type of LSI depends on the number of gates, and the number of gates depends on the memory capacity of the code conversion table ROM. The above memory capacity is set to 16K in this example.
If it is a word, the number of gates is slightly less than 125K gates, which makes it difficult to promote LSI.

[0008]

The above-mentioned conventional variable-length coding circuit has a problem that the memory capacity of the ROM storing the code conversion table is extremely large as compared with the number of words of the variable-length code word to be stored. Circuit scale becomes large and LSI
There was a drawback that it became a hindrance factor for the promotion of gasification.

Also, because of the large circuit scale described above,
There is a drawback that power consumption is large and it is difficult to increase the speed.

[0010]

A variable length coding circuit according to the present invention divides input image data into two-dimensional blocks consisting of a matrix having a predetermined number of pixels, and performs orthogonal transform and quantization for each of the two-dimensional blocks. Receiving the supplied quantized image data, a code signal for a code word search corresponding to a combination of a run signal that is a continuous zero coefficient value of the quantized image data and a level signal that is a non-zero value following the run signal Code conversion table
In response to the supply of the run signal and the level signal.
In the variable length coding apparatus for performing variable length coding using Huffman codes answer to determine the code word, and the absolute value circuit for generating an absolute value signal by converting the value of said level signal to an absolute value, the absolute value a bit conversion circuit for generating the signal and shortening the address signal with a reduced number of bits in advance determined manner than the sum of each number of bits of a received these absolute value signal and the run signal supply between the run signal, the shorter address signal a conversion table ROM for outputting the code length signal indicative of the code length code word signal of a predetermined code length by the access of the corresponding said code conversion table stores this short address signal, the code length signal and the level A decoder circuit for outputting a positive / negative code signal in response to the supply of a signal, and a variable length code with a positive / negative sign receiving the supply of the positive / negative sign signal and the code word signal It is configured to include a negative sign adding circuit for outputting a signal.

[0011]

FIG. 1 is a block diagram showing an embodiment of the present invention.
, The variable length encoding circuit of the present embodiment shown in FIG.
An absolute value circuit 1 for supplying the absolute value a and a bit conversion circuit 2 for responding to the supply of the absolute value a and the run signal R to convert the bit into an n-bit address signal b corresponding to the number of words to be used in the ROM 3. A ROM 3 for storing a code word conversion table and supplying a code word c and a code length B in response to the supply of the address signal b, and a code length B in response to the supply of the code length B.
And a decoder circuit 4 that decodes the input word signal L and determines the sign of the input level signal L to supply a sign signal d.
A plus / minus sign adding circuit 5 for outputting a variable length codeword C obtained by adding a plus / minus sign to the codeword c in response to the supply of the codeword c and the sign signal d.

Next, the operation of this embodiment will be described with reference to FIG. 1. An absolute value circuit 1 is a quantizer (not shown).
-1 represented by the supplied 8-bit level signal L
From the level values 27 to 127, only the positive 0 to 127 are taken out, that is, the 7-bit absolute value a excluding the first bit indicating the sign is supplied to the bit conversion circuit 2. In response to the supply of the absolute value a and the 6-bit run signal R, the bit conversion circuit 2 performs bit conversion by compressing the number of bits to n bits corresponding to the number of words to be used in the code word conversion table of the ROM 3. To generate an address signal b. ROM3
Outputs a code word c of 14 bits and a code length B of 4 bits in response to the supply of the address signal b. Decoder circuit 4
Decodes the supplied code length B, determines the sign of the input level signal L, and supplies the sign signal d to the sign addition circuit 5. Sign addition circuit 5
Outputs a variable-length codeword C by adding a sign to the codeword c.

Next, the bit conversion circuit 2, which is an important component of the present embodiment, will be described in more detail.

Referring to Table 2 showing an example of the above-described bit conversion by array conversion of the level signal L and the run signal R with the number of bits n of the address b being 7, L and R shown in Table 2 are level signals L And the value of the run signal R, the 63 coefficients to be variable-length coded are converted into address values designated in the table, and the other coefficients are converted into any of the parts indicated by '-'.

[0015]

[Table 2]

Referring to FIG. 2 showing a specific circuit example of the bit conversion circuit 2, the bit conversion circuit 2 includes a conversion circuit 21 for outputting an address b when the value of the run signal R is 0 to 7. And a conversion circuit 22 that outputs an address b when the value of the run signal R is 8 or more, and selects one of the outputs of the conversion circuits 21 and 22 in response to the value of the selection signal S to generate a 7-bit address. A selection circuit 23 that outputs signals b0 to b6 and a selection signal generation circuit 24 that supplies a selection signal S that controls the selection circuit 23 according to the value of the run signal are provided.

The conversion circuit 21 receives the supply of the run signals R0 to R2 and the level signals L3 to L6 and activates the mask signal m1, and the level signal in response to the activation state of the mask signal m1. A mask circuit 212 for masking each of the L0 to L3 and the run signals R0 to R2.

The conversion circuit 22 includes an MSB output circuit 221 for generating the most significant bit (MSB) MB of the output signal, and a mask signal generation circuit for activating the mask signal m2 when the level signal L is other than 1 and the MSBMB is off. 222, and a mask circuit 223 that performs a mask operation in response to the activation state of the mask signal m2 and the logic 1 of R5 of the run signal R.

In operation, the lower 7 bits L0 to L6 of the level signal L are supplied to the conversion circuits 21 and 22 in parallel. At the same time, the lower R0 to R2 of the 6 bits R0 to R5 of the run signal R are supplied to the conversion circuit 21 by all the R0 to R5.
R5 is supplied to the conversion circuit 22, respectively. When the absolute value of the level signal L is 16 or more, that is, when one or more of L4, L5, and L6 is supplied, the value of the run signal R is other than 0, and Is activated, the mask signal m1 is activated and supplied to the mask circuit 212. The mask circuit 212 sets all output signals to logic 1 in response to the activation state of the mask signal m1, otherwise, the lower 3 bits R0 to R2 of the run signal R and the lower 4 bits L0 to L3 of the level signal L Are supplied to the output selection circuit 23.

The MSB output circuit 221 is activated when the value of the level signal L is 2 and the value of the run signal R is 8 to 15, and outputs the signal MB which is the MSB of the output signal to the output selection circuit 2.
3 and the mask signal generation circuit 222. The mask signal generation circuit 222 determines that the value of the level signal L is other than 1 and M
The mask signal m2 is supplied to the mask circuit 223 when the SB output circuit 221 is in the inactive state. Mask circuit 223
Means that all output signals are set to logic 1 when the mask signal m2 is in an activated state and when the MSB of the run signal R, that is, R5 is logic 1, and otherwise, the lower 5 bits of the run signal R
The bits R0 to R4 are supplied to the output selection circuit 23.

The selection signal generating circuit 24 determines that the run signal R is 0
If it is 〜7, logic 0 is supplied to the output selection circuit 23 as a selection signal S otherwise. The output selection circuit 23 responds to the logic 0 of the selection signal S,
In response to the logic 1, the output of the conversion circuit 22 is selected, and the address signals b0 to b6 are output.

As a result, the number of bits of the address signal b can be reduced in the bit conversion circuit 2, and the memory size of the ROM 3 is reduced to reduce the circuit scale to about 1.5K gates in terms of gates, ie, about 1/100 of the conventional size. Since it can be reduced to 80, it is easy to implement an LSI.

[0023]

As described above, the variable length coding circuit according to the present invention is a bit conversion circuit for generating a reduced address signal in which the number of bits is smaller than the sum of the respective bits of the level absolute value signal and the run signal. When, by providing a conversion table ROM which stores a small code conversion table of the reduced address signal corresponding, the conversion table ROM
Required memory capacity can be greatly reduced , and the circuit scale can be reduced, so that there is an effect that the LSI can be easily implemented.

Further, there is an effect that the power consumption can be reduced and the operation speed can be increased by reducing the circuit size.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a variable length coding circuit according to the present invention.

FIG. 2 is a circuit diagram showing details of a bit conversion circuit of FIG. 1;

FIG. 3 is a block diagram showing an example of a conventional variable length coding circuit.

[Description of Signs] 1 Absolute value circuit 2 Bit conversion circuit 3, 3A ROM 4 Decoder circuit 5 Positive / negative sign addition circuit 21, 22 Conversion circuit 23 Output selection circuit 24 Selection signal generation circuit 211, 222 Mask signal generation circuit 212, 223 Mask Circuit 221 MSB output circuit

Claims (2)

(57) [Claims] 1. An input image data is divided into a two-dimensional block composed of a matrix having a predetermined number of pixels, and quantized image data obtained by orthogonally transforming and quantizing each of the two-dimensional blocks is supplied. A code for searching for a code word corresponding to a combination of a run signal that is a coefficient value of consecutive zeros and a level signal that is a non-zero value following the run signal
Using a conversion table, the run signal and the level signal
A variable-length encoding device that performs variable-length encoding using a Huffman code that determines the codeword in response to a supply; an absolute value circuit that converts an value of the level signal into an absolute value to generate an absolute value signal; a bit conversion circuit for generating receiving a shortened address signal with a reduced number of bits in these absolute value signal and the run signal each style predetermined than the sum of the number of bits of the supply of the absolute value signal and the run signal, the shortening a conversion table ROM for outputting the code length signal indicative of the code length code word signal of a predetermined code length by access to store the code conversion table in the address signal corresponding this short address signal, the code length signal and A decoder circuit for outputting a positive / negative sign signal in response to the supply of the level signal; and a sign circuit receiving the supply of the positive / negative sign signal and the code word signal. Variable-length coding circuit, characterized in that it comprises a sign adding circuit for outputting a variable-length code word signal. 2. A first conversion circuit , wherein the bit conversion circuit generates the shortened address signal when the value of the run signal is equal to or less than a predetermined set value; the short when the value is equal to or larger than the set value
A first conversion circuit for generating a reduced address signal, a selection circuit for selecting one of the outputs of the first and second conversion circuits and outputting the shortened address signal in response to a value of the selection signal; The value of the selection signal is set to logic 0 in accordance with the value of the run signal.
2. A variable length coding circuit according to claim 1, further comprising a selection signal generation circuit for setting the value to one of a logic 1 and a logic 1.